amd geode lx epic rdk.pdf
TRANSCRIPT
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COVER PAGE
Page Index
IMPORTANT NOTES ABOUTTHIS SCHEMATIC
2) DESIGN NOTES inyellow are notes ofcaution.
3) DESIGN NOTES inred are critical, andmust be understood andfollowed.
1) DESIGN NOTES ingrey are informationnotes.
1) UNLESS OTHERWISE SPECIFIED RESISTORS HAVE 5% TOLERANCE.NOTES:
1------- ------------------------
REVISION HISTORY
BLOCK DIAGRAM
POWER ON & RESET SEQUENCE
PCI & JTAG BLOCK DIAGRAM
DDR SODIMM CONNECTOR
LX PROCESSOR DDR MEMORY
LX PROCESSOR VGA
LX PROCESSOR PCI / SYSTEM
LX PROCESSOR POWER
CS5536 PCI / SYSTEM / PM / FWH
CS5536 IDE / USB / AC97 / LPC
CS5536 POWER & CLOCK GENERATOR
VGA CONNECTOR
ETHERNET CONN / USB CONN & PWR / uDOC
AUDIO CODEC REALTEK ALC655
ETHERNET - 10 / 100 MICREL KSZ8842
IDE CONNECTOR
POWER SUPPLIES
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AMD Geode LX EPIC RDK Reference Schematic
------- ------------------------Page Index
2) UNLESS OTHERWISE SPECIFIED CAPACITORS HAVE 20% TOLERANCE.MINI PCI
20
21
PCI TO ISA BRIDGE ITE IT8888G
22
23
24
25
PC104 CONNECTORS
PARALLEL PORT, KEYBOARD, & MOUSE
UART & FLOPPY CONNECTORS
SUPER IO ITE IT8712F & SPI BOOT FLASH
26 TFT & LVDS CONNECTORS
2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOUT NOTICE.CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR APARTICULAR USE.
1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENTAND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULDCONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE, ORPROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOMMENDATIONS AND PCB LAYOUTGUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAMAND PCB LAYOUT BEFORE CONSIDERING PRODUCTION.
2007 ADVANCED MICRO DEVICES, INC. ALL RIGHTS RESERVED. AMD, THE AMD ARROW LOGO,AMD GEODE, AND COMBINATIONS THEREOF ARE TRADEMARKS OF ADVANCED MICRO DEVICES,INC. OTHER NAMES USED IN THIS PUBLICATION ARE FOR IDENTIFICATION PURPOSES ONLYAND MAY BE TRADEMARKS OF THEIR RESPECTIVE COMPANIES.
IMPORTANT NOTICE:
3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESSFOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT,SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PERFORMANCE,OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION.
DESIGN NOTE: Exampletext for the design note toshow the note inside thecolored box.
DESIGN NOTE: Exampletext for the design note toshow the note inside thecolored box.
DESIGN NOTE: Exampletext for the design note toshow the note inside thecolored box.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 1 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
REVISION HISTORY:
A Initial Release*07-09-2006REV DATE NOTES------- ------------------ ---------------------------------------------------------------------------------------
12-04-2006 * Page 8 - Changed LX symbol - DRGB6 pin from Y32 to AH8BC 01-19-2007
** Page 10 - Connected C102-C108 to Ground
Page 13 - Connected C133-C137 and C149-C152 to GroundD Page 13 - Added design note regarding USB VCORE supply.*04-10-2007
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 2 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEMORY BUS
Clock
AMD GeodeLX Processor
DC/DC
REFCLK
AMD Geode CS5536
PCI(33 MHz)
Companion Device
14.318 MHzCrystal Synthesizer
(MK1491-09F)
66 MHz
48 MHzSIO
AUDIO CODEC5.1 SUPPORT
AC97
VCORE(1.25V)
VCC3 (3.3V)VMEM (2.6V)
VCORESB (1.225V)VCC3SB (3.3V)
VCC5SB
CRT
TFTLVDS
HD/CD X2
uDOC FLASH STORAGE
CLIENT X1
PRIMARY IDE ATA-100
USB2.0HOST X1
MONITOR
BASEBOARD ONLY
SODIMM200 DDR
PCI BUS (33MHz)
10 / 100ETHERNET 2 PORT
PCI TO ISA BRIDGE
FULL ISA
SPI BIOSFLASH
LEGACYPARALLEL SERIAL KB/MS
VCC5
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 3 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIRST#
10K
Power On and Reset Sequence - Cold start
VCC=+5.0VSYSTEM POWER
SYS_RST#
AMDGeodeCS5536
AMDGeode LX Processor
PCIRST#
10K
DC/DC
VCORE @ 2A Max
EN
EN
DC/DCVCC3 @ 2A Max
LM317LINEAR
VCC3SB
470
WORK AUX
PWRBTN# WORKING
PWRBTN#WORKING
VCC3SB
LM4041
VCORESB
VCCMEM MVREF
DESIGN NOTE: This design usesLVD to generate system reset.Since LVD only monitors Vcore,the designer must guarantee thatVio and other required voltagesare valid at or before Vcore. If thiscannot be guaranteed, thenRESET_WORK# must be used tohold system in reset until Vio andVcore and any other requiredvoltages are valid.
LVD_EN#
5V
5V
WORK AUX
AOZ1012
5VSBDC/DC
EN
VMEM @ 2A Max
WORKING
AOZ1012
AOZ1012
5VSB
VCC3_EXT=+3.30V - PC104 SLOTS
VCORE=+1.25V
VIO=+3.30V
VIO=+3.30VMVREF=+1.3V
AMD Geode LX Processor
VCCMEM=+2.60V
AMD Geode CS5536
VCORESB=+1.225V
MVREF=+1.3VVMEM=+2.60V
VCORE=+1.25V
MEMORY
VCC3=+3.30V - BASEBOARD
5V5VSB 3.3VSB1.225VSBVCC3VCOREVMEM
LVD
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 4 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TMS
TCK
FS2 HEADER
PCI MASTER SETTING
TMS
AMDGeode LXProcessor
TDITDO
TDI
TDO
TCK
AMD GEODE LX PROCESSOR
TDI
AMD GEODE CS5536
TDEBUG_OUTTDEBUG_IN
TDEBUG_IN
TDO
TDEBUG_OUTTDEBUG_OUT
MK1491-09TCK
TMS
PCI CLOCK SETTING
JTAG DAISY CHAIN MODE WITH AMD GEODE CS5536 COMPANION DEVICECLOCK
TDEBUG_IN
GENERATORSEL66_33#
REQ2#/GNT#2
Expander
REQ_EXT0#/GNT_EXT0#
AMD Geode CS5536
PCI to ISA Bridge
Mini PCI
ExpanderREQ0#/GNT#0
REQ_EXT1#/GNT_EXT1#
REQ_EXT2#/GNT_EXT2# PC104 Slot 3Ethernet Controller
PC_REQ0#/PC_GNT0#
PC_REQ1#/PC_GNT1#
PC_REQ2#/PC_GNT2#
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2
REQ1#/GNT#1Jumpers to select2 of the 3 devices
CLK_CPUAMD Geode LX ProcessorAMD Geode CS5536
CLK_IOC
PCI 66 MHz
PCI 33 MHz0
1
FunctionSEL66_33#
CLK_EXT0
Expander
Not Used
PC104 Slot 1
PC104 Slot 3
PC_CLK
CLK_EXT
PC_CLK0
PC_CLK1
Mini PCIEthernet Controller
PC_CLK3
PC104 Slot 0
PC104 Slot 2
CLK_EXT1
CLK_EXT3
CLK_EXT2Expander
PC_CLK2
PCI to ISA Bridge
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 5 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE:Use SDCLKpairs that aremost convientfor clean routing.
DESIGN NOTE: Place DQS andDQM series resistors as closeto the SODIMM connector aspossible.
DESIGN NOTE: Place addressand control series resistors as close to the processor aspossible.
DESIGNNOTE: Placedata bus seriesresistors asclose to thememorydevices aspossible.
DESIGNNOTE: Swap seriesresistors onthe data linesin orderminimize the number ofvias.
Vout = 1.30
DESIGN NOTE:Swap seriesresistors on theDQS lines inorder minimizethe number ofvias.
DESIGNNOTE: Swap seriesresistors onthe addresslines in orderminimize thenumber ofvias.
DESIGN NOTE: BA0,BA1must be trace lengthmatched to within 50 mils.
DESIGN NOTE: This schematic shows anon-parallel terminated DDR solution.There may be restrictions as to the totalnumber of DRAMS and the number ofbanks supported on the SODIMM. See LXlayout guidelines for current restrictions.
DESIGN NOTE:Do not swapseries resistorson the DQS,DQM or Datalines with theAddress orcontrol lines.
DESIGN NOTE: See LXlayout guidelines forlatest recommendationson memory routing.
AMD GEODE
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 6 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
MD54MD50
MDQM7
MD61
MA8
MDQS7
MA9
MA7
MRAS#
MCAS#
MA6
MD60
MD51MD55
MDQS6
MD56
MWE#
MDQM6
MD57
MD53
MD52MD48
MD49
MCS0#MCS1#
MA4MA5
MA3MA2
MBA1MA10
MA0MA1
MD18
MD25
MDQS1
MD6
MD38
MDQM1
MD7
MD36
MD30
MD9
MD5
MD4
MD41
MD20MD17
MD31
MD11
MDQS5
MD10
MD2
MDQM2
MDQS4
MD39
MD37
MD16
MDQM5
MD24
MD12
TLA1
MD21
MD8
MD44
MD42
MD40
TLA0
MD23
MDQS2
MD46
MD19
MD27
MD45
MD33
MD34
MD28
MD26
MD15
MD0
MDQM3
MD43
MD29
MD3
MD32
MD35
MDQM4
MD22
MD14
MD13
MD1
MD47
MDQS3
MA11MA12
MCKE0
MD63MD59
MD58
MD54
MD41
MD39
MD32
MD22
MD18
MDQM0
MA9
MA6
MDQS7
MD46
MD33
MD29
MD5
MDQM1
MDQS4MDQS3MDQS2
MD53
MD7
MDQS0
TLA1
MD51
MD45
MD20
MD13
MBA1
MD40
MD36
MA13
MA3
TLA0
MWE#
MD34
MD16
MD12
MD0
MD56
MD48
MD44
MD31
MD23
MDQM6
MA0
MCS1#
MA11
MDQS1
MRAS#
MD27
MD10
MCKE0
MD52
MD38MD37
MDQM7
MBA0
MA2
MDQS5
MCAS#
MD61
MD43
MD35
MD15
MD1
MDQM2
MD63
MD60
MD19
MD9
MD6
MD59
MD55
MD47
MD30
MD28
MD21
MD17
MD62
MD57
MD3
MA7
MCS0#
MD50
MD26MD25MD24
MD11
MD8
MD4
MDQS6
MDQM5MDQM4
MA12
MA4MA5
MA1
MD49
MD42
MD14
MD2
MDQM3
MA10
MA8
MDQS0MDQM0
MD62MD58
MBA0
MA13
SDCLK07
SDCLK27
SDCLK2#7
SDCLK4#7
SDCLK0#7
SDCLK47
RMD5 7
RMD0 7
RMD1 7
RMD2 7
RMD3 7
RMD4 7
RMD6 7
RMD7 7RMD8 7
RMD9 7
RMD10 7
RMD11 7
RMD12 7
RMD13 7
RMD14 7
RMD15 7
RMD16 7
RMD17 7
RMD18 7
RMD19 7
RMD20 7
RMD21 7
RMD22 7
RMD23 7RMD24 7
RMD25 7
RMD26 7
RMD27 7
RMD28 7
RMD29 7
RMD30 7
RMD31 7
RMD32 7
RMD33 7
RMD34 7
RMD35 7
RMD36 7
RMD37 7
RMD38 7
RMD39 7RMD40 7
RMD41 7
RMD42 7
RMD43 7
RMD44 7
RMD45 7
RMD46 7
RMD47 7
RMD48 7
RMD49 7
RMD50 7
RMD51 7
RMD52 7
RMD53 7
RMD54 7
RMD55 7RMD56 7
RMD57 7
RMD58 7
RMD59 7
RMD60 7
RMD61 7
RMD62 7
RMD63 7
RMDQM0 7
RMDQM1 7
RMDQM2 7
RMDQM3 7
RMDQM4 7
RMDQM5 7
RMDQM6 7
RMDQM7 7
RMDQS0 7
RMDQS1 7
RMDQS2 7
RMDQS3 7
RMDQS4 7
RMDQS5 7
RMDQS6 7
RMDQS7 7
RTLA0 7RTLA1 7
RMA0 7RMA1 7
RMA2 7RMA3 7RMA4 7RMA5 7
RMA6 7RMA7 7RMA8 7RMA9 7
RMA10 7
RMA11 7RMA12 7
RMA13 7RMCS0# 7RMCS1# 7
RMCAS# 7
RMRAS# 7RMWE# 7
RMBA0 7
RMBA1 7
RMCKE0 7
DGND
MVREF
DGND DGND
MVREF
VCCMEM
RN2333
12345
678
RN733
12345
678
RN1733
12345
678
R110K
1
RN633
12345
678
RN2433
12345
678
RN1933
12345
678
C2
100nF
1
RN1533
12345
678
RN2633
12345
678
RN1622
12345
678
RN933
12345
678
RN2522
12345
678
RN1333
12345
678
RN133
12345
678
RN333
12345
678
RN1422
12345
678
RN233
12345
678
RN833
12345
678
RN1822
12345
678
RN1233
12345
678
RN433
12345
678
R210K
1
RN2222
12345
678
RN2733
12345
678
RN2022
12345
678
RN533
12345
678
RN1133
12345
678
U1A
LX PROCESSOR
C13
F30
C17C15
D11D12
D8D9D6
D19D5
C16
D13
C5
M1G2A6 D26
C20B10A19
H29N30
C24
P2N2M3K2P3N1L3K1J2J1F3E3J3G1F2F1D2B4B6C8D1A4A7B7B9C10A12B12A9C9C11A13A15B17B19B22B16A17B20A20A22A23A25A26C22C23B25B26D31F31K30K31G30G31J31J30M31M30R30R31L29M29P30R29
E4F4
B28F28F29D30
E28E29C26D27
M4J4
M28J28D23D20
C27A28
L4H4
L28H28D24D21
B15B13
M2H3C6
A10C19B23J29N31
P1
MA3
MA13
MA1MA2
MA5MA6MA7MA8MA9MA10MA11
MA0
MA4
MA12
DQM0DQM1DQM2 BA0
BA1DQM3DQM4
DQM6DQM7
DQM5
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63
CKE0CKE1
CS0#CS1#CS2#CS3#
CAS0#CAS1#RAS0#RAS1#
SDCLK0PSDCLK1PSDCLK2PSDCLK3PSDCLK4PSDCLK5P
WE0#WE1#
SDCLK0NSDCLK1NSDCLK2NSDCLK3NSDCLK4NSDCLK5N
TLA0TLA1
DQS0DQS1DQS2DQS3DQS4DQS5DQS6DQS7
MVREF
RN1033
12345
678
RN2133
12345
678
C1
100nF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: This schematicshows a non-parallel terminatedDDR solution. There may berestrictions as to the total numberof DRAMS and the number of bankssupported on the SODIMM. See LXlayout guidelines for currentrestrictions.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 7 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
RTLA06
RTLA16
RMBA16RMBA06
RMCS1#6RMCS0#6
RMCKE06
RMCAS#6RMRAS#6
RMWE#6
SDCLK0#6
SDCLK2#6
SDCLK06
SDCLK26
SMB_SCL12SMB_SDA12
SDCLK4#6SDCLK46
RMD0 6RMD1 6RMD2 6RMD3 6
RMD5 6
RMD7 6RMD6 6
RMD4 6
RMD9 6RMD10 6
RMD8 6
RMD11 6
RMD17 6RMD16 6
RMD19 6
RMD14 6RMD13 6RMD12 6
RMD18 6
RMD15 6
RMD21 6
RMD27 6RMD26 6
RMD29 6
RMD24 6RMD23 6RMD22 6
RMD28 6
RMD25 6
RMD20 6
RMD31 6
RMD37 6RMD36 6
RMD39 6
RMD34 6RMD33 6RMD32 6
RMD38 6
RMD35 6
RMD30 6
RMD41 6
RMD47 6RMD46 6
RMD49 6
RMD44 6RMD43 6RMD42 6
RMD48 6
RMD45 6
RMD40 6
RMD51 6
RMD57 6RMD56 6
RMD59 6
RMD54 6RMD53 6RMD52 6
RMD58 6
RMD55 6
RMD50 6
RMD61 6
RMD63 6RMD62 6
RMD60 6
RMDQS06
RMA06
RMDQM06
RMDQS16RMDQS26RMDQS36RMDQS46RMDQS56RMDQS66RMDQS76
RMA16RMA26RMA36
RMA76
RMA56RMA66
RMA46
RMA116
RMA96RMA106
RMA86
RMA126
RMDQM16RMDQM26RMDQM36
RMDQM66RMDQM56
RMDQM76
RMDQM46
RMA136
DGND
VCCMEM
MVREF
DGND
VCCMEM
DGND
VCCMEM
C18
1nF
1
C9
1nF
1
C24
1nF
1
C8
100pF
1
C28
10nF
1
C27
10nF
1
C21
10nF
1
C20
10nF
1
C11
22uF
1
C7
100pF
1
C17
1nF
1
J1B
SODIMMDDR-SODIMM-200P-RVS
1491381371261251041039088877675646352514039
2827161543
12
91021223334
4546575869708182929394
113114131132143144155156
167168179180191192
197
38
150159161162173174185186
36
157
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
VSSVSSVSSVSSVSSVSS
VREFVREF
VDDVDDVDDVDDVDDVDD
VDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDDVDD
VDDVDDVDDVDDVDDVDD
VDDSPD
VSS
VSSVSSVSSVSSVSSVSSVSSVSS
VDD
VDD
C3
22uF
1
C26
1nF
1
C13
100pF
1
C30
10nF
1
R3 10K1
C10
22uF
1
C15
100pF
1
C23
10nF
1
C6
100pF
1
C19
1nF
1
J1A
DDR-SODIMM-200P-RVSSODIMM
571317681418192329312024303241434953424450545559656756606668127129135139128130136140141145151153142146152154163165171175164166172176177181187189178182188190
112111110109108107106105102101115100
99
97
3537
71
73
79
83
72
74
80
84
12264862
134148170184
78
9695
8586
8991
160158
117116
98
194196198
193195
118120119
121122
123124
200
11254761
133147169183
199
77
DQ00DQ01DQ02DQ03DQ04DQ05DQ06DQ07DQ08DQ09DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63
A0A1A2A3A4A5A6A7A8A9A10/APA11A12
RFU
CK0CK0#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM0DM1DM2DM3DM4DM5DM6DM7
DM8
CKE0CKE1
RFURFU/RESET
CK2CK2
CK1CK1#
BA0BA1
RFU
SA0SA1SA2
SDASDL
RAS#CAS#WE#
S0#S1#
RFU/A13RFU
RFU
DQS0DQS1DQS2DQS3DQS4DQS5DQS6DQS7
VddID
DQS8
C16
1nF
1
C25
1nF
1
C5
100pF
1
C4
22uF
1
C12
100pF
1
C29
10nF
1
C14
100pF
1
C22
10nF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: AGND_VGA should be anisland with single point connection to thefull ground plane to reduce noise content.Zero ohm resistor can be removed aslong as above condition is met.
AMD GEODE
High SpeedInput Port
TSSOP56 Package
DESIGN NOTE: There are two conventionsfor connecting 24 bit panels. One is backwardcompatible with 18 bit panels. The connectionsdefined here are backwards compatible.
24-bit LVDS Transmitter
DESIGN NOTE: For 18-bit panels use OUT0,OUT1, and OUT2. For 24-bit panels useOUT0, OUT1, OUT2, and OUT3.
DESIGN NOTE: The LSB's foreach color (R0,R1,G0,G1,B0,B1)are not used in by 18-bit panels.
DESIGN NOTE: When using 16 data capturemode (Mode 4 - BT.601), the TFT interfacecannot be used due to pin sharing conflicts.
DESIGN NOTE: 8-bit Data StreamingMode is the simplest data input mode,but is limited to 8-bits.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 8 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
DACVDD
HSIP_D7HSIP_D6HSIP_D5HSIP_D4HSIP_D3HSIP_D2HSIP_D1HSIP_D0
HSIP_D11HSIP_D10
HSIP_D15
HSIP_D12HSIP_D13
HSIP_D9
HSIP_D14
HSIP_CLKHSIP_SYNC
HSIP_HSYNC
HSIP_HSYNC
TFTCLK
HSIP_D5
HSIP_D11
HSIP_D4
HSIP_D8
HSIP_D13HSIP_D14
HSIP_D6
HSIP_D0HSIP_D1HSIP_D2
HSIP_D10HSIP_D9
HSIP_D3
HSIP_D12
HSIP_CLK
HSIP_D15
HSIP_D7
HSIP_SYNC
LDEMOD_HSIP_VSYNC
TFT_R2TFT_R3TFT_R4TFT_R5TFT_R6TFT_R1
TFT_G2TFT_R7
TFT_G4TFT_G0
TFT_G5TFT_G1
TFT_G6TFT_G7
TFT_G3
TFT_R0
TFT_B4
TFT_B2
TFT_B1
TFT_B7TFT_B6
TFT_B0
TFT_B5
TFT_B3
HSYNC_CVSYNC_C
TFTCLK
LDEMOD_HSIP_VSYNC
DISPEN
DISPENR_F_CLK
R_F_CLK
LDEMOD_HSIP_VSYNC
VSYNC_C
HSYNC_C
TFT_G3
TFT_R5
TFT_R4
TFT_R2
TFT_G1
TFT_R7TFT_G0
TFT_B6TFT_B7
TFT_R3
TFT_R1
TFT_R0
TFT_G6
TFT_G7
TFT_G5
TFT_R6
TFT_G4
TFT_G2
HSIP_D8
TFT_B0
TFT_B1
TFT_B2
TFT_B3TFT_B4TFT_B5
T_B0T_B1T_B2T_B3T_B4
T_G0
T_B5
T_B7T_B6
T_G4
T_G1
T_G3T_G2
T_R0
T_G5
T_G7T_G6
T_R4
T_R1
T_R3T_R2
T_R0
T_R4
T_R2T_R3
T_R5
T_B6
T_R6T_B7
T_B5
T_B0
T_B4T_B3
T_G5
T_B2
T_B1T_G7
T_G6
T_G1
T_G3T_G4
T_R1
T_G2
T_G0T_R7
T_R5T_R6T_R7
HSYNC_C
VSYNC_C
BLUE 14
GREEN 14 VSYNC 14
HSYNC 14
TXCLKOUT- 26TXCLKOUT+ 26
TXOUT0- 26
TXOUT1- 26
TXOUT2- 26
TXOUT3- 26
TXOUT1+ 26
TXOUT2+ 26
TXOUT3+ 26
TXOUT0+ 26
TFTCLK26
LDEMOD_HSIP_VSYNC 26DISPEN 26HSIP_HSYNC 26
TFT_R426TFT_R326TFT_R226
TFT_G726
TFT_G626
TFT_G526
TFT_G426TFT_G326
TFT_G226
TFT_B726
TFT_R726
TFT_R626
TFT_B626
TFT_R526
TFT_B226
TFT_B326TFT_B426TFT_B526
RED 14
HSYNC_C 26
VSYNC_C 26
DGND
VCC3
AGND_VGA
AGND_VGA
AGND_VGA
DGND
VCC3VCC5
DGND
LVDS_PGND
LDVS_AGND
VCC3
LVDS_AVCC3
LVDS_PVCC3
VCC3
VCC3
DGND LVDS_PGND
LVDS_PVCC3
DGND
VCC3
LDVS_AGND
LVDS_AVCC3
DGND
VCC3
DGND
VCC3
DGND
DGND
R7 01
R8 01
RN70 2212345
678
R30 221
U26C
LX PROCESSOR
V2
U2
W3
AH13
AJ2
AJ4
AJ11
AJ13
AJ15
AK3
AH8AJ8
AH11
AK4AJ5AF2AF1AG3AG4AH1AH2
AJ1
AH7
AJ7AK7
AJ10AH10
AK10
AK12
AK13
AH3
AL13
AK15
AH5AL3
AL4
AK6AL6
AL7
AL9
AL10
AL15
V4
Y2
W1
U1
Y1
W4
AE1
U3V3
V1
W2
AD3AE3
AL12AL14
AK9
AD4AE4AE2
GREEN
BLUE
RED
VID3
DRGB8/VOP15
DRGB12/VOP11
DRGB25/VID9
VID4
VID0
DRGB9/VOP14
DRGB6/VOP1DRGB7/VOP0
DRGB24/VID8
DRGB14/VOP9DRGB15/VOP8DRGB16_VOP23DRGB17_VOP22DRGB18_VOP21DRGB19_VOP20DRGB20_VOP19DRGB21_VOP18
DRGB23_VOP16
DRGB0/VOP7
DRGB3/VOP4DRGB4/VOP3
DRGB28/VID12DRGB29/VID13
DRGB26/VID10
VID7
VID5
DRGB22_VOP17
VID6
VID1
DRGB11/VOP12DRGB10/VOP13
DRGB13/VOP10
DRGB1/VOP6DRGB2/VOP5
DRGB5/VOP2
DRGB30/VID14
DRGB27/VID11
VID2
DAVDD
DAVSS
DVREF
DAVDD
DRSET
DAVDD
DOTCLK/VOPCLK
DAVSSDAVSS
DAVDD
DAVSS
VSYNC/VOP_VSYNCHSYNC/VOP_HSYNC
VIPCLKVIPSYNC
DRGB31/VID15
LDEMOD/VIP_VSYNCDISPEN/VOP_BLANKVDDEN/VIP_HSYNC
FB2
BLM18PG600SN1
1 2FB1
BLM18PG600SN1
1 2
RN73 2212345
678
C35
10nF
1
C34
10nF
1
J3
PFL-2x20-2M0-SMD-S
246810
13579
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
RN71 2212345
678
R29 221
R10 0_NL1
C36
10uF
1
C39
10nF
1
U2
DS90C385
5152545556
234678
1011121415161819202223242527283050
311732
4039
4847
4645
4241
3837
44
34
1926
364349
3335513212953
IN00IN01IN02IN03IN04IN05IN06IN07IN08IN09IN10IN11IN12IN13IN14IN15IN16IN17IN18IN19IN20IN21IN22IN23IN24IN25IN26IN27
CLKINR_FBPD
CLKO-CLKO+
OUT0-OUT0+
OUT1-OUT1+
OUT2-OUT2+
OUT3-OUT3+
LVCC
PVCC
VCCVCCVCC
LGNDLGNDLGND
PGNDPGND
GNDGNDGNDGNDGND
R4 11
C33
10uF
1
RN74 2212345
678
R9 01
U22NC7SZ125/SC70
2 4
5
3
1
C40
100nF
1
R510K
1
D1
LM4041AIM3-1.2
2
1
3
C41
10nF
1
U23NC7SZ125/SC70
2 4
5
3
1
RN72 2212345
678
RN69 2212345
678
R60110
1
R61.2K
1
C38
100nF
1
C37
10uF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Off
Off
OffOn
On
OnOff
OffOn
On
5
4
3
2
1
DESIGN NOTE:COREPLLGND, DOTPLLGNDand GLPLLGND should eachbe an island with single pointconnection to the full groundplane to reduce noise content.Zero ohm resistor can beremoved as long as abovecondition is met.
5 4 3 2 1 CORE MEM--- --- --- --- --- --- ---Off On Off Off Off 500 400 Off On Off Off On 500 333 Off On On On On 433 333 On On On On On Bypass Bypass
DESIGN NOTE: There are 8 PCIdevices in this design requireing REQ/ GNT pairs. Two 1 to 3 expandersare provided, giving a total of 7 pairs.Two pairs are mapped to the followingthree devices: Ethernet, MiniPCI andPC104 slot 3. Jumpers are providedto select.
AMD GEODE
AMD GEODE
DebugStall
NormalSetting
DESIGN NOTE: Add"JTAG HEADER" tothe silkscreenJTAG HEADER
DESIGN NOTE: Two REQ/GNT pairs are mappedto the following three devices: Ethernet, MiniPCIand PC104 slot 3. Jumpers are provided to select.
DESIGN NOTE: CLKFB outputis used internally by the 8209 toproduce the zero delay.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 9 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
PW0
GLPLLVDD
JTAGTMS
TDBGI_CPU
PW1
DOTPLLVDD
TDBGI_CPU
SUSPA#
COREPLLVDD
DOTPLLVDD
SUSPA#
JTAGTMS
GLPLLVDD COREPLLVDD
TDBGO_CPU
PW0
JTAGTCK
JTAGTDI
PCI_AD24
PCI_AD18PCI_AD17
PCI_AD9
PCI_AD3
PCI_AD26
PCI_AD16
PCI_TRDY#
PCI_AD14
REQ2#
REQ0#
PCI_AD25
PCI_AD20
GNT0#
PCI_DEVSEL#
PCI_AD11
PCI_AD8
PCI_AD2
PCI_AD23
PCI_AD13
PCI_AD0
PCI_AD10
PCI_AD4
PCI_AD7
PCI_AD29
PCI_AD12
REQ1#
PCI_FRAME#
PCI_AD19
PCI_AD5
PCI_AD27
PCI_AD31
PCI_AD22
PCI_AD1
PCI_AD15
PCI_STOP# PCI_AD30
PCI_AD28
PCI_AD21
PCI_RST#
PCI_IRDY#
GNT0#
PCI_AD6
REQ2#
PCI_DEVSEL#
PCI_IRDY#
PCI_STOP#
PCI_TRDY#PCI_FRAME#
GNT1#
GNT2#
GNT2#
IRQ13
IRQ13
GNT1#
PCI_FRAME#PCI_STOP#
REQ1#
REQ_EXT0#
GNT1#
PCI_RST#
CLKFB_EXT
GNT_EXT2#GNT_EXT1#
TDBGI_CPUTDBGO_CPU
JTAGTDI
REQ_EXT1#REQ_EXT2#
REQ_EXT2#
REQ_EXT1#
GNT_EXT1#
GNT_EXT2#
REQ0#REQ1#
REQ_EXT1#REQ_EXT2#
REQ_EXT0#
CLKFB_EXT
PW1
JTAGTCK
JTAGTDI
PCI_PAR 11,15,19,20,24
PCI_AD[31:0] 11,15,19,20,24
CLK_48_DOT12
SUSPA#11
CIS11
CLK_CPU13
PCI_INTA#11,19,24
REQ2#11
PCI_FRAME#11,15,19,20,24
PCI_DEVSEL#11,15,19,20,24
PCI_C/BE2#11,15,19,20,24
PCI_RST#11,12,15,16,17,19,20,24,25
PCI_IRDY#11,15,19,20,24
PCI_C/BE1#11,15,19,20,24PCI_C/BE0#11,15,19,20,24
PCI_STOP#11,15,19,20,24
GNT2#11
PCI_TRDY#11,15,19,20,24
PCI_C/BE3#11,15,19,20,24
GNT0#24
REQ0#24
REQ_EXT0#20
IRQ1311
TDO_CPU 12
GNT_EXT0# 20
CLK_EXT1 19CLK_EXT0 20
CLK_EXT13
TDP17TDN17
JTAGTCK 12
JTAGTDO 12
JTAGTMS 12
SYS_RST# 11,17,25
REQ#_PC3 24
REQ#_LAN 15REQ#_MPCI 19
GNT#_LAN 15GNT#_MPCI 19GNT#_PC3 24
CLK_EXT2 15
GLPLLGND
DPLLGND
CPLLGND DGND
DGND
DGND
VCC3
CPLLGND VCC3
GLPLLGND
DPLLGND VCC3
VCC3
VCC3
DPLLGND
GLPLLGND
CPLLGND
VCC3
DGNDVCC3
VCC3_EXT1
GND_EXT1
DGND DGND
VCC3
VCC3
DGND GND_EXT1
VCC3_EXT1
VCC3
DGND
DGND
R33 11
RN28
4.7K
1234 5
678
R12 1K1
R32 01
C45
220pF
1
R15 10K_NL1
R36 01
C54
10nF
1
RN68 10K1234 5
678
C51
10nF
1
J7
PFL-7X2
2468101214
13579
1113
R16 1K1
R22 10K1
R35 01
U1B
LX PROCESSOR
AJ24
AJ27
AJ28
AH30AH29AG29AG28AF30AE28AF31AE30AE31AD29
AJ30
AJ31
AK25
AK28
AK29
AL23AL25
AL28
AL29
AJ19AH19AL20AK20AK19AH21AJ21AL19AK22AL22AK23AH22
AH24
AJ25
AJ22
AH27AH31
AA29AB31AB28
AA28AB30AC30
Y30
AL26
AH25AK26
AD15
PAR
AD16
AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
AD19
AD21
DEVSEL#
AD17
AD20
AD12AD13
FRAME#
AD18
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9
AD10AD11
AD14
STOP#
CBE0#
CBE2#CBE3#
REQ0#REQ1#REQ2#
GNT0#GNT1#GNT2#
RESET#
CBE1#
IRDY#TRDY#
C52
10nF
1
C42
10uF
1
U1D
LX PROCESSOR
AB1
AB29
AC31
AE29
AB2
AJ17AL18
AD28
AL17AK17
AB4
AA2AA1
V31V30
W31W30
Y31
W29V29AA3
AB3AA4AC1AC2
DOTREF
IRQ13
SUSPA#
CIS
TDBGI
PW1PW0
INTA#
TDPTDN
TDBGO
VAVSSVAVDD
MAVDDMAVSS
CAVDDCAVSS
SYSREF
CLPFMLPFVLPF
TDITMSTDO
TCLK
R38 01
RN54 10K1234 5
678
C55
10nF
1
C50
10uF
1
R13 10K_NL1
C56
10uF1
C47
220pF
1
R21 1K_NL1
C43
100nF
1
R34 11
R14 1K1
J6
PFL-2x6-2M0-SMD-S
246810
13579
11 12
R20 1K1
C48
10nF
1
J5
PFL-2x6-2M0-SMD-S
246810
13579
11 12
R17 10K_NL1
R37 11
C53
10uF
1
U3
IT8209R
58
11
7101234
12
2627
22201918
23
2
1
2
8
1
7
2
4
2
5
13
14 15
16
9
6
REQ1REQ2REQ3
GNT1GNT2GNT3
S_REQS_GNT
FRAMESTOP
RESETCLKIN
CLK1CLK2CLK3CLK4
CLKFB
V
C
C
A
V
C
C
V
S
S
V
S
S
A
V
S
S
NC
NC NC
NC
V
C
C
V
S
S
C44
10nF
1
R31 10K1
C46
220pF
1
R18 1K1
C49
10nF
1
FB3
BLM18PG600SN1
1 2
RN44 10K1234 5
678
J4JP-1x2_NL
1 2
R19 10K_NL1
R11 10K_NL1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AMD GEODE
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 10 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
DGND
VCORE
VCC3
VCCMEM
VCORE
DGND
VCC3
VCCMEM
C108
10nF
1
C109
100pF
1
C72
22uF
1
C73
22uF
1
C61
10nF
1
C74
22uF
1
C69
100pF
1
C62
10nF
1
C96
100pF
1
C63
10nF
1
C100
10nF
1
C97
100pF
1
C101
10nF
1
C98
100pF
1
C99
100pF
1
C90
10nF
1
C94
100pF
1
C91
10nF
1
C95
100pF
1
C92
10nF
1
C93
10nF
1
C68
100pF
1
C87
22uF
1
C102
22uF
1
C88
22uF
1
C103
22uF
1
C89
22uF
1
C104
22uF
1
C60
10nF
1
C84
100pF
1
C86
100pF
1
C58
22uF
1
C85
100pF
1
C59
22uF
1
C80
1nF
1
C81
1nF
1
C75
10nF
1
C110
100pF
1
C82
1nF
1
C111
100pF
1
C83
100pF
1
C65
1nF
1
C57
22uF
1
C112
100pF
1
C66
1nF
1
C113
100pF
1
U1E
LX PROCESSOR
W
1
7
A
1
E
1
B
2
R
4
A
H
2
8
D
1
0
A
3
B14A16D18AJ16
D
1
4
D
2
2
C
2
1
A
2
1
V17AK2V16V15R15R14R13P28L2N16A31A27N15D16D7N17N28P15P16P17H2A11R16R17
A
K
5
D
1
7
W
1
3
W
1
4
W
1
8
W
1
9
A
H
1
5
U
4
A
H
1
7
T
2
Y
2
8
N
1
3
N
1
4
T
4
N
1
8
N
1
9
P
1
3
P
1
4
D
1
5
P
1
8
P
1
9
R
2
8
U
2
8
U
2
9
U
3
0
U
3
1
V
1
3
V
1
4
V
1
8
V
1
9
V
2
8
T
1
T
3
D4C7N4
B11H1L1B8
A14B31C29P29
B5C14
K3C18A18B24C25B27D28E30G29B21H31K29L31A30N29
C3A2B1E2G3
R18AH12Y29AA30AD30AG2AH9AH4AH6AG30R19AH20C2C4A8W16W15D25B18AH14A24A29B29B30C28C30C31D29E31G28K28P31W28AC28D3A5
G
4
A
C
4
A
D
2
R
1
Y
4
H
3
0
T
1
3
L
3
0
T
1
4
T
1
5
T
1
6
T
1
7
T
1
8
T
1
9
T
2
8
T
2
9
N
3
K
4
T
3
0
T
3
1
U
1
3
U
1
4
U
1
5
U
1
6
U
1
7
U
1
8
U
1
9
C
1
2
A
H
2
3
A
H
2
6
A
F
4
A
H
1
8
A
H
1
6
B
3
C
1
P
4
R
2
AL11AG31AA31AC29AD31
AJ3AD1AC3AJ6AJ9
AJ12AG1
AF29AJ14AJ18AJ20AJ23AJ26
Y3AK1
AJ29AF3
AK31AL2AL8
AL24AL21
AL5AL27AL30
A
K
8
A
K
1
8
A
K
1
6
A
K
1
4
A
K
1
1
A
K
2
1
A
K
2
4
A
K
2
7
A
K
3
0
A
L
1
A
L
1
6
A
L
3
1
R
3
A
F
2
8
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
VSSVSSVSSVSS
V
S
S
V
S
S
V
S
S
V
S
S
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
V
S
S
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
V
D
D
VMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEMVMEM
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
VDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIOVDDIO
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
C115
10nF
1
C67
1nF
1
C114
100pF
1 C116
10nF
1
C70
100pF
1
C76
10nF
1
C71
100pF
1
C77
10nF
1
C79
1nF
1
C78
10nF
1
C64
1nF
1
C105
10nF
1
C106
10nF
1
C107
10nF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: AnyGPIO can be used asan IRQx or INT#x.There are significantbootloader configurationchanges required ifselection is different thanshown. Changes arehighly discouraged.
DESIGN NOTE:LED is optional.
PWR MANAGEMENTRED
COMPANION DEVICE
AMD GEODE
INVERTER
SAVE TO RAM SUPPORTDESIGN NOTE: GPIO24/WORK_AUX is anopen drain output, which requires a pullupresistor to achieve a high state. At initialstandby power application theGPIO24/WORK_AUX pin defaults to GPIO24and the GPIO24 defaults as an input. Thisdefault combination will leave the pin in ahigh state due to the pullup which isnormally connected to VCC3SB. This circuitworks aournd that behaviour so that Save toRAM will function correctly.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 11 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
TEST_MODE
FUNC_TEST
WORK_AUX
SYS_RST#
PWRBTN#IDE_CABLEID#
CS5536_GPIO25
PME#MFGPT7_C1
WORKING
PCI_INTB#PCI_AD7
PCI_AD18
PCI_AD15
PCI_AD17
PCI_AD28
PCI_AD3
PCI_INTA#
PCI_AD13
PCI_AD23PCI_AD22
PCI_AD29
PCI_AD21
PCI_AD9
PCI_AD25
PCI_AD30
PCI_AD12
PCI_AD14
PCI_AD19
PCI_AD24
PCI_AD20
PCI_AD26
PCI_AD11
PCI_AD8
PCI_AD1
PCI_AD4
PCI_AD6
PCI_AD10
PCI_AD27
PCI_AD16
PCI_AD31
PCI_AD0
PCI_AD5
PCI_AD2
RTCXINRTCXOUT
PCI_INTD#PCI_INTC#
RTCXOUT
MFGPT7_C1
PCI_INTD#
PWRBTN#
TEST_MODE
RST_STB#
PCI_INTB#
FUNC_TEST
SYS_RST#IDE_CABLEID#
WORKING
PCI_INTA#
SLP_CLK#
PCI_INTC#
MFGPT7_C1
PME#
RTCXIN
5536_GPIO6
WORK_AUX
WORKING
MFGPT7_C1
RST_STB#
WORK_AUX
CS5536_GPIO25
5536_GPIO6
PCI_RST# 9,12,15,16,17,19,20,24,25
IDE_CABLEID# 21
CLK_IOC 13
PME# 15,17,19,25
PCI_INTB# 15,19,24
SUSPA# 9
PWRBTN# 25
CIS 9
SLP_CLK# 13
WORKING 25
PCI_PAR9,15,19,20,24
PCI_AD[31:0]9,15,19,20,24
REQ2#9
PCI_STOP#9,15,19,20,24
PCI_C/BE2#9,15,19,20,24PCI_C/BE1#9,15,19,20,24PCI_C/BE0#9,15,19,20,24
PCI_IRDY#9,15,19,20,24PCI_FRAME#9,15,19,20,24
PCI_INTA#9,19,24
GNT2#9
PCI_TRDY#9,15,19,20,24
PCI_C/BE3#9,15,19,20,24
PCI_DEVSEL#9,15,19,20,24
IRQ13 9
CLK_14_IOC 13
PS_ON# 25
PCI_INTC# 24PCI_INTD# 24
WORK_AUX 25
SYS_RST# 9,17,25
OT_ALARM 17
CS5536_GPIO8 17CS5536_GPIO9 17
IDE_LED21EXT_PWRBTN#25
EXT_RST#25
RST_STB# 25
CS5536_GPIO25 17
LAN_PD# 15
CS5536_GPIO6 17
VCC3
VCC3SB
VCC5SB
DGND
DGND
DGND
DGND
VCC3SBVCC3SB
DGND
DGND DGND
DGND
VCC3
RN30 10K1234 5
678
R46 5601
RN31 10K1234 5
678
C120
100nF
1
R441M1
C119
22pF
1
R91330R
1
R40 5.6K1
D2
LTST-C190EKT
12
C118
22pF
1
R95 01
Y132.768KHz
ABS13-32.768KHz-12.5pF - T
1 4
R39 1K1
R41 5.6K1
R4710K
1
R4522M1
R42 1K1
C1171pF
1
U4A
CS5536
R17T17R16T16P16T15R15P15T14R14U13T13R13U12T12R12
U8T8R8U7T7R7U6T6U5T5R5T4R4U3T3U1
U10
U14U11
T9R6
U9R10R11T10R2
T11
R1T1
U4
C5
A8D3
D2C2
E3D1
C3A1
C9A9
B7C8
A5B8C6
F2
P3N1
J3
K2
C1A4B3
G15
A6B9
F3
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
PAR
C/BE0#C/BE1#C/BE2#C/BE3#
FRAME#IRDY#DEVSEL#TRDY#GPIO0STOP#
GNT#REQ#
PCI_CLK
WORKING
GPIO28/PWR_BUT#GPIO5/MFGPT1_RS/MFGPT0_C1
GPIO6/MFGPT0_RS/MFGPT1_C1/MFGPT2_C2GPIO7/MFGPT2_C1/SLEEP_X
GPIO8/UART1_TX/UART1_IR_TXGPIO9/UART1_RX/UART1_IR_RX
GPIO10/THRM_ALRM#GPIO11/SLP_CLK_EN#/MFGPT1_C2
GPIO24/WORK_AUXGPIO25/LOW_BAT#/MFGPT7_C2
GPIO26/MFGPT7_RSGPIO27/MFGPT7_C1/32KHZ
RESET_OUT#RESET_STAND#RESET_WORK#
GPIO13/SLEEP_BUT
SUSP#/CISSUSPA#
GPIO12/AC_S_IN2/SLEEP_Y
IRQ13
MHZ14_CLKKHZ32_XCI
KHZ32_XCO
USB_PTEST
TEST_MODELVD_TEST
FUNC_TEST
R94 0_NL1
R48 10K1
Q1BSS138/SOT
C122
4.7uF
1
R43 1K1
RN29 10K1234 5
678
C121
100nF
1
J31
PFL-2x4-2M0-SMD-S
2468
1357
U5
NC7SZ08/SC70
1
24
5
3
R93330R
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BOS0
DESIGN NOTE: Place series Rnear the audio CODEC.
BOS1
DESIGN NOTE: Place series R near the IOC.
11
BOOT STRAP OPTIONS0 LPC ROM OFF LPC
RESERVED01
SST FWH OFF LPC (DEFAULT)1
NOR FLASH OFF IDE INTERFACE0
BOS10
BOS0
DESIGN NOTE: This design uses LVD (LVD_EN# tiedlow) to generate system reset. Since LVD only monitorsVcore in the working domain, the designer mustguarantee that Vio and other required voltages arevalid at or before Vcore. If this cannot be guaranteed,then RESET_WORK# must be used to hold system inreset until Vio and Vcore and any other requiredvoltages are valid.
DESIGN NOTE: USBPWR_EN1/2 andUSB_OC# are used for a fully compliantUSB design. See Option Schematics forfully compliant USB design.
COMPANION DEVICE
AMD GEODE
LPC Header
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 12 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
XTALI_48
TDBGI_IOC
XTALO_48
CRT_SDA
SYNC_BOS0
LVD_EN#
SDATA_OUT_BOS1SDATA_IN
BITCLK
CLK_LPC_IOC
BITCLK
SDATA_IN
SYNC_BOS0
SDATA_OUT_BOS1
USB_REXT
CRT_SCL
LAD1LAD0
LAD2
SMB_SCLSMB_SDA
XCEN
I_D0
I_D7I_D8
I_D2
I_D10
I_D12
IDE_DRQ#
I_D15
I_D9
IDE_IRQ
I_D14
I_D6
I_D3
I_D11
I_D4I_D5
I_D1
I_D13
IDE_RDY#
LAD3
SERIRQ
XTALO_48XTALI_48
SERIRQLDRQ#
LAD1
LAD3CLK_LPC_IOC
LAD0LFRAME#
LAD2
LFRAME#LDRQ#
SMB_SCL
SERIRQLDRQ#
PCBEEP
CRT_SDA
IDE_RDY#
LAD1
LFRAME#
TDBGI_IOC
LAD2LAD3
CRT_SCL
USB_OC#
LVD_EN#
IDE_D7
LAD0
XCEN
IDE_DRQ#
SMB_SDA
IDE_IRQ
I_IRQI_RST#
I_A0I_A1I_A2I_ACK#I_DRQ#I_IOR#I_IOW#I_RDY#I_CS0#I_CS1#
I_IRQ
I_RST#
I_DRQ#
I_IOR#I_IOW#
I_RDY#
I_CS0#I_CS1#
I_A1
I_A2I_A0
I_ACK#
I_D12
I_D7
I_D15
I_D1
I_D5I_D10
I_D8
I_D13
I_D2
I_D4
I_D6
I_D14
I_D9
I_D3
I_D0
I_D11
IDE_D2
IDE_D3
IDE_D4
IDE_D7IDE_D8
IDE_D5
IDE_D6
IDE_D1
IDE_D10
IDE_D11
IDE_D12
IDE_D0
IDE_D9
IDE_D13
IDE_D14
IDE_D15
CLK_LPC_IOC 13
USB_OC#18
LAD3 17
TDO_CPU 9JTAGTDO 9
LAD2 17
LAD0 17
LFRAME# 17
JTAGTCK 9
CRT_SDA 14,26
LAD1 17
JTAGTMS 9
USB3-18USB3+18
USB0-18
USB2+18USB1-18USB1+18
USB0+18
USB2-18
AC97_DATA_OUT 16
AC97_SYNC 16AC97_BITCLK 16
AC97_DATA_IN 16
CRT_SCL 14,26
CLK_IDE13
IDE_ACK#21
IDE_IOW#21
IDE_CS1#21IDE_CS0#21
IDE_IRQ21IDE_A121
IDE_A221IDE_A021
IDE_RDY#21
IDE_RST#21
IDE_IOR#21
IDE_DRQ#21
PCBEEP16
CLK_48_DOT9
SERIRQ 17,20
LDRQ# 17
SMB_SCL 7SMB_SDA 7
USB_PWR_EN118USB_PWR_EN218
PCI_RST# 9,11,15,16,17,19,20,24,25
IDE_D[15:0]21
DGND
VCC3
DGND
DGNDDGND
DGND
VCC3 VCC3
DGND
VCC3
VCC5
R64 221
R53 10K1
R57 10K1
R61 2.2K1
C123
18pF
1
C124
18pF
1
R52 4.7K1
RN40 221234 5
678
R66 221
RN35 10K1234 5
678
R65 221
R56 10K_NL1
R60 2.2K1
Y2
48.0000MHz
1 2
RN36 221234 5
678
R70 1K1
RN37 221234 5
678
R54 10K1
RN32 221234 5
678
R623.4K,1%
1
R67 10K_NL1
R59 10K1
RN38 221234 5
678
R58 10K1
J8
PFL-2x10
13579
1113151719
2468101214161820
R51 2.2K1
RN34 221234 5
678
R68 1K1
RN33 10K1234 5
678
R50 2.2K1
R63 221
R69 10K_NL1
R55 10K1
RN39 221234 5
678
U4B
CS5536
B12F15A10
A11A12B11C12A14B13C13A13B10C10
B14A15C15C16B17D15E15E16E17D17D16C17A17B16B15C14
K3
M1
L3L1L2
N17
P17N16N15
K16K17L16L17H17H16G17G16
H1H2J2J1K1G1H3G2
G3F1
E1E2
N2P1P2N3M2M3
C7
M15K15
J15H15F17
GPIO2/IDE_IRQ0IDE_RESET#MHZ66_CLK
IDE_AD0/FLASH_AD25/AD0/FLASH_CLEIDE_AD1/FLASH_AD26/AD1IDE_AD2/FLASH_AD27/AD2IDE_DACK0#/FLASH_CS3#/FLASH_CE3#IDE_DREQ0/FLASH_CS2#/FLASH_CE2#IDE_IOR0#/FLASH_RE#IDE_IOW0#/FLASH_WE#IDE_RDY0/FLASH_IOCHRDY/FLASH_RDY/BUSY#IDE_CS0#/FLASH_CS0#/FLASH_CE0#IDE_CS1#/FLASH_CS1#/FLASH_CE1#
IDE_DATA0/FLASH_AD10/IO0IDE_DATA1/FLASH_AD11/IO1IDE_DATA2/FLASH_AD12/IO2IDE_DATA3/FLASH_AD13/IO3IDE_DATA4/FLASH_AD14/IO4IDE_DATA5/FLASH_AD15/IO5IDE_DATA6/FLASH_AD16/IO6IDE_DATA7/FLASH_AD17/IO7IDE_DATA8/FLASH_AD18/AD3IDE_DATA9/FLASH_AD19/AD4IDE_DATA10/FLASH_AD20/AD5IDE_DATA11/FLASH_AD21/AD6IDE_DATA12/FLASH_AD22/AD7IDE_DATA13/FLASH_AD23/AD8IDE_DATA14/FLASH_AD24/AD9IDE_DATA15/FLASH_ALE
GPIO1/AC_BEEP/MFGPT0_C2
AC_CLK
AC_S_SYNC/BOS0AC_S_INAC_S_OUT/BOS1
MHZ48_CLK
USB_PWR_EN1USB_PWR_EN2USB_OC_SENS#
USB1_DATPOSUSB1_DATNEGUSB2_DATPOSUSB2_DATNEGUSB3_DATPOSUSB3_DATNEGUSB4_DATPOSUSB4_DATNEG
LPC_CLKLPC_AD0/GPIO16LPC_AD1/GPIO17LPC_AD2/GPIO18LPC_AD3/GPIO19
LPC_DRQ#/GPIO20LPC_FRAME#/GPIO22
LPC_SERIRQ/GPIO21/MFGPT2_RS
GPIO14/SMB_CLKGPIO15/SMB_DATA
GPIO3/UART2_RXGPIO4/UART2_TX
TCKTDI
TDOTMS
T_DEBUG_INT_DEBUG_OUT
LVD_EN#
USB_VBUSUSB_REXT
MHZ48_XCOMHZ48_XCI
MHZ48_XCEN
R49 1K1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: Enablesspread spectrum. EMImitigation technique
1-2
2-3 Clear CMOS
Normal
J1
J1
DESIGN NOTE: Without UL approvalof the internal VBAT circuity, a 47 ohmresistor (R1) is required. UL approvalis in process and is expected. WithUL approval R1 can be removed.
R1
COMPANION DEVICE
AMD GEODE
DESIGN NOTE: Swap series resistorson the clock lines in order minimizethe number of vias.
DESIGN NOTE: If this schematic is usedfor future designs, R72 should be replacedwith a 220_2A ferrite bead.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 13 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*CLKX2
14_318MHZ0
48MHZ
PCI_CLK1
PCI_CLK3
14_318MHZ1
LCLK1LCLK0
PCI_CLK2
IDE_CLK
CLKX1
14_318MHZ014_318MHZ1
PCI_CLK0
IDE_CLK
PCI_CLK0PCI_CLK1PCI_CLK2PCI_CLK3
48MHZ
LCLK1LCLK0
SLP_CLK#11
PC_CLK 24
CLK_IDE 12
CLK_14_IOC 11
CLK_IOC 11CLK_EXT 9
CLK_14_CODEC 16
CLK_CPU 9
CLK_LPC_SIO_EXT 17
CLK_14_ISA 24
CLK_LPC_IOC 12
SIO_CLK_48 17
DGND
VCC3SB
VCC3
DGND
DGND
VCC3
VCORESB
VCORE
VCORE
DGND
DGND
DGND
DGND
VCC3
DGND
VCC3USB
DGND
DGNDDGND
VCC3
VCORE
DGND
VBAT
VCC5
DGND
VCC3SB
VBAT
DGND
D17
BAS40_NL
1 2
C126
22uF
1
C139
100pF
1
FB4HI1206N101R-00
1
C163
18pF
1
C133
10nF
1
C127
100nF
1
C151
10nF
1
R213
330_NL1
C159
100nF
1
C143
22uF
1
C136
10nF
1
R74 10K1
J9
PFL-1x3
123
C149
10nF
1
U6
MK1491-09F
1
2
1
1
10
9
8
7
65
2726
23
2
5
4 2
8
3
2
2
2
24
1
1314
1
5
17
18
1
9
20
2
1
16
V
D
D
G
N
D
SEL66/33#
LCLK2
V
D
D
G
N
D
LCLK1LCLK0
REFCLK0/SP#REFCLK1
PCICLK2
V
D
D
V
D
D
V
D
D
XTALOUT
XTALIN
G
N
D
PCICLK3
G
N
D
48MHz48MHz/TS#
G
N
D
PD#
PCICLK0
V
D
D
PCICLK1
G
N
D
66MHz
C134
10nF
1
R72 4.7R1
C155
100pF
1
R75 10M_NL1
R731K
1
C150
10nF
1
C142
100pF
1
+
VBH2032-1
BT1
1
2
C140
100pF
1
C130
10nF
1
C156
100pF
1
C125
22uF
1
C148
22uF
1
C132
100nF
1
R214
330_NL1
R71 471
U4C
CS5536
A3
A7
B6
K14H14
D10D8H4K4P8
P10
P14M14F14D14
D12D9D6D4F4M4P4P6P9
P12
F16J16M16
L14J14G14
E14D13D11D7D5E4G4J4L4N4P5P7P11P13
C4B2
U15C11A16R3
U16U17R9
M17J17B5B4B1T2U2A2
N14
L15VBAT
VCORE_VSB
VIO_VSB
VDDC_USB1VDDC_USB0
VCOREVCOREVCOREVCOREVCOREVCORE
VDDIO_USB0VDDIO_USB1VDDIO_USB2VDDIO_USB3
VIOVIOVIOVIOVIOVIOVIOVIOVIOVIO
NCNCNC
VSSIO_USB0VSSIO_USB1VSSIO_USB2
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
NCNC
NCNCNCNC
NCNCNC
NCNCNCNCNCNCNCNC
VSS
NC
C138
100pF
1
RN41
22
1234 5
678
C160
100nF
1
Y3
14.31818MHz
1 2RN43
22
1234 5
678
C147
22uF
1
C157
22uF
1
C158
100nF
1
D19
BAS40_NL
1 2
R2151K_NL
1
C144
10nF
1
C162
18pF
1
C137
10nF
1
C154
100pF
1
C131
1uF
1
C135
10nF
1
C129
10nF
1
C128
22uF
1
C146
100pF
1
C222
220M_NL
1
D18
BAS40_NL
1 2
C152
10nF
1
R23 221
RN42
22
1234 5
678
C145
10nF
1
C141
100pF
1
C161
100nF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VGA
DESIGN NOTE: Placethe ESD protectioncomponents as close tothe VGA connector aspossible.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 14 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
MCRT_HSYNC
MDDCLK_UART_RX
MRED
MBLUE
MGREEN MDDAT_UART_TX
MCRT_VSYNC
RED8
GREEN8
HSYNC 8
BLUE8 CRT_SCL 12,26
CRT_SDA 12,26
VSYNC 8
DGND
VCC3
VCC5
DGND
VCC3
DGND
VGA_CHASSIS
AGND_VGA
DGND
VGA_CHASSIS
P1C CON-COMBO-DB9-15-25-TRIPLEPORT
C15C10
C5
C14C9C4
C13C8C3
C12C7C2
C11C6C1
M
T
G
5
M
T
G
6
R8075
1
D6
BAV99/SOT
C165
4.7pF
1
C164
4.7pF
1
L1
22nHINDUCTOR, 22NH, 5%, 0603, 0.48A
1
D8
BAV99/SOT
C171
100nF
1
C170100nF
1
L2
22nHINDUCTOR, 22NH, 5%, 0603, 0.48A
1
R78 0
R8175
1
FB5BLM18PG600SN1
1
C169
4.7pF
1
D4
BAV99/SOT
R79 0
C168
4.7pF
1
L3
22nHINDUCTOR, 22NH, 5%, 0603, 0.48A
1
R77 0
D3
BAV99/SOT
D9
BAV99/SOT
C167
4.7pF
1
R76 0
C166
4.7pF
1
D5
BAV99/SOT
F11.10A, 16V
1
R8275
1
D7
BAV99/SOT
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H
L
Normal
DefinitionPWRDN
Powerdown
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 15 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
EESKEEDOEEDI
EECS
EESK
EECSEEDO
EEDI
PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10
PCI_AD12PCI_AD11
PCI_AD13PCI_AD14PCI_AD15
PCI_AD30PCI_AD31
PCI_AD24
PCI_AD16
PCI_AD28
PCI_AD17
PCI_AD26
PCI_AD18
PCI_AD27
PCI_AD20PCI_AD19
PCI_AD29
PCI_AD21PCI_AD22PCI_AD23
PCI_AD25
PCI_AD24
PCI_AD[31:0]9,11,19,20,24
GNT#_LAN9REQ#_LAN9
PCI_DEVSEL#9,11,19,20,24
PCI_STOP#9,11,19,20,24PCI_TRDY#9,11,19,20,24PCI_IRDY#9,11,19,20,24
PCI_FRAME#9,11,19,20,24PCI_PAR9,11,19,20,24
CLK_EXT29
TXM2 18
TXP2 18
RXP2 18
RXM2 18
P1LED2 18
PCI_RST#9,11,12,16,17,19,20,24,25PCI_INTC#11,19,24
P2LED2 18P2LED3 18
P1LED3 18
PME#11,17,19,25
PCI_C/BE0#9,11,19,20,24PCI_C/BE1#9,11,19,20,24PCI_C/BE2#9,11,19,20,24PCI_C/BE3#9,11,19,20,24
TXP1 18
RXP1 18
RXM1 18
TXM1 18
LAN_PD# 11
DGND
DGND
DGND
DGND
DGND
DGND
DGND
VCC3
V_LAN_12A
VCC3V_LAN
V_LAN_12AVCC3V_LAN
V_LAN_12
VCC3
VCC3
V_LAN_12A_PLL
V_LAN_12A_PLL
VCC3
VCC3
V_LAN_12
V_LAN_12
VCC3
DGND
VCC3
C187
22uF
1
C175
100nF
1
Y425MHZ Crystal
R89 10K
C182
100nF
1
C174
100nF
1
R85 1K
R83 1K
R8810K
1
R9210K
1
C183
22uF1
U8
AT93LC46 MSOP8
1234 5
678CS
SKDIDO GND
ORGNC
VCC
R84 3K,1%
C181
100nF
1
C184
100nF
1
C188
100nF
1
C191
100nF
1
C193
100nF
1
FB6BLM18PG600SN1
1 2
U7
KSZ88XX-PMQL
128127126122121120119118117116115114113112111110109106105104103102101100
9998979695949389
88878685
8077767574737271706968
48
49
45
46
56
55
53
52
4461
5960124041
6712
543
876
26
27
282930
65
66
8182838411
14
13
16
15
1820
22
212531
36
19
9 2
3
7
8
9
0
1
0
7
1
2
3
3
7
3
9
4
2
4
7
5
4
5
8
6
2
6
4
2
4
9
1
1
2
5
4
3
5
7
3
8
6
3
1
0
7
9
1
0
8
5
1
5
0
3
4
3
5
1
2
4
3
3
9
2
17
3
2
PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7PAD8PAD9PAD10PAD11PAD12PAD13PAD14PAD15PAD16PAD17PAD18PAD19PAD20PAD21PAD22PAD23PAD24PAD25PAD26PAD27PAD28PAD29PAD30PAD31
CBE0#CBE1#CBE2#CBE3#
SERR#PERR#GNT#REQ#DEVSEL#IDSELSTOP#TRDY#IRDY#FRAME#PAR
TXP1
TXM1
RXP1
RXM1
TXP2
TXM2
RXP2
RXM2
FXSD1/NCISET
NCNC
TESTENSCANEN
NCNC
RST#PCLK
P1LED0P1LED1P1LED2
P2LED0P2LED1P2LED2
EEEN
P1LED3
EEDOEESKEEDI
X1
X2
NCNCNCNCNC
PME#
NC
INTR
NC
NCNC
P2LED3
NCNCNC
PWRDN
EECS
D
G
N
D
D
G
N
D
D
G
N
D
D
G
N
D
D
G
N
D
D
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
A
G
N
D
V
D
D
C
O
V
D
D
C
V
D
D
I
O
V
D
D
A
V
D
D
A
V
D
D
A
V
D
D
A
P
V
D
D
I
O
V
D
D
I
O
V
D
D
I
O
V
D
D
A
R
X
V
D
D
A
T
X
D
G
N
D
D
G
N
D
D
G
N
D
V
D
D
I
O
V
D
D
I
O
NC
V
D
D
I
O
C185
100nF
1
100R901
C179
100nF
1
C172
22uF
1
C190
22uF
1
C192
100nF
1
C194
22pF
1
C186
100nF
1
C173
100nF
1
C178
100nF
1
FB7
BLM18PG600SN1
1 2
R86 1K
C177
100nF
1
C195
22pF
1
FB8
BLM18PG600SN1
1 2
C180
22uF
1
R8710K
1
C176
100nF
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALC655
Left Channel
Right Channel
REALTEK
DESIGN NOTE: Use14.318MHz externalclock
GroundBuzzer
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 16 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
VREFOUT
VCC_AUD
MIC1
MIC2JD0
FRONT_OUT_RJD2
FRONT_OUT_L
LINE_IN_RLINE_IN_RJD1
LINE_IN_LLINE_IN_L
LINE_IN_R
LINE_IN_L
MIC1
MIC2
VREFOUT
JD_0JD0
JD1 JD_1
JD2
JD_0
JD_2
JD_2
JD_1
FRONT_OUT_R
FRONT_OUT_L
AC97_PCBEEP
AC97_PCBEEP
PCI_RST#9,11,12,15,17,19,20,24,25
PCBEEP12 AC97_SYNC12
CLK_14_CODEC13
AC97_DATA_IN12AC97_DATA_OUT12
AC97_BITCLK12
VCC5
VCC3
DGND
VCC3
DGND DGND
DGND DGND
DGND
DGND
DGND
VCC3
GND_AUD GND_AUD
GND_AUD GND_AUD
GND_AUD
GND_AUD
GND_AUD
GND_AUDGND_AUD
GND_AUD
GND_AUD
DGND AUD_CHASSIS
GND_AUD
DGND
GND_AUD
AUD_CHASSIS
AUD_CHASSIS
FB34BLM18PG600SN1
1
R202 10K
10KR1971
R10122K
1
1nFC199 1FERR
FB12 FB/1201 2
R1034.7K
1
R12722K
1
220pF
C215
1
Red Mic InJ10A
AJ3595
1234
5
L1L2R1R2
A
G
N
D
10KR1981
1uFC200
1
3.3uF
C203
1
1uFC2091
22uFC216
1
FERRFB9 FB/120
1 2
R2031K
1
100nFC217
1
FERRFB13 FB/120
1 2
100nFC338
1
C189100nF
1
R12622K
1
BUZ1DET801H_NL
41
2 3
N
C
+
- N
C
10KR1991
FERRFB14 FB/120
1 2
1uFC2061
100nF
C341
1
FERRFB10 FB/120
1 2
100nF
C1971
100pF
C207
1
R108 22_NL
22uF
C1981
0R1961
0R1051
Blue Line InJ10C
AJ3595
10111213
1
6
1
7
L1L2R1R2
S
H
L
D
S
H
L
D
R1024.7K
1
100pF
C208
1
R10910K_NL
1
Green Line OutJ10B
AJ3595
6789
1
4
1
5
L1L2R1R2
S
H
L
D
S
H
L
D
R13010K
1
3.3uF
C201
1
0R971
0R961
100pF
C211
1
0R1041
FERRFB11 FB/120
1 2
FERRFB15 FB/120
1 2
100pF
C210
1
1nFC196 1
R10722K
1
1uFC2041
100nFC3421
3.3uF
C202
1
1uFC2051
R10022K
1
100nFC337
1
220pF
C214
1
R10622K
1
U9
ALC6551234567891 01 11 2
13
14
15
16
17
18
19
20
21
22
23
24
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
37
38
39
40
41
42
43
44
45
46
47
48
D
V
D
D
1
X
T
L
-
I
N
X
T
L
-
O
U
T
D
V
S
S
1
S
D
A
T
A
-
O
U
T
B
I
T
-
C
L
K
D
V
S
S
2
S
D
A
T
A
-
I
N
D
V
D
D
2
S
Y
N
C
R
E
S
E
T
#
P
C
-
B
E
E
P
PHONE
AUX-L
AUX-R
JD2
JD1
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-IN-L
LINE-IN-R
A
V
D
D
1
A
V
S
S
1
V
R
E
F
V
R
E
F
O
U
T
A
F
I
L
T
1
A
F
I
L
T
2
V
R
D
A
/
V
R
A
D
F
R
O
N
T
-
M
I
C
2
/
V
R
D
A
V
R
E
F
O
U
T
2
F
R
O
N
T
-
M
I
C
1
F
R
O
N
T
-
O
U
T
-
L
F
R
O
N
T
-
O
U
T
-
R
MONO-O
AVDD2
SURR-OUT -L/HP-OUT-L
NC
SURR-OUT -L/HP-OUT-R
AVSS2
CENTER-OUT
LFE-OUT
JD0/GPIO0
XTLSEL/ID1#
SPDIFI/EAPD
SPDIFO1uFC2121
Q2BSS138/SOT NL
1uFC2131
22pFC218
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SPI FLASH
S1DESIGN NOTE: Explanation of straps on SIOS1 - SPI Flash - 0=enable, 1=disable, Default=0S2 - SPI Flash Data out - 0=SD1, 1=SD2, Default=1S3 - See chip ID Byte 2, Not used, Default=1S4 - Not used, Default=1S5 - Fan Control EC index - 0=00h, 1=40h, Default=1S6 - Not used, Default=1
Fan Control
WATCHDOG OUT
DESIGN NOTE: The 8 bit ADC has a 16mVLSB, with a 0V to 4.096V input range. Ifnegative voltage is to be measured useVREF in a divider to produce a positiverange. A seperate low impedance groundplane should be used to achieve accuratemeasurements.
SIO STRAPING
S2S3S4S5S6
DRB
DESIGN NOTE: The 8 bit ADC has aconversion rate of 8Hz. Use of the ADCfeature is limited to applications that canaccept this frequency.
DESIGN NOTE: Install DRB jumperwhen booting from Disaster RecoveryBoard. Install the DRB into J8, LPCHeader.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 17 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
PD1PD2
PD0
PD5
PD7
PD4PD3
PD6
S_FLASH_DOUT
S_FLASH_CLKS_FLASH_CE#
S_FLASH_DIN
SIO_PWM5SIO_PWM4SIO_PWM3SIO_PWM2FAN_CNTL
SIO_GPIO30SIO_GPIO31SIO_GPIO32SIO_GPIO33SIO_GPIO34SIO_GPIO35
S_FLASH_CLK
SIO_ADC1
SIO_ADC3
SIO_ADC0
SIO_ADC2
SIO_ADC7
S_FLASH_DIN
SIO_ADC4SIO_ADC5SIO_ADC6
S_FLASH_CE#
SIO_ADC_VREF
SIO_GPIO37SIO_GPIO25
SIO_GPIO52
SIO_GPIO24
FAN_TAC
TDP
SIO_GPIO20SIO_GPIO17
SIO_GPIO21
SIO_GPIO13
SIO_GPIO62
SIO_GPIO14
SIO_GPIO41
SIO_GPIO10/WD_ACTIVE
SIO_GPIO50
SIO_GPIO40
SIO_ADC0
SIO_PWM3
SIO_ADC7
SIO_PWM2
SIO_ADC1SIO_ADC2
SIO_PWM4SIO_PWM5
SIO_ADC6
SIO_ADC4SIO_ADC3
SIO_ADC5
SIO_GPIO46SIO_GPIO47
SIO_GPIO53SIO_GPIO42SIO_GPIO43
SIO_GPIO44SIO_GPIO45
SIO_GPIO14
SIO_GPIO24
SIO_GPIO13
SIO_GPIO21
SIO_ADC_VREF
TDP
DTR1#
RTS1#
TXD1
DTR2#
SIO_ADC_VREF
FAN_CNTL
S_FLASH_DOUT
SIO_BOARDTEMP
RI1#
RI2#
SIO_ADC_VREF
SIO_BOARDTEMP
SIO_GPIO17SIO_GPIO20
SIO_GPIO31
SIO_GPIO35
SIO_GPIO30
SIO_GPIO34SIO_GPIO33SIO_GPIO32
SIO_GPIO25
SIO_GPIO37
SIO_GPIO41SIO_GPIO40
SIO_GPIO46SIO_GPIO47
SIO_GPIO44SIO_GPIO45
SIO_GPIO42SIO_GPIO43
SIO_GPIO50
SIO_GPIO52SIO_GPIO53
FAN_TAC
FAN_TACRI1#
RI2#
RTS2#
TXD2
SIO_GPIO10
SIO_GPIO10
WD_ACTIVE
SIO_GPIO10/WD_ACTIVE
SIO_GPIO62
WD_ACTIVESIO_GPIO62
PD[0:7] 23
PME#11,15,19,25
LAD112
LAD312
LAD012
LAD212
SERIRQ12,20
PCI_RST#9,11,12,15,16,19,20,24,25LDRQ#12
LFRAME#12
SIO_CLK_4813CLK_LPC_SIO_EXT13
KBCLK 23KBDAT 23
MSDAT 23MSCLK 23
DTR2# 22
CTS1# 22
TXD2 22
STB# 23
BUSY 23
SYS_RST# 9,11,25
DSR1# 22
PE 23
DCD1# 22
SLCT 23
AFD# 23
RTS2# 22
PRNINIT# 23
RXD1 22
ACK# 23
CTS2# 22
ERR# 23
RXD2 22
RTS1# 22
TXD1 22
DSR2# 22
DTR1# 22
DCD2# 22
DSA#22
WGATE#22HDSEL#22
DSKCHG#22
INDEX#22
RDATA#22
WDATA#22
STEP#22
TRK0#22
WP#22
MOT0#22
DIR#22
TDP9
TDN9
OT_ALARM11
SLIN# 23
RS485_EN222RS485_EN122
CS5536_GPIO8 11
CS5536_GPIO25 11CS5536_GPIO9 11
CS5536_GPIO6 11
VCC3
DGNDDGND
VCC3
DGND
VCC5
SIO_AGND
VCC3 VCC5
DGND DGND
VCC5VCC5
DGND SIO_AGND DGND
DGND SIO_AGND
VCC3
SIO_AGND
VCC3
VCC3SB12V
VCC5
DGND
VCC3
VCC5
SIO_AGND
DGND DGND
VCC5
DGND
VCC5
VCC3SB
DGND
VCC5SBVCC5
DGND
VCC5SB
220pFC2191
U24
NC7SZ74
8
53
476
12 VCC
QQ#
GNDPR#CL#
CLKD
R111 10K
C221
1nF
1
D16 MMBD4148AC
R190 0
R125 30K
R211 0
R212 0_NLFB16
BLM18PG600SN1
1 2
J27
PFL-1x3
21
3
J11
AMP-640456-3
21
3R110 10K
J18
JP-1x2_NL
1 2
C336
1.5nF
1
10K_NLR1151
J12
PFL-2x20-2M0-SMD-S
246810
13579
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
128 pin QFP
U11
IT8712F
4
1
5
3
5
5
0
6
9
7
4
8
9
9
10
7
5
911
123
6
1819
17
8
6
2021
1
1
7
12
131416
2223
2425
2726
28293031
128
127126
125124123122121
323334
37
120
119118
116
38394041424344
45
115114113112111110109
108
3
6
46
47
48
49
515253545556575859606162636465
66
68
70
717273757677
107106105104103102101100
989796959493929190
898887
8584
83828180
7978
6
7
V
C
C
G
N
D
D
V
C
C
G
N
D
D
V
B
A
T
G
N
D
D
FAN_CTL1
V
C
C
FAN_CTL2/GP51
FAN_TAC1
SOUT2/JP6
FAN_TAC2/GP52FAN_TAC3/GP37
DTR2#/JP4RTS2/JP5
DSR2#/GP64
SIN2/GP63
VID1/GP31VID0/GP30
VID2/GP32
G
N
D
A
FAN_CTL4/JSBB2/GP27FAN_CTL5/JSBB1/GP26
G
N
D
D
FAN_CTL3/GP36
VID5/GP35VID4/GP34VID3/GP33
FAN_TAC4/JSBCY/GP25FAN_TAC5/JSBCX/GP24
JSAB2/GP23/SIJSAB1/GP22/SCK
JSACX/GP20JSACY/GP21
MIDI_OUT/GP17MIDI_IN/GP16/SO2RESETCON#/CIRTX/GP15/CE_NPCIRST1#/SCRRST/GP14
CTS2#/GP65
RI2#/GP67DCD2#/GP67
SIN1SOUT1/JP3
DSR1#RTS1#/JP2DTR1#/JP1
PWROK1/SCRPFET#/GP13PCIRST2#/SCRIO/GP12PCIRST3#/SCRCLK/GP11
LRESET#
CTS1#
RI1#DCD1#
PD7
LDRQ#SERIRQLFRAME#LAD0LAD1LAD2LAD3
KRST#/GP62
PD6PD5PD4PD3PD2PD1PD0
STB#
V
I
D
V
C
C
GA20
PCICLK
PCIRST5#/GP50
CLKIN
DENSEL#MTRA#ETS_DAT/MTRB#DRVA#EST_CLK/DRVB#WDATA#DIR#STEP#HDSEL#WGATE#RDATA#TRK0#INDEX#WPT#DSKCHG#
IRTX/GP47
COPEN#
IRRX/GP46
SUSB#/GP45PWRON#/GP44PME#/GP54PANSWH#/GP43PSON#/GP42SUSC#/GP53
AFD#ERR#INIT#
SLIN#ACK#BUSY
PESLCT
VIN0VIN1VIN2VIN3/ATXPGVIN4VIN5VIN6VIN7/PCIRSTIN#VREF
TMPIN1TMPIN2TMPIN3/SO1
RSMRST#/CIRRX/GP55PCIRST4#/SCRPSNT#/GP10
MCLK/GP56MDAT/GP57KCLK/GP60KDAT/GP61
3VSBSW#/GP40PWROK2/GP41
V
C
C
H
R112 10K_NL
10K_NLR1161
R209 10K
Q6SI2307DS
D15
MMBD4148
A
C
10K_NLR1171
J13
PFL-2x20-2M0-SMD-S
246810
13579
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
Q5BSS138/SOT
U10
SST25LF080A
12
34
6
5
7
8
CE#SO
WP#GND
CLK
SI
HLD#
Vcc
10K_NLR1181
10KR1921
C220
1nF1
10KR1911
1KR1281
C153
1uF
1
R2810K
1
10KR1131
R194470
1
R195 30K
R19310K
1
C335
1uF
1
Q11MMBT3904/SOT
10K_NLR1141
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE:Reg. SGCR5 bit [15,9] =[1,0]LED3 = ActLED2 = Link
DESIGN NOTE: PlaceESD protectioncomponents as close tothe USB/Ethernetconnector as possible.
M-Systems uDOC ConnectorDESIGN NOTE: Jumperpins 3 & 4, 5 & 6 whenuDOC is not used.
DESIGN NOTE: WhenuDOC is used USB2 isnot available.
DESIGN NOTE: Pin 9on header should becut off.
DESIGN NOTE: Do notviolate USB 2.0 routingrequirements whenrouting USB2.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 18 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
USB2_CON-USB2_CON+
USB2_CON+
USB2_CON-
TXM115
RXM115
TXP115
RXP115
USB2-12USB2+12
USB_PWR_EN212
USB_OC#12USB_PWR_EN112
USB0-12
USB0+12
USB1-12
USB1+12
P1LED215
P1LED315
P2LED215
TXP215TXM215
RXP215RXM215
P2LED315
USB3-12
USB3+12
LAN_CHASSIS
DGND
VCC_USB1
DGND
DGND
VCC_USB0
DGND
VCC3
DGND
VCC_USB3
VCC_USB1
VCC_USB0
DGND
DGND
VCC5
VCC5
DGND
VCC3V_LAN
VCC5
DGND
DGND
VCC3
DGND
LAN_CHASSIS
DGND
DGND
VCC3
VCC_USB2
VCC_USB3
VCC3V_LAN
DGND
DGNDDGND
DGNDDGND
VCC3
LAN_CHASSIS
VCC_USB2
R12910K
1
R13449.9,1%
1
FB22HI1206N101R-00
1
C223
100nF
1
C227
470pF
1
C237
100nF
1
C1002
100nF_NL
1
R12049.9,1%
1
FB18HI1206N101R-00
1
J14
CON-COMBO-USB2-ETH1
1
23
4
5
67
8
910
11
12
1314
1516
1718
1920212223242526VCC1
-DATA1+DATA1
GND1
VCC2
-DATA2+DATA2
GND2
TCT+TX
-TX
+RX
-RXRCT
-LED1+LED1
-LED2+LED2
SHDSHDSHDSHDSHDSHDSHDSHD
R1003 220
C233
100uF
1
L4CMF-3216-0090A-N2
4 3
1 2
R12310K
1
C225
100nF
1
R1004 220
1 SS2
J15
CON-COMBO-USB2-ETH1
1
23
4
5
67
8
910
11
12
1314
1516
1718
1920212223242526VCC1
-DATA1+DATA1
GND1
VCC2
-DATA2+DATA2
GND2
TCT+TX
-TX
+RX
-RXRCT
-LED1+LED1
-LED2+LED2
SHDSHDSHDSHDSHDSHDSHDSHD
R12410K
1
C228
100uF
1
KEYGNDUSB+USB-
VCC5II
OONCNC
NC
J16
uDOC
246810
13579
L7CMF-3216-0090A-N2
4 3
1 2
1 SS4
R12149.9,1%
1
C234
470pF
1
FB19HI1206N101R-00
1
1 SS1
FB1001
MLB-201209-0120P-N2
1
2
FB24HI1206N101R-00
1
C229
470pF
1
1 SS3
1 SS6
U13
LM3526H
12
34
5
6
7
8
ENAFLGA
FLGBENB
OUTB
GND
IN
OUTA
C235
100uF
1
FB25HI1206N101R-00
1
1 SS5
FB21MLB-201209-0120P-N2
1 2
R11949.9,1%
1
FB1000
MLB-201209-0120P-N2
1
2
C238
100nF
1
R13149.9,1%
1
C1000
100nF_NL
1
L5CMF-3216-0090A-N2
4 3
1 2
FB20HI1206N101R-00
1
U12
LM3526H
12
34
5
6
7
8
ENAFLGA
FLGBENB
OUTB
GND
IN
OUTA
C226
100uF
1
C236
470pF
1
C230220pF
1
FB17HI1206N101R-00
1
1 SS8
L6CMF-3216-0090A-N2
4 3
1 2
C224
100nF
1
R13249.9,1%
1
R1001 220
1 SS7
FB23HI1206N101R-00
1
R12249.9,1%
1
C231
100nF
1
R1002 220
R13349.9,1%
1
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: Route PCI CLOCK trace 1.5inches shorter than other PCI clocks. Lengthof PCI clock on MiniPCI cards will typicallybe 1.5 inches. Confirm with cardmanufacturer.
DESIGN NOTE: Consult MiniPCI cardmanufacturer for any special design orlayout considerations of MiniPCI slot toaccomidate a particular MiniPCI card.
National Semiconductor Confidential
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 19 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
PCI_AD30
PCI_AD4
PCI_AD23PCI_AD24
PCI_AD6
PCI_AD17
PCI_AD28
PCI_AD31
PCI_AD10
PCI_AD27
PCI_AD29
PCI_AD26
PCI_AD11
PCI_AD9
PCI_AD15
PCI_AD12
PCI_AD19
PCI_AD25
PCI_AD0
PCI_AD20
PCI_AD13
PCI_AD22
PCI_AD2
PCI_AD21
PCI_AD7
PCI_AD1
PCI_AD5
PCI_AD3
PCI_AD8
PCI_AD21
PCI_AD29
PCI_AD27
PCI_AD14
PCI_AD12
PCI_AD19
PCI_AD0
PCI_AD13
PCI_AD6
PCI_AD24
PCI_AD9PCI_AD10
PCI_AD20
PCI_AD5
PCI_AD31
PCI_AD16
PCI_AD8PCI_AD7
PCI_AD4
PCI_AD11
PCI_AD23
PCI_AD16PCI_AD25
PCI_AD1
PCI_AD28
PCI_AD26
PCI_AD22
PCI_AD15
PCI_AD30
PCI_AD3
PCI_AD18
PCI_AD2
PCI_AD17
PCI_AD18
PCI_SERR#
PCI_PERR#
PCI_PERR#
PCI_SERR#
PCI_AD23
PCI_AD14
PCI_INTB# 11,15,24PCI_INTA#9,11,24
PCI_AD[31:0]9,11,15,20,24
CLK_EXT19
REQ#_MPCI9 GNT#_MPCI 9
PCI_RST# 9,11,12,15,16,17,20,24,25
PME# 11,15,17,25
PCI_C/BE2#9,11,15,20,24
PCI_C/BE3#9,11,15,20,24
PCI_C/BE0# 9,11,15,20,24
PCI_C/BE1#9,11,15,20,24
PCI_PAR 9,11,15,20,24
PCI_STOP# 9,11,15,20,24PCI_TRDY# 9,11,15,20,24PCI_FRAME# 9,11,15,20,24
PCI_DEVSEL# 9,11,15,20,24
PCI_IRDY#9,11,15,20,24
DGND
DGND
DGNDDGND
VCC3VCC5
VCC3SB
VCC3SB
VCC3
VCC5
VCC3
C241
100nF
1
C239
22uF
1
R136 10K
C242
100nF
1
C243
100nF
1
J17
PCITYPEIII
1 2
3 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 98
10099101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120121 122123 124
TIP RING
RD+ TD+RD- TD-TERMINATION TERMINATIONTERMINATION TERMINATIONLED1_GRNP LED2_YELPLED1_GRNN LED2_YELNCHSGND RESERVEDINTB# 5V3.3V INTA#RESERVED RESERVEDGND 3.3VAUXCLK RESET#GND 3.3VREQ# GNT#3.3V GNDAD31 PME#AD29 RESERVEDGND AD30AD27 3.3VAD25 AD28RESERVED AD26C/BE3# AD24AD23 IDSELGND GNDAD21 AD22AD19 AD20GND PARAD17 AD18C/BE2# AD16IRDY# GND3.3V FRAME#CLKRUN# TRDY#SERR# STOP#GND 3.3VPERR# DEVSEL#C/BE1# GNDAD14 AD15GND AD13AD12 AD11AD10 GNDGND AD9AD8 C/BE0#AD7 3.3V3.3V AD6AD5 AD4RESERVED AD2AD3 AD05V RESERVED_WIP
RESERVED_WIPAD1GND GNDAC_SYNC M66ENAC_SDATA_IN AC_SDATA_OUTAC_BIT_CLK AC_CODEC_ID0#AC_CODEC_ID1# AC_RESET#MOD_AUDIO_MON RESERVEDAUDIO_GND GNDSYS_AUDIO_OUT SYS_AUDIO_INSYS_AUDIO_OUT_GND SYS_AUDIO_IN_GNDAUDIO_GND AUDIO_GNDRESERVED MPCIACT#VCC5VA 3.3VAUX
C244
22uF
1
C245
100nF
1
C246
100nF
1
C247
100nF
1
C240
100nF
1
R135 100
R137 10K
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DESIGN NOTE: Configuration StrapsAEN - 1 = Factory Test 0 = Normal operationBALE - 1 = Positive decode on BIOS address range 0 = BIOS address range disabledTC - 1 = Enable SMB Boot ROM Configuration 0 = Disabe SMB Boot ROM Configuration
DESIGN NOTE: Install in orderto disable the bridge. This is atemporary measure.
40744 DAMD GEODE LX EPIC RDK Reference Schematic
B 20 26Wednesday, April 11, 2007
Advanced Micro Devices1351 South Sunset St.Longmont CO 80501
Title
Size
Document Number Rev
Date: Sheetof
*AMD CONFIDENTIAL*
PCI_AD1
PCI_AD18
PCI_AD5
PCI_AD16
PCI_AD8
PCI_AD19PCI_AD20
PCI_AD28
PCI_AD0
PCI_AD11
PCI_AD14
PCI_AD3
PCI_AD23
PCI_AD31
PCI_AD6
PCI_AD25
PCI_AD27
PCI_AD12PCI_AD13
PCI_AD9
PCI_AD2
PCI_AD7
PCI_AD21
PCI_AD30
PCI_AD26
PCI_AD22
PCI_AD15
PCI_AD4
PCI_AD17
PCI_AD10
PCI_AD24
PCI_AD29
ISA_SA1ISA_SA2
ISA_SA0
ISA_SA8
ISA_SA4
ISA_SA7
ISA_SA5
ISA_SA9
ISA_SA3
ISA_SA11ISA_SA12
ISA_SA10
ISA_SA6
ISA_SA18
ISA_SA14
ISA_SA17
ISA_SA15
ISA_SA19
ISA_SA13
ISA_LA20ISA_LA21
ISA_SA16
ISA_SMEMR#
ISA_LA23
ISA_SMEMW#
ISA_LA22
ISA_IOR#
ISA_IOCHCK#
ISA_IOCS16#ISA_IOCHRDY
ISA_MASTER#
ISA_MEMCS16#
DRQ5DRQ6
DRQ3
ISA_TC
DRQ1DRQ0
DRQ2
DRQ7
ISA_SD11
ISA_SD14
ISA_SD9
ISA_SD4
ISA_SD8
ISA_SD6
ISA_SD0
ISA_SD7
ISA_SD5
ISA_SD12
ISA_SD1
ISA_SD3
ISA_SD15
ISA_SD13
ISA_SD10
ISA_SD2
B
R
D
G
_
L
O
C
K
#
B
R
D
G
_
S
E
R
R
#
B
R
D
G
_
P
E
R
R
#
B
R
D
G
_
C
L
K
R
U
N
#
B
R
D
G
_
P
P
R
E
Q
#
B
R
D
G
_
P
P
G
N
T
#
ISA_BCLK
ISA_RSTDRV
ISA_MEMW#ISA_MEMR#
ISA_SBHE#
ISA_BALEISA_AEN
ISA_IOW#
ISA_REFRESH#
ISA_AEN
ISA_BALE
ISA_TC
ISA_NOWS#