COMPLETE TEARDOWN WITH:

• Detailed photos and cross-sections

• Precise measurements

• Material analysis

• Manufacturing process flow

• Supply chain evaluation

• Manufacturing cost analysis

• Estimated sales price

• Comparison with NVIDIA Tesla and TSMC CoWoS

AMD Radeon Vega Frontier Edition

Title: AMD Radeon Vega with HBM2

Pages: 130

Date: November 2017

Format: PDF & Excel file

Price: Full report: EUR 3,490

New GPU is AMD’s first with Samsung 8-Hi second generation high bandwidth memory and the latest 2.5D chip-on-wafer packaging from SPIL

Two years after the release of the Radeon Fury X, using the world’s first on-chipintegrated high bandwidth memory (HBM), at CES 2017, AMD presented theRadeon Vega graphics procession unit (GPU), featuring second generation HBM(HBM2). We have analyzed the Radeon Vega Frontier Edition, which can do 13 or25 trillion floating point operations per second (TFLOPS) depending on thefloating point format. The GPU has a 16GB high bandwidth cache, assembledfrom two 8-Hi HBM2 stacks.

In a smaller, 47x47mm 10-layer flip-chip ball grid array (fcBGA) package, thecomponent uses more than 2,800mm² of silicon, an impressive silicon-to-packageratio.

Compared to NVIDIA, which uses only TSMC to manufacture the Pascal GPU, AMDhas chosen to use multiple sources to produce the Vega GPU. The GPU die is madeby GlobalFoundries with a 14nm FinFET process, giving it 12.5 billion transistors.The interposer, with via-middle through silicon via (TSV) technology, is provided byUMC, which was also the provider for the Radeon Fury X. The 2.5D assembly of thecomponent is done by two sources, with Taiwan’s SPIL estimated to be the mainone. It uses SPIL's ‘CoW-last’ Chip-on-Wafer after Through-Silicon Interposerprocess.

Regarding the HBM2, only two stacks of 8GB are used to obtain the 16GB capacity.As for NVIDIA’s GPUs, Samsung is the provider of the HBM2 stacks, whereas SK-Hynix was the supplier for previous Radeon Fury X. The 8GB HBM2 consists of eight1GB HBM2 dies and a buffer die at the bottom of the stack, which are all verticallyinterconnected by TSVs and microbumps.

The report includes a complete physical analysis of the packaging process, withdetails on all technical choices regarding processes, equipment and materials. Also,the complete manufacturing supply chain is described and manufacturing costs arecalculated.

The report compares the Radeon Vega solution with NVIDIA’s Tesla P100,highlighting the integration choices made by both companies. Also, the reportfeatures a comparison with AMD’s Fury X, which uses HBM1 and 2.5D assembly, toexplain the interest in evolution through the HBM2 and CoW 2.5D platforms.

TABLE OF CONTENTS

Overview / Introduction

Company Profile and Supply Chain

Physical Analysis

• AMD Radeon Vega Frontier Edition Teardown

• Package

View, dimensions and marking Die sizes

• DRAM Die

View, dimensions and marking µBumps and TSVs

• Package Cross-Section

Laminate and frame cross-section

Interposer cross-section GPU cross-section 8-Hi HBM2 stack cross-section

• Comparison with AMD Fury X including SK-Hynix HBM1

• Comparison with NVIDIA Tesla P100 including Samsung 4-Hi HBM2

Manufacturing Process Flow

• Global Overview

• GPU Process Description

• HBM2 Stack Process Flow

• Interposer Process Flow

• CoW and Final Assembly

Process Flow

Cost Analysis

• Overview of the Cost

Analysis

• Yield Hypotheses

• GPU Front-End and Die Cost

• Interposer Wafer and Die

Cost

• DRAM Front-End Cost TSV manufacturing cost Micro-bumping

manufacturing cost

• DRAM Die Cost

• Logic Die Cost

• 8-Hi HBM Stack Cost

• CoW Assembly

Manufacturing Cost

• Final Component Cost

Estimated Price Analysis

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AUTHORS:

charge of structure analysis ofsemiconductors. She has deepknowledge of chemical andphysical technical analyses. Shepreviously worked for 20 yearsat Atmel’s Nantes Laboratory.

VéroniqueLe Troadec(Lab)

Véronique is in

analyses for AdvancedPackaging, MEMS and IC. He haspublished numerous reports onadvanced packaging devicesincluding fan-in and fan-outWLP, embedded die packagingand 3D TSV packaging.

Romain Fraux

R o m a i n i s i ncharge of costing

3D Package CoSim+

IC Price +

ANALYSIS PERFORMED WITH OUR COSTING TOOLS 3D PACKAGE COSIM+ AND IC PRICE+

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Cost simulation tool to evaluatethe cost of any Packagingprocess: Wafer-level packaging,TSV, 3D integration…

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(GPU) with HBM2

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System-in-Package

Includes 3D stacked memory with2.5D integration on a siliconinterposer in a Chip-on-Wafer-on-Substrate (CoWoS) process.

A closer look at the impressive,industry-first, tri-layer stacked CIS.This innovative CIS is Sony’s nextgeneration technology.

The 1st ultra-small multi-die lowpower module with boot memoryand power management integratedin a PoP compatible device for theIoT.

Pages: 130Date: October 2017Full report: EUR 3,490*

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