amkor’s next generation package technologies · amkor confidential i oct-15 7 2.5d mcm tsv...
TRANSCRIPT
Amkor Confidential I Oct-15 1
Amkor’s Next Generation Package Technologies Paul Silvestri: Director, TSV Product Development
Amkor Confidential I Oct-15 2
Agenda
Packaging Evolution
TSV Platform and Status
SLIM Technology
SWIFT Technology
Moving Forward
Amkor Confidential I Oct-15 3
Packaging Evolution
Amkor Confidential I Oct-15 4
Semiconductor Packaging Evolution
Board Space Performance Higher bandwidth Lower power Increased
functionality
Multi-die integration Form-factor
(thin & small) Reduced board
complexity (cost)
Cost Reduction Advanced silicon
node avoidance Chip size reduction
Amkor Confidential I Oct-15 5
Semiconductor Packaging Interconnect Evolution
100 µm 10 µm 1 µm 10 nm
PCB Design Rule Wafer Design Rule
Organic Substrate
GAP! BEOL
~ 1-8µm
Highest Cost
Lowest Cost
BUMP & RDL
Substrate
OSAT
Foundry
Evolving
Amkor Confidential I Oct-15 6
Amkor’s TSV Package Platform
Amkor Confidential I Oct-15 7
2.5D MCM TSV Interposer Progress Side-by-side stacking on interposer
– Wide variety of 2.5D products supported Multiple logic and/or Memory die on thinned interposer Many years of development completed Several products in production 2.5D MEOL & assembly line qualified for production Primarily large package body focused (25-55mm)
– Logic + Memory on Interposer – Logic + Logic on Interposer
LogicHBM HBM
Amkor Confidential I Oct-15 8
2.5D Product Experience/TV Floor Plan Applications Platform Graphics/HPC Network/Server FPGA Network/Server
Interposer Si Si Si Si Organic
Logic 40/28 nm 28 nm 28 nm 28 nm 40/45 nm
Memory/ Small Logic DRAM HBM (x2/x4) RLDRAM (x1/x4) HBM
starting 2016 SerDes HBM/TV
Status Qualified Qualified/LVM 2015 Qualified/ LVM 2016 Qualified/LVM 2013 Under Development
Floor Plan
Substrate Si interposer Organic Interp. Logic Memory/ Small Logic
Amkor Confidential I Oct-15 9
Keys to Successful Interposer Assembly
Reliability & Test
MEOL
Warpage Control
Chip Attach
Amkor Confidential I Oct-15 10
MEOL: Middle End of Line MEOL
Amkor Confidential I Oct-15 11
TSV General Process Flow
TSV Processing
TSV Wafer Fabrication
Front Side Bumping Assembly Test Back Side
Bumping MEOL2 MEOL1
Completed TSV Structure
MEOL - 1 Backside Bump MEOL - 2
Temp. Wafer Bond
Wafer Thin
Si Dry Etch PECVD CMP Backside RDL & Bump Temp. Wafer
De-Bond Dicing
Amkor Confidential I Oct-15 12
2.5D Interposer MEOL-1: TSV Processing
MEOL - 1 Backside Bump
Temp. Wafer Bond
Wafer Thin
Si Dry Etch PECVD CMP Backside RDL & Bump
Amkor Confidential I Oct-15 13
2.5D Interposer MEOL-2: De-Bond & Dice
MEOL - 2
Temp. Wafer De-Bond Dicing
Amkor Confidential I Oct-15 14
Silicon Interposer Assembly Chip
Attach
Amkor Confidential I Oct-15 15
Interposer on Substrate Package Assembly Flow
Interposer Attach
Top Die Attach
Underfill Stack
Amkor Confidential I Oct-15 16
0
200
400
600
800
1000
0 200 400 600 800 1000 1200
Logi
c (la
rge
die)
are
a (m
m2)
Si interposer area (mm2)
2.5D Chip on Substrate Process Window Qualified for wide range of Si interposer sizes
including greater than reticle size – up to 33mm x 26mm
– Stitching support for > 32mm x 25mm available
Low volume manufacturing underway to support customer product launches – 300mm2-600mm2 Logic, 28nm Si
– 500mm2-1000mm2 Si interposer
– 1, 2 & 4 HBM placements
– 45mm-55mm body FCBGA typ.
– Integrated heat spreader
– Interim and final test support Reticle size
I: 33 x 27mm
I: 36 x 28mm
I: 32 x 26mm
L: 26 x 22mm
L: 26 x 20mm
L: 22 x 18mm
L: Logic die size I: Si interposer size CoS
Both CoS and CoW
Amkor Confidential I Oct-15 17
Reliability Reliability
Amkor Confidential I Oct-15 18
2.5D MCM TSV Product Qualification Data Product 1 Product 2 Product 3 Product 4
Package type 2.5D TSV FCBGA 2.5D TSV FCBGA 2.5D TSV FCBGA 2.5D TSV FCBGA
Package dimensions 45 x 45 mm 55 x 55 mm 50 x 50 mm 25 x 25 mm
Interposer size 26 x 32 mm 28 x 36 mm 26 x 32 mm 21.5 x 22.0 mm
Logic die size 19.5 x 26.0 mm 22 x 26 mm 18 x 18 mm 5.0 x 12.7 mm
Memory size 5.48 x 7.29 mm 5.48 x 7.29 mm 9 x 9 mm 10.9 x 16.0 mm
Memory type x4 HBM x4 HBM x2 die x1 die
Moisture Sensitivity Level MSL4 @ 260'C 90/90 90/90 90/90 MSL4 @ 260'C 90/90 90/90 90/90 MSL4 @ 245'C 50/50 50/50 MSL3 @ 245'C 20/20 45/45
Highly Accelerated Stress Test 130'C/85% 96hrs 45/45 45/45 45/45 130'C/85% 96hrs 45/45 45/45 45/45 130'C/85% 96hrs 25/25 25/25 130'C/85% 96hrs n/a 15/15
Temperature Cycling Test T/C-B 1000x 45/45 45/45 45/45 T/C-G 1000x 45/45 45/45 45/45 T/C-B 1000x 25/25 25/25 T/C-B 1000x 20/20 25/25
T/C-B 2000x 45/45 n/a n/a T/C-G 2000x 45/45 n/a n/a T/C-B 2000x n/a 25/25 T/C-B 2000x n/a n/a
High Temperature Storage Test 150'C 1000hrs 45/45 45/45 45/45 150'C 1000hrs 45/45 45/45 45/45 150'C 1000hrs 25/25 25/25 150'C 1000hrs n/a 15/15
Amkor Confidential I Oct-15 19
Next Level of Package Integration SLIM : Silicon-Less Interposer Module
Amkor Confidential I Oct-15 20
System level cost benefit
Package price
sensitive
2.5D Proliferation = Interposer Dependency
Network Computing
Gaming HE Tablet
HDTV Computing
Value Tablet Smartphone
2013 2015 2017
Amkor Confidential I Oct-15 21
SLIMTM Package Definition
Amkor Confidential I Oct-15 22
SLIM™: Amkor’s Most Advanced Packaging Solution Silicon-Less Interposer Module (SLIM)
2.5D TSV Si Interposer
Foundry BEOL layers retained
Same CuP bond pads
Same UBM and solder bump
No TSV
Much thinner
Leverage 2.5D TSV Platform
SLIM™ (non-TSV interposer)
Amkor Confidential I Oct-15 23
SLIM™ // 2.5D Construction Comparison
Top Die Cu-Pillar Bumps
TSV C4
BEOL Layer M1 Contact
2.5D
Amkor Confidential I Oct-15 24
SLIM Interposer
SLIM™: Process Differentiation Basic process
– SLIM wafer processing complexity is reduced from 2.5D Silicon Interposer
MEOL Process
2. Si Etch (Dry)
3. Passivation (PECVD)
4. TSV Reveal (CMP)
5. UBM + Bump
1. Wafer Thinning
1. Wafer Thinning simplified
2. Si Etch (Dry) simplified
3. UBM + Bump
Silicon as Sacrificial
Platform
X X
2.5D Silicon Interposer
Amkor Confidential I Oct-15 25
SLIM™: Value Proposition Lower cost
– Simplified wafer construction – Simplified wafer processing
Supply chain flexibility – No longer tied to TSV foundry
Reduction in package thickness – Simplified wafer construction
Leverages 2.5D wafer processing, assembly equipment, and expertise
– 2.5D production line is in place
Amkor’s SLIM™
Lower Cost
Supply Chain Flexibility
Thin
Amkor Confidential I Oct-15 26
SLIM™ Package Assembly Flow POP Pillars
200 µm Pitch Or TMV® Opt.
RDL for Memory Interface (If Required)
30-50 µm Bump Pitch
Molded Wafer: Thinning As Required Top Of Package: RDL If Necessary For POP Chip Attach & UF
Interposer With < 1 µm L/S Foundry BEOL
Wafer Mold
< 0.35 mm Total Height
Carrier Remove & Ball Drop
Amkor Confidential I Oct-15 27
SLIM Package Variants
Wafer SLIM FI-POP Substrate SLIM TMV-POP
Memory
SLIM Interposer
Logic Memory
Substrate
Substrate SLIM Large Body 2.5D
Substrate
SLIM Interposer
Logic A Logic B
Substrate SLIM Small Body 2.5D
Amkor Confidential I Oct-15 28
Amkor’s Advanced Fan-out Package Platform
Amkor Confidential I Oct-15 29
SWIFTTM Package Definition
Amkor Confidential I Oct-15 30
SLIM vs SWIFT Signal Routing Capacity
SLIM and SWIFT cover different design space
Via Capture Pad Diameter (um)1.0 2.0 3.0 14.0 20.0
0.5 950 925 900 n/a n/a2.0 225 225 200 150 1003.0 n/a n/a n/a 75 505.0 n/a n/a n/a 50 25
Line and Space (um)
No of Signals/mm/Layer
Amkor Confidential I Oct-15 31
Silicon Wafer Integrated Fan-out Technology RDL for Memory Interface
(Opt.) 40 µm Pitch
RDL & Copper Pillar Bump (Opt.)
Chip Attach & UF
Carrier
Wafer Mold
< 0.30 mm Total Height
Carrier
Die 1 Die 2
POP Pillars 200 µm Pitch (Opt.)
SWIFT™
Top Side Routing For Memory Interface
Carrier Remove & Ball Drop
Amkor Confidential I Oct-15 32
SWIFT Key Enabling Process Technologies
300mm with mold capability
Fine L/S RDL ≥ 2um Stepper capability Multilayer to 3 layers
Through mold interface (Tall Cu Pillar or TMV) > 180um tall CuP bump
Fine pitch u-bump interconnection 40um pitch qualified 30um pitch demonstrated
Amkor Confidential I Oct-15 33
SWIFT™: Silicon Wafer Integrated Fan-out Technology
Utilize existing bump & assembly infrastructure – Polymer based – Flexible Single-die & Multi-die integration capable
– Advanced die integration Stepper capability down to 2 µm line/space Die shift/orthogonal rotation elimination 30 µm in-line copper pillar pitch demonstrated
– 3D capability TMV or Cu pillars to support POP structures
SWIFTTM 2 Die Overmold
SWIFTTM 2 Die Exposed
SWIFTTM 2 Die TMV PoP Overmold
SWIFTTM 2 Die Fan-in PoP
Amkor Confidential I Oct-15 34
Differentiating SWIFT & Fan-Out Packages
Key Attributes SWIFT WLFO
Top Die extra bump + underfill eWLB
Wafer Process Cu pillar for fine pitch None required
Die Dedication Die last Die first
Die Attach High accuracy FC bond Only to known good RDL site
High accuracy D/A (slow); Orthogonal Rotation Error
Patterning Stepper Mask align or Stepper
Line/Space 2-10 µm 6-15 µm
# RDL Layers 1-3 1-2
Amkor Confidential I Oct-15 35
Summary … the future is now!
Amkor Confidential I Oct-15 36
Amkor’s Advanced Wafer Product Positioning Multi dies, SoC partition, 3D compatible < 2 µm L/S by foundry interposer BEOL; No TSV High performance (CPU/GPU), mobile AP, BB
Multi die, SoC partition, HBM, 3D compatible RDL 2 ~ 10 µm by bumping line; mobile AP/BB
Single or multi die integration RDL 6 ~ 12 µm by bump line; RFIC & PMIC
Single die RDL ~ ≥ 10 µm by bump line RF, WLAN, power etc.
W-SLIM
WLCSP
Performance
SWIFT
Fan-Out
Products: RF & Analog to Advanced Processors
Amkor Confidential I Oct-15 37
Amkor’s Advanced Flip Chip Product Positioning
Multi die, SoC partition, HBM, 3D compatible ≤ 2 µm L/S by foundry BEOL interposer Ultra thin; no TSV Lower cost; SLIM ˂ 2.5 D
Multi die, SoC partition, HBM, 3D compatible ≤ 2 µm L/S by foundry BEOL interposer + TSV
HBM integration RDL 2 ~ 10 µm L/S by Amkor
Single or multi die RDL > 10 µm L/S by substrate 3D compatible
S-SLIM
Advanced fcCSP/FCBGA
Performance
2.5 D
S-SWIFT
Products: AP, BB, CPU, GPU and networking
Amkor Confidential I Oct-15 38
Contact Paul Silvestri Director TSV Products [email protected]
Ron Huemoeller Corporate VP & WW Head of R&D [email protected]