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Synchronization of Primary Multiplexers Siemens
TT2550EU01AL_011
Contents
1 Clock Distribution in a Synchronous 64 kbit/s Network 3
1.1 Synchronous Operation Mode 4
1.2 Clock Precision and Frame Slip 8
2 Exercise 9
Synchronization of Primary Multiplexers
Siemens Synchronization of Primary Multiplexers
TT2550EU01AL_012
Synchronization of Primary Multiplexers Siemens
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1 Clock Distribution in a Synchronous64 kbit/s Network
Siemens Synchronization of Primary Multiplexers
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1.1 Synchronous Operation Mode
The use of PCM30 as digital signal multiplexer is based on the precondition that inthe direction of transmission the data source and the clock supply on transmit side ofM30 are synchronous; the same for the receive direction: the clock supply of thePCM30 and the data destination must be synchronous, i.e. they must have in eachcase one common clock generator.
Fig. 1 shows an example of a possible clock distribution. At station A is located themaster clock generator, which receives a signal with highly precise frequency from anetwork-central master frequency. The master clock generator itself supplies the sub-multiplexer ZD-A3 and the PCM30 with the master clock via the respective clockinput.
Synchronization of Primary Multiplexers Siemens
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Station A
Master frequency
Station B Station C
Master clock
generator
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1 n
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T3an
64 kbit/s
S
E
1
30
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DTE
Subbitrates
2 Mbit/s
E
S
2 Mbit/s
S
E
T3inT3out
2 Mbit/s
2 Mbit/s
E
S
TS
1
30
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64 Kbit/s
Subbitrates
TS
DTE
PCM30 PCM30 PCM30 PCM30
TS TS
PCM30 Primary Multiplexer T3in External Clock InputDTE Data Terminal Equipment T3out External Clock Output
TS Internal Loop for Timing Signal
Fig. 1 Example of clock distribution in a synchronous 64 kbit/s network
Siemens Synchronization of Primary Multiplexers
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There are no master clock generators at stations B and C. Therefore, in station B the2048-kHz-clock derived from the 2-Mbit/s-receive signal is relayed to a furtherPCM30G, so that the transmit side of the PCM30 operates with this master clock,too. In B and C the respective transmit side of PCM30 is operated with the receivingclock signal via internal loops.
A further loop in the submultiplexer ZD-A3 in station C allows to use the clock derivedfrom the 64-kbit/s-receive signal for the control of the transmitting clock signal supply.In this way the opposite direction (from C to A) is likewise supplied with the masterclock.
This synchronous mode of operation is the essential precondition for the ISDN(Integrated Services Digital Network).
Synchronization of Primary Multiplexers Siemens
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1
A
D
A
DPCM
MUX
2
30
2
30
A
D
A
D
PCM
MUX
TA
TA
TB
TB
A B
Fig. 2 PCM30-transmission, clock supply
Siemens Synchronization of Primary Multiplexers
TT2550EU01AL_018
1.2 Clock Precision and Frame Slip
With a clock precision of ... a frame slip occurs in ...
10-12 700 days
10-11 70 days
10-10 7 days
10-9 17 hours
10-8 1:40 hours
10-7 19 minutes
10-6 1 minutes
10-5 6 seconds
10-4 0,6 seconds
10-3 0,06 seconds
Synchronization of Primary Multiplexers Siemens
TT2550EU01AL_019
2 Exercise
Which signals, apart from the voice signals, may be transmitted via a 2-Mbit/s-signal?
Siemens Synchronization of Primary Multiplexers
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