1 68hc11 analog i/o chapter 12. 2 analog to digital converter (adc) what is it? converts an analog...
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68HC11 Analog I/O68HC11 Analog I/O
Chapter 12Chapter 12
22
Analog to Digital Converter (ADC)Analog to Digital Converter (ADC)What is it?What is it? Converts an analog voltage level to a digital output.Converts an analog voltage level to a digital output.
Dout = F(Vin)Dout = F(Vin)
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
'00
'01
'10
'11
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Analog to Digital ConvertersAnalog to Digital ConvertersTerminologyTerminology Full Scale Voltage: VFS=VH-VLFull Scale Voltage: VFS=VH-VL
Difference between maximum and minimum voltage levelsDifference between maximum and minimum voltage levels Bits (N): Number of bits in the digital outputBits (N): Number of bits in the digital output Resolution (LSB): smallest quantizing step sizeResolution (LSB): smallest quantizing step size
LSB = Vfs/2LSB = Vfs/2NN Conversion time: time needed for one conversionConversion time: time needed for one conversion Quantization error: Voltage error between digital Quantization error: Voltage error between digital
output and analog input.output and analog input. The maximum error is 1 LSBThe maximum error is 1 LSB
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Analog to Digital ConvertersAnalog to Digital ConvertersIn GeneralIn General
Given: VFS, N bitsGiven: VFS, N bits
LSB = VFS/(2LSB = VFS/(2NN))
Digital Output: DoutDigital Output: Dout
Analog Output: VoutAnalog Output: VoutVout = Dout*LSB = Dout * VFS/2Vout = Dout*LSB = Dout * VFS/2NN
Quantization Error = Vin - Vout Quantization Error = Vin - Vout
2 1Nin in
FS
V VDout INT INT
V LSB
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Analog to Digital ConvertersAnalog to Digital ConvertersExampleExample
Given: VFS=5V, N=2 bitGiven: VFS=5V, N=2 bit What is the bit resolution (LSB) and the transfer curveWhat is the bit resolution (LSB) and the transfer curve
Answer:Answer:
LSB = 5/(2LSB = 5/(222) = 1.25V) = 1.25V
0.000V < Vin < 1.25V 0.000V < Vin < 1.25V Dout = 00 Dout = 00
1.25V < Vin < 2.50V 1.25V < Vin < 2.50V Dout = 01 Dout = 01
2.50V < Vin < 3.75V 2.50V < Vin < 3.75V Dout = 10 Dout = 10
3.75V < Vin < 5.000V 3.75V < Vin < 5.000V Dout = 11 Dout = 11
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2-bit Analog to Digital Converter 2-bit Analog to Digital Converter Voltage Transfer CurveVoltage Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
'00
'01
'10
'11
Vin, V
Dout
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Analog to Digital ConvertersAnalog to Digital ConvertersExampleExample
Given: VFS=5V, N=8 bitsGiven: VFS=5V, N=8 bits What is Dout (in hex) for Vin=2.35VWhat is Dout (in hex) for Vin=2.35V
Answer:Answer:
LSB = 5/(2LSB = 5/(288) = 0.0195V = 19.5mV) = 0.0195V = 19.5mV
22NN = 256 = 256
Dout = INT(2.35V/19.5mV)=120=$78Dout = INT(2.35V/19.5mV)=120=$78
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Analog to Digital ConvertersAnalog to Digital ConvertersExampleExample
Given: VFS=5V, N=8 bits, Dout=$78Given: VFS=5V, N=8 bits, Dout=$78 What is the quantization error (in mV) if Vin=2.35VWhat is the quantization error (in mV) if Vin=2.35V
Answer:Answer:
LSB = 5/(2LSB = 5/(288) = 0.0195V = 19.5mV) = 0.0195V = 19.5mV
Vout = Dout*LSB = 120*19.5mV=2.34VVout = Dout*LSB = 120*19.5mV=2.34V
QE = Vout – Vin = 2.35V-2.34V = 10mVQE = Vout – Vin = 2.35V-2.34V = 10mV
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68HC11 A/D Converter68HC11 A/D Converter
8-bit resolution (256 bit levels)8-bit resolution (256 bit levels)8 channels: Port E8 channels: Port E
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Port EPort E
8-bit8-bit
Address $100AAddress $100A
Multi-FunctionMulti-Function Digital Input Port Digital Input Port Analog Input Port (Built-in A/D)Analog Input Port (Built-in A/D)
1111
Port E - $100A Data RegisterPort E - $100A Data Register
7 6 5 4 3 2 1 0
Bits
III IIIII
O=OutputI =InputB=Bidirectional
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Using the Using the 68HC11 A/D Converter68HC11 A/D Converter
Power-up the A/D SystemPower-up the A/D SystemConfigure the A/D conversion systemConfigure the A/D conversion system
Two modesTwo modesSingle channel scanSingle channel scanContinuous channel scanContinuous channel scan
Channel controlChannel controlConversion on a single channelConversion on a single channelConversion on four channelsConversion on four channels
Start the A/D conversionStart the A/D conversionPoll the conversion completion flag (CCF)Poll the conversion completion flag (CCF)Read the resultRead the resultSave the resultSave the result
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Reading the ResultsReading the Results
Load the ADC result from theLoad the ADC result from the
ADC Input Registers: ADC Input Registers: ADR1 = $1031ADR1 = $1031 ADR2 = $1032ADR2 = $1032 ADR3 = $1033ADR3 = $1033 ADR4 = $1034ADR4 = $1034
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Power the A/D ConverterPower the A/D Converter
7 6 5 4 3 2 1 0
Bits
CR2CR1DLY N/ACMEIRQECSELADPU
Option Register: $1039 System Configuration Options
ADPU = A/D Power-up 0 = A/D not powered up 1 = A/D powered up (need at least 100uS for process to stabilize)
CSEL = Clock select 0 = Use external clock (E-clock) for power up (default) 1 = Use internal clock for power up
CB = %11000000
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Configure the ADCConfigure the ADCA/D Control/Status Register A/D Control/Status Register
7 6 5 4 3 2 1 0
Bits
CACBMULT CCCDSCANN/ACCF
ADCTL Register: $1030 A/D Control/Status Register
SCAN = Continuous Scan Control 0 = One cycle of four conversions each time ADCTL is written 1 = Continuous conversions
MULT = Multiple Channel/Single Channel Control 0 = perform four consecutive conversions on a single channel 1 = perform four conversions on four channels consecutively
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A/D Control/Status Register A/D Control/Status Register Single Channel ModeSingle Channel Mode
7 6 5 4 3 2 1 0
Bits
CACBMULT CCCDSCANN/ACCF
ADCTL Register: $1030 A/D Control/Status Register
CD,CC,CB,CA = Channel Conversion Select Bits
CD CC CB CA Channel
0 0 0 0 PE00 0 0 1 PE10 0 1 0 PE20 0 1 1 PE30 1 0 0 PE40 1 0 1 PE50 1 1 0 PE60 1 1 1 PE7
Mult=0
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A/D Control/Status Register A/D Control/Status Register Multiple Channel ModeMultiple Channel Mode
7 6 5 4 3 2 1 0
Bits
CACBMULT CCCDSCANN/ACCF
ADCTL Register: $1030 A/D Control/Status Register
CD,CC,CB,CA = Channel Conversion Select Bits Mult=1
CD CC CB CA Channel
0 0 d d PE0-PE30 1 d d PE4-PE7
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A/D Control/Status RegisterA/D Control/Status RegisterConversion Completion Flag Conversion Completion Flag
7 6 5 4 3 2 1 0
Bits
CACBMULT CCCDSCANN/ACCF
ADCTL Register: $1030 A/D Control/Status Register
CCF = A/D Conversion Complete Flag 0 = Conversion not complete 1 = Conversion complete. Set when all four A/D result registers contain valid conversions
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Project Pseudo-CodeProject Pseudo-Code* Power ADC using Internal Clock* Power ADC using Internal Clock Option ($1039) Option ($1039) %11000000 %11000000
* Delay Loop * Delay Loop N=10N=10 For I = 1 to NFor I = 1 to N Next I Next I
* Configure ADC for * Configure ADC for * Single channel, single scan, PE0* Single channel, single scan, PE0* Set scan=0,mult=0, Cd,Cc,Cb,Ca to 0000* Set scan=0,mult=0, Cd,Cc,Cb,Ca to 0000 ADCTL ADCTL %00000000 ; This starts conversion %00000000 ; This starts conversion
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Project Pseudo-CodeProject Pseudo-Code* Wait for CCF Flag* Wait for CCF Flag Repeat Repeat Until CCF=1Until CCF=1
* Read Result* Read Result A A ADR1 ($1031) ADR1 ($1031)
* Save Result* Save Result Dout Dout A A
**
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TPS QuizTPS Quiz
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Initialization ExamplesInitialization ExamplesSingle channel, single scanSingle channel, single scan Set scan=0,mult=0Set scan=0,mult=0 Set Cd,Cc,Cb,Ca to select channelSet Cd,Cc,Cb,Ca to select channel
Single channel, continuous scanSingle channel, continuous scan Set scan=1,mult=0Set scan=1,mult=0 Set Cd,Cc,Cb,Ca to select channelSet Cd,Cc,Cb,Ca to select channel
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Initialization ExamplesInitialization ExamplesMultiple channel, single scanMultiple channel, single scan Set scan=0,mult=1Set scan=0,mult=1 Set Cd,Cc,Cb,Ca to select channel pairSet Cd,Cc,Cb,Ca to select channel pair
Either PE0-PE3 or PE4-PE7Either PE0-PE3 or PE4-PE7
Multiple channel, continuous scanMultiple channel, continuous scan Set scan=1,mult=1Set scan=1,mult=1 Set Cd,Cc,Cb,Ca to select channel pairSet Cd,Cc,Cb,Ca to select channel pair
Either PE0-PE3 or PE4-PE7Either PE0-PE3 or PE4-PE7
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Pseudo-code:Multi-Channel ModePseudo-code:Multi-Channel Mode68HC11 A/D Converter68HC11 A/D Converter
Initialize A/D conversion systemInitialize A/D conversion systemPower A/D systemPower A/D systemEnable A/D system ; This starts A/D conv.Enable A/D system ; This starts A/D conv.RepeatRepeatUntil CCF=1Until CCF=1For n = 1 to 4For n = 1 to 4
A A ADR(n) ; Read ADC register n ADR(n) ; Read ADC register nOut(n) Out(n) A ; Save conversion A ; Save conversionNext nNext n
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A/D SubroutineA/D Subroutine
**** Define Symbols**** Define Symbols*** Assume standard equates*** Assume standard equatesOPTION EQU $1039OPTION EQU $1039ADCTL EQU $1030ADCTL EQU $1030ADR1 EQU $1031ADR1 EQU $1031ADPU EQU %11000000ADPU EQU %11000000ADC EQU %00010100 ; Single scan-multi channelADC EQU %00010100 ; Single scan-multi channel ; PE4-PE7; PE4-PE7CCF EQU %10000000 ; CCFCCF EQU %10000000 ; CCFDelay EQU $1010 ; this is the delayDelay EQU $1010 ; this is the delayN EQU $04N EQU $04
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A/D SubroutineA/D Subroutine
**** Initialize the Interface**** Initialize the Interface**** X contains the address of the output string**** X contains the address of the output string**** B contains the number of values to collect**** B contains the number of values to collect Org ProgramOrg ProgramStart: LDY #Option ; Load address of A/D option register Start: LDY #Option ; Load address of A/D option register BSET 0,Y #ADPU ; This power ups the A/DBSET 0,Y #ADPU ; This power ups the A/D LDAA #DelayLDAA #DelayLoop: DECALoop: DECA BNE Loop ; This delay allows the A/D to power upBNE Loop ; This delay allows the A/D to power up LDAA #PE0 ; This are the bits to configure the ADCTLLDAA #PE0 ; This are the bits to configure the ADCTL STAA ADCTL ; Configure ADCTL and start conversionSTAA ADCTL ; Configure ADCTL and start conversion
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A/D SubroutineA/D Subroutine LDY #ADCTL ; This is the address of the ADCTLLDY #ADCTL ; This is the address of the ADCTLL0: BRCLR 0,Y #CCF L0 ; Stay here until CCF is setL0: BRCLR 0,Y #CCF L0 ; Stay here until CCF is set LDAB #NLDAB #NL1: LDY #ADR1L1: LDY #ADR1 LDX #OUTLDX #OUT LDAA 0,Y ; This will load the first conversionLDAA 0,Y ; This will load the first conversion STAA 0,X ; Save this conversionSTAA 0,X ; Save this conversion INX ; Point to next characterINX ; Point to next character INYINY DECBDECB BNE L1BNE L1 RTS ; Return from subroutineRTS ; Return from subroutine ORG DataORG DataOUT RMB 4OUT RMB 4
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Maximum Sampling RateMaximum Sampling Rate
Nyquist Theorem:Nyquist Theorem: Must sample at Must sample at twicetwice the maximum frequency of the input signal the maximum frequency of the input signal to reconstruct the signal from the samples.to reconstruct the signal from the samples.68HC11 Conversion time: 68HC11 Conversion time: 32 clock cycles = 32Tc32 clock cycles = 32Tc Maximum signal period: 1/(2Fmax)Maximum signal period: 1/(2Fmax)
32Tc = 1/2Fmax 32Tc = 1/2Fmax Fmax = 1/(64Tc) Fmax = 1/(64Tc)
Given Fclk=2Mhz Given Fclk=2Mhz Tc= 0.5uS Tc= 0.5uS Fmax=31.5KHzFmax=31.5KHz
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Aperture TimeAperture Time
The amount of time needed by ADC to The amount of time needed by ADC to sample the analog input is known as the sample the analog input is known as the “aperture time.” In the 68HC11, 12 “aperture time.” In the 68HC11, 12 cycles are needed to convert Vin.cycles are needed to convert Vin.
If the input signal changes considerable If the input signal changes considerable during the sample, we will see Aperture during the sample, we will see Aperture Jitter, signal “noise”, or signal error due Jitter, signal “noise”, or signal error due to the uncertainty of the input signal.to the uncertainty of the input signal.
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TPS QuizTPS Quiz
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