1 cs/coe0447 computer organization & assembly language chapter 2 part 1
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CS/COE0447
Computer Organization & Assembly Language
Chapter 2 Part 1
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Topics to cover in Chapter 2
• MIPS operations and operands• MIPS registers• Memory view• Instruction encoding
• Arithmetic operations• Logic operations• Memory transfer operations
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MIPS Operations/Operands
• “Operation” (instruction)• “Operand”
• MIPS operations– Arithmetic operations (integer/floating-point) (add, sub,…)– Logical operations (and, or,…)– Shift operations (shift a certain number of bits to the left or right)– Compare operations (do something if one operand is less than another,…)– Load/stores to transfer data from/to memory– Branch/jump operations– System control operations/coprocessor operations
• MIPS operands– General-purpose registers– Fixed registers, e.g., HI/LO registers– Memory location– Immediate value
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MIPS Arithmetic
• <op> <rdestination> <rsource1> <rsource2>
• All arithmetic instructions have 3 operands– Operand order is fixed: destination first– 32 registers (page 2 of green card)
• Examples– add $t0, $s0, $s2 # $t0 = $s0 + $s2– sub $s0, $t0, $t1 # $s0 = $t0 – $t1
rd rs rt
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MIPS Registers
r0r1r2r3r4r5r6r7r8r9
r10r11r12r13r14r15
r16r17r18r19r20r21r22r23r24r25r26r27r28r29r30r31
$zero$at$v0$v1$a0$a1$a2$a3$t0$t1$t2$t3$t4$t5$t6$t7
HILO
PC
$s1$s2$s3$s4$s5$s6$s7$t8$t9$k0$k1$gp$sp$fp$ra
$s0
General-Purpose Registers Special-Purpose Registers
32 bits 32 bits 32 bits
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General-Purpose Registers
• GPR: all can be used as operands in instructions
• Still, conventions and limitations exist to keep GPRs from being used arbitrarily
– r0, termed $zero, always has a value “0”– r31, termed $ra (return address), is reserved for subroutine call/return– Etc. (we’ll see otherc conventsion/limitations later)– Register usage and related software conventions are summarized in “application
binary interface” (ABI), which is important when writing system software such as an assembler and a compiler
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Instruction Encoding
• Instructions are encoded in binary numbers– Assembler translates assembly programs into binary numbers– Machine decodes binary numbers to figure out what the instruction is– MIPS has “fixed” 32-bit instruction encoding
• MIPS has several instruction formats– R-format: arithmetic instructions– I-format: transfer/branch/immediate format– J-format: jump instruction format– (FI/FR-format: floating-point instruction format)(later chapter)
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MIPS Instruction Formats
Name Fields Comments
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits
R-format op rs rt rd shamt funct Arithmetic/logic instruction format
I-format op rs rt address/immediate Transfer, branch, immediate format
J-format op target address Jump instruction format
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R-Format Instructions• Define “fields” of the following number of bits each: 6 + 5 +
5 + 5 + 5 + 6 = 32
6 5 5 5 65
opcode rs rt rd functshamt
• For simplicity, each field has a name:
For shift instructions:“shift amount”
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R-Format Example
• MIPS Instruction:add $8,$9,$10
Binary number per field representation:
Decimal number per field representation:
hex representation:
decimal representation:
On Green Card: Format in column 1, opcodes in column 3(Let’s look and then come back)
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M I P S Reference Data: CORE INSTRUCTION SET
NAME MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add add R R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}
Later
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R-Format Instructions (REMINDER)
• Define “fields” of the following number of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 32
6 5 5 5 65
opcode rs rt rd functshamt
• For simplicity, each field has a name:
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R-Format Example
• MIPS Instruction:add $8,$9,$10
Binary number per field representation:
Decimal number per field representation:
Now let’s fill this in
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R-Format Example
• MIPS Instruction:add $8,$9,$10
0 9 10 8 320Binary number per field representation:
Decimal number per field representation:
hex representation: 012A 4020hex
decimal representation: 19,546,144ten
000000 01001 01010 01000 10000000000hex
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I-Format Instructions• Define “fields” of the following number of bits each: 6 + 5 +
5 + 16 = 32
6 5 5 16
opcode rs rt immediate
• For simplicity, each field has a name:
Let’s do an example using addi
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M I P S Reference Data: CORE INSTRUCTION SET
NAME MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add add R R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}
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I-Format Example
• MIPS Instruction:addi $8,$9,7
Binary number per field representation:
Decimal number per field representation:
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I-Format Example
• MIPS Instruction:addi $8,$9,7
Binary number per field representation:
Decimal number per field representation:
hex representation: 0x21280007
8 9 8 7
001000 01001 01000 0000000000000111hex
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M I P S Reference Data: CORE INSTRUCTION SET
NAME MNE-MON-IC
FOR-MAT
OPERATION (in Verilog)
OPCODE/ FUNCT (hex)
Add add R R[rd] = R[rs] + R[rt] (1)
0 / 20hex
Add Immediate
addi I R[rt] = R[rs] + SignExtImm (1)(2)
8hex
Branch On Equal
beq I if(R[rs]==R[rt]) PC=PC+4+ BranchAddr (4)
4hex
(1) May cause overflow exception(2) SignExtImm = { 16{immediate[15]}, immediate }(3) ZeroExtImm = { 16{1b’0}, immediate }(4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0}
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addi $8,$9,7
Executing the addi instruction
$8
$9 0x00000023Suppose
Immediate = 0x0007 (16 bits; 4 hex digits)
SignExtImm = 0x00000007 (32 bits; 8 hex digits)
00000023+00000007 0000002A
This will be more interesting when we get to negative numbers.
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Exercise
Which instruction has same representation as 35ten?A. add $0, $0, $0
B. subu $s0,$s0,$s0
C. lw $0, 0($0)
D. addi $0, $0, 35
E. subu $0, $0, $0
F. Trick question! Instructions are not numbers.
• Use Green Card to Answer
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Exercise Which instruction has same representation as 35ten?
A. add $0, $0, $0B. subu $s0,$s0,$s0C. lw $0, 0($0)D. addi $0, $0, 35E. subu $0, $0, $0F. Trick question! Instructions are not numbers.
Registers numbers and names: 0: $0, 8: $t0, 9:$t1, …,16: $s0, 17: $s1, …,
Opcodes and function fieldsadd: opcode = 0, function field = 32subu: opcode = 0, function field = 35addi: opcode = 8lw: opcode = 35
35 0 0 0
0 3200 0 0
8 0 0 35
16 3500 16 16
0 3500 0 0
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Logic Instructions
• Bit-wise logic operations• <op> <rdestination> <rsource1> <rsource2>
• Examples– and $t0, $s0, $s2 # $t0 = $s0 ^ $s2– or $s0, $t0, $t1 # $s0 = $t0 | $t1– nor $s0, $t0, $t1 # $s0 = ~($t0 | $t1)– xor $s0, $t0, $t1 # $s0 = $t0 ^ $t1
Name Fields Comments
R-format op rs rt rd shamt funct Logic instruction format
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Logic Instructions: Example
.text addi $t0,$0,0x32 addi $t1,$0,0x777 and $t2,$t1,$t0
$t0
$t1
$t2
Answer in class; also, replace and by or
Next: andi and ori
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Andi and Oriandi I R[rt] & ZeroExtImm (3)
lui I R[rt] = {immediate,16’b0}
(3) ZeroExtImm = {16{1’b0},immediate}
In Verilog: 4'b1001 // a 4-bit binary number16'h704f // a 16-bit hex number1b‘0 // a 1-bit binary number
.text lui $t1,0x7F40 addi $t2,$t1,0x777 andi $t3,$t2,0x5555
In class
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Long Immediates (review)
• Sometimes we need a long immediate, e.g., 32 bits
• MIPS requires that we use two instructions– lui $t0, 0xaa55
• Then we get lower-order 16 bits– ori $t0, $t0, 0xcc33
1010101001010101 1100110000110011$t0
1010101001010101 0000000000000000$t0
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Loading a memory address
• .data places values in memory starting at 0x10010000. So, 32 bits are needed to specify a memory address.
• Format I has a 16 bit field and Format J has a 26 bit field…neither is long enough.
• la $t0,0x1001008 is a pseudo instruction – not implemented in the hardware
• lui $1,4097 la $t0,0x10010008• ori $8,$1,8 • lw $t1,0($t0)
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A program
• Get sample1.asm from the schedule• Load it into the simulator• Figure out the memory contents, labels• Trace through the code
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.data # sample1.asma: .word 3,4c: .word 5,6 .text la $t0,c # address of c la $t1,k # address of k lw $s0,0($t0) # load c[0] lw $s1,4($t1) # load k[1] slt $s3,$s0,$s1 # if c[0] < k[1], $s3 = 1, else $s3 = 0 beq $s3,$0,notless # if c[0] < k[1] swap their values sw $s0,4($t1) sw $s1,0($t0)notless: .datak: .word 0xf,0x11,0x12
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