1 finite state machines (fsms) today: first hour: fsm concept –section 8.1 of katz’s textbook...
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Finite State Machines Finite State Machines (FSMs)(FSMs)
Today:
• First Hour: FSM Concept– Section 8.1 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Design Example w/ FSM• Section 8.2 of Katz’s Textbook
– In-class Activity #2
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Counters vs FSMsCounters vs FSMs
• Counters: Simple sequential circuits
State = Output
No inputs
Simple single-path sequencing through the states
• Generalizes to Finite State Machines:
Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" or “control” logic
A Precursor of Finite State MachinesA Precursor of Finite State Machines
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Recap: Synchronous FSMsRecap: Synchronous FSMs
• Described by State Diagrams, much the same way that combinational logic circuits are described by Boolean Algebra.
Current State
[output]
New State
[output]
Current Input(s)
Change of state happens only on the clocking event
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Each circle corresponds
to a state
Each circle corresponds
to a state
Recap:Recap: 3-bit Binary Up-Counter3-bit Binary Up-Counter
The label inside each circle
describes the state
The label inside each circle
describes the state Arrows
represent state
transitions
Arrows represent
state transitions
No labels on arrows, since the counter has no inputsNo labels on arrows, since the counter has no inputs
000 001 010
110 101 100
111 011
000 001 010010
110 101 100
111 011
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Example: Odd Parity CheckerExample: Odd Parity CheckerAsserts output whenever input bit stream (seen so far) has
odd # of 1's
Even [0]
Odd [1]
Reset
0
0
1 1
StateDiagram
StateDiagram
Present State Even Even Odd Odd
Input 0 1 0 1
Next State Even Odd Odd Even
Output 0 0 1 1
Symbolic State Transition TableSymbolic State Transition Table
Output 0 0 1 1
Next State 0 1 1 0
Input 0 1 0 1
Present State 0 0 1 1
Encoded State Transition TableEncoded State Transition Table
Observe that the output in this case depends only
upon the present state, and not upon the input.
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Design with Flip-flopsDesign with Flip-flops
Q Q+ T0 0 00 1 11 0 11 1 0
T F/F: Excitation Table
D F/F inputs are identical to the nextstate outputs in the state transition tableD F/F inputs are identical to the nextstate outputs in the state transition table
Q Q+ D0 0 00 1 11 0 01 1 1
D F/F: Excitation Table
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Odd Parity Checker OperationOdd Parity Checker OperationExcitation/Output FunctionsExcitation/Output Functions
D = PS Input; Output = PS
D
R
Q
Q
Input
Clock PS/Output
\Reset
D
D FF ImplementationD FF Implementation
T
R
Q
Q
Input
Clock
Output
\Reset
T FF ImplementationT FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clock
Output
Input 1 0 0 1 1 0 1 0 1 1 1 0
1 1 0 1 0 0 1 1 0 1 1 1
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WhenWhen are inputs sampled, next states computed, outputs asserted? WhenWhen are inputs sampled, next states computed, outputs asserted?
State TimeState Time: Time between clocking events
• Clocking eventClocking event causes state/outputs to transition, based on inputs
• For set-up/hold time set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delaypropagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediatelyNOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking eventSynchronous signals take effect at the next clocking event
E.g., 3-state enable: effective immediatelyE.g., 3-state enable: effective immediately sync. counter clear: effective at next clock eventsync. counter clear: effective at next clock event
TimingTiming
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Timing ExampleTiming Example
On rising edge: inputs sampled, outputs & next state computed
After propagation delay: outputs and next state are stable
Immediate Outputs affect datapath immediately could cause inputs from datapath to
change
Delayed Outputs take effect on next clock edge propagation delays must exceed
hold times
Positive Edge Triggered Synchronous System Positive Edge Triggered Synchronous System
Outputs
State Time
Clock
Inputs
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Communicating State MachinesCommunicating State Machines
Machines advance in lock stepMachines advance in lock stepInitial inputs/outputs: X = 0, Y = 0Machines advance in lock stepMachines advance in lock stepInitial inputs/outputs: X = 0, Y = 0
One machine's output is another machine's inputOne machine's output is another machine's input
CLK
FSM 1 X FSM 2
Y
A A B
C D D
FSM 1 FSM 2
X
Y
A [1]
B [0]
Y=0
Y=1
Y=0,1
Y=0
C [0]
D [1]
X=0
X=1
X=0
X=0
X=1Could be used to model:
bus protocols, handshaking,2-way communications, etc.
[0], [1]
outputs
[0], [1]
outputs
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Do Activity #1 NowDo Activity #1 Now
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Basic Design ApproachBasic Design Approach
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
Six Step ProcessSix Step Process
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Vending Machine ConceptVending Machine Concept
deliver package of gum after 15 cents is deposited
single coin slot for dimes, nickels
no change
General Machine ConceptGeneral Machine Concept
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Vending Machine FSM - 1Vending Machine FSM - 1
Block Diagram
Vending Machine
FSM
N
D
Reset
Clk
OpenCoin
SensorGum
Release Mechanism
INPUTS OUTPUTS
Step 1. Understand the problemStep 1. Understand the problemStep 1. Understand the problemStep 1. Understand the problem
Draw a picture!Draw a picture!
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Vending Machine FSM - 2Vending Machine FSM - 2
Tabulate typical input sequencesTabulate typical input sequences
three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime
Draw state diagramDraw state diagram
Inputs: N, D, reset
Output: open
Step 2. Map into more suitable abstract representationStep 2. Map into more suitable abstract representationStep 2. Map into more suitable abstract representationStep 2. Map into more suitable abstract representation
Reset
N
N
N
D
D
N D
[open]
[open] [open] [open]
S0
S1 S2
S3 S4 S5 S6
S8
[open]
S7
D
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Vending Machine FSM - 3Vending Machine FSM - 3Step 3: State MinimizationStep 3: State MinimizationStep 3: State MinimizationStep 3: State Minimization
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
reuse statesreuse stateswhenever possiblewhenever possible
reuse statesreuse stateswhenever possiblewhenever possible
Symbolic State TableSymbolic State Table
Present State
0¢
5¢
10¢
15¢
D
0 0 1 1 0 0 1 1 0 0 1 1 X
N
0 1 0 1 0 1 0 1 0 1 0 1 X
Inputs Next State
0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X
10¢ 15¢ 15¢ X
15¢
Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1
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Vending Machine FSM - 4Vending Machine FSM - 4Step 4: State EncodingStep 4: State EncodingStep 4: State EncodingStep 4: State Encoding
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
How many flip-flops are needed?
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Vending Machine FSM - 5aVending Machine FSM - 5aStep 5. Choose F/Fs for implementationStep 5. Choose F/Fs for implementationStep 5. Choose F/Fs for implementationStep 5. Choose F/Fs for implementation
D F/F easiest to useD F/F easiest to use
K-map for OpenK-map for D0 K-map for D1
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
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Vending Machine FSM - 5bVending Machine FSM - 5bStep 5. Choose FF for Implementation (continued)Step 5. Choose FF for Implementation (continued)Step 5. Choose FF for Implementation (continued)Step 5. Choose FF for Implementation (continued)
J 1
0 0 1 X 0 1 1 X X X X X X X X X
J-K F/F
Remapped encoded state transition tableRemapped encoded state transition table
Next State Q0+
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs K 1
X X X X X X X X 0 0 0 X 0 0 0 X
K 0
X X X X 0 1 0 X X X X X 0 0 0 X
J 0
0 1 0 X X X X X 0 1 1 X X X X X
Q1+
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Vending Machine FSM - 6aVending Machine FSM - 6a
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q08 Gates
CLK
OPEN
CLK
Q 0
D
R
Q
Q
D
R
Q
Q
\ Q 1
\reset
\reset
\ Q 0
\ Q 0
Q 0
Q 0
Q 1
Q 1
Q 1
Q 1
D
D
N
N
N
\ N
D 1
D 0
Step 6. Implementation: D F/FsStep 6. Implementation: D F/FsStep 6. Implementation: D F/FsStep 6. Implementation: D F/Fs
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Vending Machine FSM - 6bVending Machine FSM - 6bStep 6. Implementation: J-K F/FsStep 6. Implementation: J-K F/FsStep 6. Implementation: J-K F/FsStep 6. Implementation: J-K F/Fs
K-map for K1K-map for J1
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
K-map for K0K-map for J0
Q1 Q0D N
Q1
Q0
D
N
Q1 Q0D N
Q1
Q0
D
N
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
7 Gates
OPEN Q 1
\ Q 0
N
Q 0 J
K R
Q
Q
J
K R
Q
Q
Q 0
\ Q 1
\ Q 1
\ Q 0
Q 1
\reset
D
D
N
N
CLK
CLK
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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.
RETAIN THE LAST PAGE(S) (#3 onwards)!!
For Next Class:• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:– Sec 8.4 of Katz
• This reading is necessary for getting points in the Studio Activity!
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