1 scalable pattern matching for high speed networks authors: christopher r.clark and david e....
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Scalable Pattern Matching for High Speed Networks
Authors: Christopher R.Clark and David E. SchemmelPublisher: Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM) Present: Kia-Tso ChangDate: November 1 2007
Three designed method on FPGA
1. brute-force, 2. deterministic finite automata (DFA) 3. non-deterministic finite automata
(NFA).
Distributed comparators and Character Decoder
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Pattern-matching module using multi-character decoder
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Four-character parallel NFAcircuit for the pattern “abcde”
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Upper bound of per matcher
Upper bound of per matcher
Each FPGA logic element (LE) can implement up to a four-input logic gate and a flip-flop,
Upper bound of per matcher
Upper bound of per matcher
Experiment result
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Experiment result
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Throughput and capacity trade-off summary
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Throughput and capacity trade-off summary
Performance comparison with previous work
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