10/27/05elec 5970-001/6970-001 lecture 161 elec 5970-001/6970-001(fall 2005) special topics in...

10/27/05 ELEC 5970-001/6970-001 Lecture 16 1

ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits

Adiabatic and Charge Recovery Logic

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

10/27/05 ELEC 5970-001/6970-001 Lecture 16 2

Examples of Power Saving and Energy Recovery

• Power saving by power transmission at high voltage:– 1000W transmitted at 100V, current I = 10A– If resistance of transmission circuit is 1Ω, then power

loss = I2R = 100W– Transmit at 1000V, current I = 1A, transmission loss =

1W

• Energy recovery from automobile brakes:– Normal brake converts mechanical energy into heat– Instead, the energy can be stored in a flywheel, or– Converted to electricity to charge a battery

10/27/05 ELEC 5970-001/6970-001 Lecture 16 3

Reexamine CMOS Gate

i = Ve-t/RpC/Rp

i2Rp

VV2/Rp

C

Time, t

Po

we

r

Most energy dissipated here

V2e-2t/RpC/Rp

0

Energy = Area = CV2/2

v(t)

V v(t)

v(t

)

3RpC

10/27/05 ELEC 5970-001/6970-001 Lecture 16 4

Charging with Constant Current

i = K i2Rp

V(t)

C

Po

we

r0

v(t) = Kt/C

Time to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/KCurrent, i = K = CV/T

Ou

tpu

t vo

ltag

e, v

(t)

0

V

Time, t t=CV/K

Kt/C

Power = i2Rp = C2V2Rp/T2

Energy = Power × T = (RpC/T) CV2

C2V2Rp/T2

10/27/05 ELEC 5970-001/6970-001 Lecture 16 5

Or, Charge in Steps

i = Ve-t/RpC/2Rp

i2Rp

0→V/2→V

V2/4Rp

C

Time, t

Po

we

r

V2e-2t/RpC/4Rp

0Energy = Area = CV2/8

v(t)

V v(t)

v(t

)

V/2

Total energy = CV2/8 + CV2/8 = CV2/4

3RpC 6RpC

10/27/05 ELEC 5970-001/6970-001 Lecture 16 6

Energy Dissipation of a Step

TE = ∫ V2e-2t/RpC/(N2Rp) dt 0

= [CV2/(2N2)] (1 – e-2T/RpC)

≈ CV2/(2N2) for large T ≥ 3RpC

Voltage step = V/N

10/27/05 ELEC 5970-001/6970-001 Lecture 16 7

Charge in N Steps

Supply voltage 0 → V/N → 2V/N → 3V/N → . . . NV/N

Current, i(t) = Ve-t/RpC/NRp

Power, i2(t)Rp = V2e-2t/RpC/N2Rp

Energy = N CV2/2N2 = CV2/2N → 0 for N → ∞

Delay = N × 3RpC → ∞ for N → ∞

10/27/05 ELEC 5970-001/6970-001 Lecture 16 8

References

• C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1-17.

• W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994.

10/27/05 ELEC 5970-001/6970-001 Lecture 16 9

Dynamic CMOS Inverter

V

C

v(t)

CK

vin

CK

vin

v(t)

P E P E P E

10/27/05 ELEC 5970-001/6970-001 Lecture 16 10

Adiabatic Dynamic CMOS Inverter

C

v(t)

CK

vin

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

CK

vin

v(t)

V

0

V-Vf

0

Vf+

10/27/05 ELEC 5970-001/6970-001 Lecture 16 11

Cascaded Adiabatic Inverters

CK1 CK2 CK1’ CK2’

vin

CK1

CK2

CK1’

CK2’

precharge

input

evaluatehold

10/27/05 ELEC 5970-001/6970-001 Lecture 16 12

Complex ADL Gate

CK

B

A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995.

AC

AB + C

Vf < Vth

10/27/05 ELEC 5970-001/6970-001 Lecture 16 13

Quasi-Adiabatic Logic• Two sets of diodes:

One controls the charging path (D1) while the other (D2) controls the discharging path

• Supply lines have EVALUATE phase ( swings up) and HOLD phase ( swings low)

D1

D2

10/27/05 ELEC 5970-001/6970-001 Lecture 16 14

Possible Cases:• The circuit output node X is LOW

and the pMOS tree is turned ON: X

follows as it swings to HIGH (EVALUATE phase)

• The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase)

• The circuit node X is HIGH and the

nMOS tree is ON. X follows down to LOW, i.e. energy is recovered (RESTORE phase)

Quasi-Adiabatic Logic Design

10/27/05 ELEC 5970-001/6970-001 Lecture 16 15

A Case Study

K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis,Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.

10/27/05 ELEC 5970-001/6970-001 Lecture 16 16

Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Specifications

• Operating voltage: 2.5 V

• Operating temperature: 25oC

• Operating frequency: 10 MHz to 100 MHz

• Leakage current: 0.5 fAmps

• Load capacitance: 6X10-18 F (15% activity)

• Transistor Count

10/27/05 ELEC 5970-001/6970-001 Lecture 16 17

Technology Distribution• Microprocessor has a mix of static CMOS

and Quasi-adiabatic components

ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit

ALUALU• Adder-subtractor unit• Barrel shifter unit• Booth-multiplier unit

Control UnitsControl Units• ARM controller unit• Bus control unit

Pipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unit

Control UnitsControl Units• ARM controller unit• Bus control unit

Pipeline UnitsPipeline Units• ID unit• IF unit• WB unit• MEM unit

Quasi-Adiabatic Static CMOS

10/27/05 ELEC 5970-001/6970-001 Lecture 16 18

Power AnalysisDatapath

Component

Power Consumption (mW)

Frequency 25 MHz

Power Consumption (mW)

Frequency 100 MHz

Quasi-adiabatic

* Static CMOS

Power Saved

Quasi-adiabatic

* Static CMOS

Power Saved

32-bit Adder Subtracter

1.01 1.55 44% 1.29 1.62 20%

32-bit Barrel Shifter

0.9 1.681 46% 1.368 1.8 24%

32-bit Booth Multiplier

3.4 5.8 40% 5.15 6.2 17%

Power Consumption (mW)

Frequency 25 MHz

Quasi-adiabatic

* Static CMOS

Power Saved

60 mW 85 mW 40%

10/27/05 ELEC 5970-001/6970-001 Lecture 16 19

Power Analysis (Cont’d.)

10/27/05 ELEC 5970-001/6970-001 Lecture 16 20

Area AnalysisDatapath

Component

Area (mm2)

Quasi-adiabatic

* Static CMOS Area Increase

32-bit Adder Subtracter 0.05 0.03 66%

32-bit Barrel Shifter 0.25 0.11 120%

32-bit Booth Multiplier 1.2 0.5 140%

Chip Area (mm2)

Quasi-adiabatic

* Static CMOS

Area Increase

1.01 1.55 44%

10/27/05 ELEC 5970-001/6970-001 Lecture 16 21

Summary• In principle, two types of adiabatic logic designs

have been proposed:– Fully-adiabatic

• Adiabatic charging• Charge recovery: charge from a discharging capacitor is

used to charge the capacitance from the next stage.• W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and

E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994.

– Quasi-adiabatic• Adiabatic charging and discharging• Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery

Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001.