1/27/06eecs150 lab lecture #21 designing with verilog eecs150 spring 2006 – lab lecture #2 brian...

1/27/06 EECS150 Lab Lecture #2 1

Designing with Verilog

EECS150 Spring 2006 – Lab Lecture #2

Brian GawaltGreg Gibeling

1/27/06 EECS150 Lab Lecture #2 2

Today Top-Down and Bottom-Up Partitioning & Interfaces Behavioral vs. Structural Verilog Administrative Info Blocking and Non-Blocking Verilog and Hardware Lab #2 Primitives

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Top-Down vs. Bottom-Up (1) Top-Down Design

Start by defining the project Then break it down Starts here:

Lab3Top Out

Select

In

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Top-Down vs. Bottom-Up (2) Top-Down Design

Ends here:

Out

Select

In

Lab3Top

Accumulator

Peak Detector

Mux

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Top-Down vs. Bottom-Up (3) Bottom-Up Testing Faster, Easier and

Cheaper Test each little

component thoroughly

Allows you to easily replicate working components

Peak Detector OutIn

PeakTestbench

Accumulator OutIn

AccTestbench

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Partitioning & Interfaces (1) Partitioning

Break the large module up Decide what sub-modules make sense

Partitioning is for your benefit It needs to make sense to you

Each module should be: A reasonable size Independently testable

Successful partitioning allows easier collaboration on a large project

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Partitioning & Interfaces (2)

Interfaces A concise definition of signals and

timing Timing is vital, do NOT omit it

Must be clean Don’t send useless signals across Bad partitioning might hinder this

An interface is a contract Lets other people use/reuse your module

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Behavioral vs. Structural (1)

Rule of thumb: Behavioral doesn’t have sub-

components Structural has sub-components:

Instantiated Modules Instantiated Gates Instantiated Primitives

Most modules are mixed Obviously this is the most flexible

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Behavioral vs. Structural (2)

Structural

StructuralStructuralBehavioral

Behavioral

Behavioral Primitive

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Behavioral vs. Structural (3)

Lab3TopStructural Behavioral

AccumulatorBehavioral

PeakDetectorStructural

Reg8Structural

Comp8 Structural

Comp1Structural

FDCEPrimitive

Gate Primitives

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Administrative Info

Lab Grading Get it in by the opening of the next

lab Partial credit will be given for

incomplete labs Please stick to one lab session

Card Key Access for All is coming soon!

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Blocking vs. Non-Blocking (1)

always @ (a) beginb = a;c = b;

end

always @ (posedge Clock) beginb <= a;c <= b;

end

C = B = A

B = Old AC = Old B

Verilog Fragment Result

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Blocking vs. Non-Blocking (2)

Use Non-Blocking for FlipFlop Inference posedge/negedge require Non-Blocking Else simulation and synthesis wont match

Use #1 to show causality

always @ (posedge Clock) beginb <= #1 a;c <= #1 b;

end

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Blocking vs. Non-Blocking (3)

If you use blocking for FlipFlops:

YOU WILL NOT GET WHAT YOU WANT!always @ (posedge Clock) begin

b = a; // b will go awayc = b; // c will be a FlipFlop

end// b isn’t needed at all

always @ (posedge Clock) beginc = b; // c will be a FlipFlopb = a; // b will be a FlipFlop

end

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Blocking vs. Non-Blocking (4)

file xyz.v: module XYZ(A, B, Clock);

input B, Clock;output A;reg A;always @ (posedge Clock)

A = B;endmodule

file abc.v: module ABC(B, C, Clock);

input C, Clock; output B; reg B; always @ (posedge Clock)

B = C; endmodule

Race Conditions

THIS IS WRONG

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Blocking vs. Non-Blocking (5)

file xyz.v: module XYZ(A, B, Clock);

input B, Clock;output A;reg A;always @ (posedge Clock)

A <= B;endmodule

file abc.v: module ABC(B, C, Clock);

input C, Clock; output B; reg B; always @ (posedge Clock)

B <= C; endmodule

Race Conditions

THIS IS CORRECT

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Verilog and Hardware (1)

+ Sum

A

B

assign Sum = A + B;

reg [1:0] Sum;always @ (A or B) begin

Sum = A + B;end

0

Sum

AB

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Verilog and Hardware (2)

assign Out = Select ? A : B;

reg [1:0] Out;always @ (Select or A or B) begin

if (Select) Out = A;else Out = B;

end

Mux

0

1

S

Out

B

A

Select

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Verilog and Hardware (3)

assign Out = Sub ? (A-B) : (A+B);

reg [1:0] Out;always @ (Sub or A or B) begin

if (Sub) Out = A - B;else Out = A + B;

end

Mux

0

1

S

+

B

A

Sub

Out

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Verilog and Hardware (4)

reg [1:0] Out;always @ (posedge Clock) begin

if (Reset) Out <= 2’b00;else Out <= In;

end

Q

QSET

CLR

DIn

Reset

Out

Clock

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Lab #2 (1)

Lab2Top Accumulator

Stores sum of all inputs Written in behavioral verilog Same function as Lab1Circuit

Peak Detector Stores largest of all inputs Written in structural verilog

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Lab #2 (2)

Out

Select

In

Lab2Top

Accumulator

Peak Detector

Mux

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Lab #2 (3)

Register+

Accumulator

In

Enable

Clock

Out

Reset

88

8

8

Accumulator.v

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Lab #2 (4)

PeakDetector.v

Register

PeakDetector

In

Enable

Clock

Out

Reset

≥8

8

8

8

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Primitives (1)

wire SIntermediate, SFinal, CPropagrate, CGenerate;

xor xor1( SIntermediate, In, Out);and and1( CGenerate, In, Out);xor xor2( SFinal, SIntermediate, CIn);and and2( CPropagate, In, CIn);or or1( COut, CGenerate,

CPropagate);

FDCE FF( .Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal));

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Primitives (2)

wire SIntermediate, SFinal, CPropagrate, CGenerate;

xor xor1( SIntermediate, In, Out);and and1( CGenerate, In, Out);xor xor2( SFinal, SIntermediate,

CIn);and and2( CPropagate, In, CIn);or or1( COut, CGenerate,

CPropagate);

FDCE FF( .Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal));

1/27/06 EECS150 Lab Lecture #2 27

Primitives (3)

wire SIntermediate, SFinal, CPropagrate, CGenerate;

xor xor1( SIntermediate, In, Out);and and1( CGenerate, In, Out);xor xor2( SFinal, SIntermediate, CIn);and and2( CPropagate, In, CIn);or or1( COut, CGenerate,

CPropagate);

FDCE FF( .Q( Out),.C( Clock),.CE( Enable),.CLR( Reset),.D( SFinal));