15 thomsen isscc 2000
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8/13/2019 15 Thomsen ISSCC 2000
http://slidepdf.com/reader/full/15-thomsen-isscc-2000 1/2 2000 IEEE International Solid-State Circuits Conference 07803-5853-8/00 ©2000 IEEE
WA 20.1 A DC Measurement IC with 130nVpp
Noise in 10Hz
Axel Thomsen, Edwin de Angel, Sherry Xiaohong Wu, Aryesh Amar1, Lei Wang2,Wai Lee
Crystal Industrial and Communications Division, Cirrus Logic, Austin, TX1Crystal Industrial and Communications Division, Cirrus Logic, Nashua,NH2Texas A&M University, College Station, TX
A CMOS DC measurement IC surpasses the noise performance of
prior-art integrated systems. The instrumentation amplifier sur-
passes commercially-available stand-alone inamp solutions in
0.1 to 10Hz noise performance. It is targeted for bridge transducer
measurements where signal levels are typically on the order of a fewmV. Low noise is crucial at these signal levels. In prior-art, inte-
grated DC measurement systems the wideband noise of the instru-
mentation amplifier is sampled directly without anti-aliasing and
thus noise performance is sacrificed for a simpler interface between
amplifier and modulator [1,2]. Figure 20.1.1 shows a block diagramof the IC consisting of a programmable gain instrumentation ampli-
fier followed by a 4th-order ∆Σ modulator, a programmable decima-
tion filter, and a 3-wire serial interface. The inamp uses the
multipath feedforward architecture presented in Reference [3] that
offers flexibility in low frequency applications because it separates
the low frequency signal path from the high frequency path de-signed for stability. The architecture is modified to reduce the offset
introduced by the second stage of the amplifier. It is also modified
according to the reduced bandwidth requirements in the DC mea-
surement application. Special attention is given the chopper stabi-
lization.
The opamp architecture used in the inamp is shown in Figure 20.1.2.
Multipath feedforward compensation allows the cascading of sev-
eral integrators to achieve high gain. It achieves stability by
bypassing slower integrator stages at higher frequencies by provid-ing a unity gain path around each integrator. Many arrangements
of integrator stages are possible and after gain and stability require-
ments are met, more subtle issues determine the optimal arrange-
ment of stages. The first stage I1 is chopper-stabilized and must be
a low bandwidth integrator to allow filtering of chop artifacts. Butsince its input transconductance sets the noise performance of the
amplifier, it must be large to meet the noise target. To avoid an
external capacitor and noise pickup problems that may arise, in
Reference [3] this stage is followed by an attenuator that reduces the
effective bandwidth of the stage by 1/128x from the 2.56MHzimplemented as gm
in /C
load to 20kHz. But this arrangement leads to
a more significant effect of the second-stage offset. A 5mV offset in
the second stage must be overcome by –640mV of offset at the output
of the first stage. Even with 80dB of gain in the first stage, this leads
to an unacceptable 64µ V input offset. This arrangement uses a 1/64xattenuator and places a low-bandwidth second integrator I2 before
the attenuator. In this arrangement the integrator provides the
drive to cancel the offset of the subsequent stages reflected through
the attenuator. The first stage I1 sees only the offset of the new
integrator I2.
The implementation of the chopper is as follows: Input chop switches
are regular voltage switches (Figure 20.1.3). The output chopper is
implemented as current steering, rather than as voltage switching,
to minimize artifacts at the chop frequency. The voltage swings onthe switches p1, p2, n1, n2 are reduced to an effective gate-v
on
voltage. The phasing of clocks 1 and 2 is simple non-overlap. Clock
phases n1 and p1 start after and end before 1, n2 and p2 maintain
similar relations to 2. The phases nx and px direct the current to the
supply during the crossover switching at the input. Chop frequencyis 38.4kHz to maintain input currents below 1nA. The 0.1-10Hz
noise results show the effectiveness of the chop circuitry in sup-
pressing low-frequency noise (Figure 20.1.4). Noise below 10Hz is
kept to within 130nV pp
with 20nV measured RMS noise. The offsetdrift is <70nV/ °C.
To maintain gain accuracy of the DC measurement system in the
presence of an anti-alias filter, a rough-charging scheme is required
(Figure 20.1.5). Otherwise the switched-capacitor current flowing through the anti-alias resistor creates unacceptable temperature
coefficients. A signal-dependent rough-charge buffer scheme mini-
mizes power consumption and maximizes voltage swing into the
ADC. This buffer pre-charges the 16pF of ADC input capacitance so
that the path through the anti-alias resistor has to provide for onlythe remaining charge error. The implementation of the rough-buffer
takes advantage of the asymmetric behavior of a two-stage class-A
opamp in response to a step on the output. A comparator is used to
detect the polarity of the input signal during a preceding clock.
Assuming vamp+ is greater than vamp-, all switches labeled p areclosed. A switched-capacitor connected to vadcR+ has to be pulled up
to vamp+ by the rough-buffer. VadcR+ is pulled down initially by
this switched-capacitor, but this downward glitch couples through
to node B. With the selected active-pMOS output stage, the pull up
is accelerated. Similarly, the active-nMOS output stage efficientlypulls down. The rough-buffer input stages are of a chopper stabi-
lized, rail-to-rail folded cascode design. The resulting measured gain
drift is 15ppm/ oC.
The switched-capacitorΣ∆ modulator is chopper stabilized to achieve70nV/ √Hz in the band of interest. It is dynamically biased as
described in Reference [4] to minimize power consumption while
providing a wide instantaneous dynamic range. The presence of
switched-capacitor circuits and clocked currents due to dynamic
biasing do not adversely affect the noise performance of the inamp.Figure 20.1.6 shows a spectrum with a full-scale 20Hz input signal
at the 64x gain and 240Hz output word rate setting. The noise rolls
off slightly with frequency due to the droop in the Sinc3 decimation
filter response. No appreciable 1/f noise is detectable down to
0.01Hz. The noise density is 6.2nV/ √Hz. The THD is 101dB. TheSNR (not counting the harmonic components) is 112dB. At the 64x
gain settling, the full-scale input signal is only 28mVrms. Since the
inamp is programmable from 2x to 64x gain, this represents a total
of 142dB dynamic range over the 120Hz bandwidth.
The digital filter uses as its fastest clock the modulator output bit-
rate. CIC filters reduce hardware complexity and thus noise[5]. All
analog signals are fully-differential to avoid pickup of digital noise.
The 16mm2 chip micrograph is shown in Figure 20.1.7. Power
consumption is 41mW from ±2.5V analog and +5V digital supplies.
References:
[1] Mc Cartney, D. et al, “A Low-noise, Low-drift Transducer ADC”, JSSC, July1997, pp. 959-967.[2] Kerth, D. A. D. S. Piasecki, “An Oversampling Converter For Strain GaugeTransducers”, JSSC, Dec. 1992, pp. 1689-1696.[3] Thomsen, A. “A 5 Stage Chopper Stabilized Instrumentation Amplifierusing Feedforward Compensation”, Proc. VLSI Circ Symp, Honolulu, June1998, pp. 220-223.
[4] Kasha, D. B. et al, “A 16mW, 120dB Linear Switched Capacitor Σ∆Modulator with Dynamic Biasing”, JSSC, July 1997, pp. 921-926.[5] Hogenauer, E. B. “An Economical Class of Digital Filters for Decimationand Interpolation”, Trans. Acoustics Speech Signal Proc., April 1981, pp. 155-162.
8/13/2019 15 Thomsen ISSCC 2000
http://slidepdf.com/reader/full/15-thomsen-isscc-2000 2/2• 2000 IEEE International Solid-State Circuits Conference 07803-5853-8/00 ©2000 IEE
Figure 20.1.7: Chip micrograph.Figure 20.1.6: Full-scale input spectrum:
vertical axis, dB; horizontal axis, Hz.
Figure 20.1.5: ADC rough charge buffer implementation.
Figure 20.1.4: Low-frequency (0-10Hz) noise.
Figure 20.1.3: Implementation of chopper using current steering.
Figure 20.1.2: Opamp architecture.
Figure 20.1.1: System overview.
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