2/16/09 lab 3 jorge crichigno. 2/16/09 half-adder

2/16/09

Lab 3

Jorge Crichigno

2/16/09

Half-adder

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Half-adder Testbench

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Waveform for half-adder simulation tbstimulus

10 ns

testbench

ha

x_signal

y_signal

x

ysc

s_signal

c_signal

0

0

0

0

0

1

1

0

1

0

0

0

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Full-adder

2/16/09

Full-adder Testbench

2/16/09

Waveform for full-adder simulation tb

testbench

fa

x_signal

y_signal

x

ysc

s_signal

c_signal

z_signal z

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• Process. Type of processes. Process with sensitivity list. Process with wait statement. Example.

• Sequential Signal Assignment Statement. Syntax. Examples. Pitfall. Intermediate value. Conceptual implementation

• Variables. Syntax. Intermediate value. Example. Conceptual implementation

• Case statement. Syntax. Example. Multiplexor. Conceptual implementation.

Lab 3 - Sequential Statements

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Process

• Contains a set of sequential statements to be executed sequentially• The whole process is a concurrent statement

• Can be interpreted as a circuit part enclosed inside of a black box

• Two types: with sensitive list and with wait statement

Lab 3 - Sequential Statements

2/16/09

A process with a sensitivity list

• Syntax

process (sensitivity_list)

declarations;

begin

sequential statement;

sequential statement;

. . .

end process;

Lab 3 - Sequential Statements

2/16/09

Lab 3 - Sequential StatementsProcess with sensitivity list. Interpretation: “black box, indivisible circuit part”.

Sensitivity list

The execution of the process is initiated whenever an event occurs on any of the signals in the sensitivity listFor practical purposes, you can regards a process as a “big” concurrent signal assignment statement

Note:

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Waveform for Example 1

0

00

0

11

0

00

0

10

0

00

0

10Process not

activated on Bchange

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A Process With wait Statement• Process has no sensitivity list• Process continues the execution until a wait statement is reached and

then suspended• Forms of wait statement:

– wait on signals;– wait until boolean_expression;– wait for time_expression;

2/16/09

Sequential Signal Assignment StatementSignal_name <= value_expression;Syntax:

00

1

01

0

10

0

11

0

0

0

U

0

1U

1

0U

1

1U

undefined

CS1

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Sequential Signal Assignment Statement

If all assignments are within DELTA-delay, only the last assignment takes effect. You can think as the signals are not updated until the end of the process (i.e., it never assumes any “intermediate” value).

2/16/09

Variable Assignment StatementVariable_name := value_expression;Syntax:

Used inside processes. The assignment takes effect “immediately”.

Easy to understand, but not clear hardware mapping!Use signal always you can; rely on variables only for the characteristics that cannot be described by signals

Note:

0 tmp

A

B

C

Conceptual implementation

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Case Statement

Syntax: Example:

2/16/09

Introduction to Multiplexers

Example of case statement: Multiplexor

S Y

0 I 0

1 I 1

Truth Table

2/16/09

4-to-1 multiplexer – VHDL Implementation

EntityENTITY mux4x1 IS

PORT (

S : IN STD_LOGIC_VECTOR (1 downto

0);

D0 : IN STD_LOGIC;

D1 : IN STD_LOGIC;

D2 : IN STD_LOGIC;

D3 : IN STD_LOGIC;

Y : OUT STD_LOGIC

);

END mux4x1;

ARCHITECTURE multiplexor4x1 OF

mux4x1 IS

BEGIN

PROCESS(S, D0, D1, D2, D3)

BEGIN

CASE S IS

WHEN "00" => Y <= D0;

WHEN "01" => Y <= D1;

WHEN "10“ => Y <= D2;

WHEN OTHERS => Y <= D3;

END CASE;

END PROCESS;

END multiplexor4x1;

Architecture