55:035 computer architecture and organization lecture 4
Post on 21-Dec-2015
224 Views
Preview:
TRANSCRIPT
55:035Computer Architecture and Organization
Lecture 4
Outline HDL Overview Why not use “C”?
Concurrency Hardware datatypes / Signal resolution Connectivity / Hierarchy Hardware simulation
SystemVerilog Introduction Datapaths and Control Paths Moore and Mealy State Machines Examples State Encoding
255:035 Computer Architecture and Organization
HDL Overview Hardware Description Languages
Used to model digital systems Can model anything from a simple gate to a complete system Support design hierarchy Support Hardware Design Methodology
Can model “real” hardware (synthesizable) Can model behavior (e.g. for test) Most widely used are VHDL and VerilogHDL
Both are non-proprietary, IEEE standards
Behavioral and structural coding styles
355:035 Computer Architecture and Organization
55:035 Computer Architecture and Organization 4
Basic Design Methodology
SimulateRTL Model
Gate-levelModel
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
TimingModel Simulate
Requirements
Device Libraries
Why Not Use C or C++? HDLs need to support characteristics of “real”
hardware Concurrency Hardware datatypes / Signal resolution Connectivity / Hierarchy Circuit timing
HDLs must support hardware simulation Time Cycle-accurate or Event-driven (for simulation speed)
Note: C++ has been extended for hardware SystemC
55:035 Computer Architecture and Organization 5
Basic Comparison
Verilog Similar to C Popular in commercial,
on coasts of US Designs contained in
“module”s
VHDL Similar to Ada Popular in Military,
midwest US Designs contained in
“entity” “architecture” pairs
55:035 Computer Architecture and Organization 6
Concurrency HDLs must support concurrency
Real hardware has many circuits running at the same time!
Two basics problems Describing concurrent systems Executing (simulating) concurrent systems
55:035 Computer Architecture and Organization 7
Describing Concurrency Many ways to create concurrent circuits
initial/always (Verilog) and process (VHDL) blocks Continuous/concurrent assignment statements Component instantiation of other modules or
entity/architectures
These blocks/statements execute in parallel in every VHDL/Verilog design
55:035 Computer Architecture and Organization 8
Executing Concurrency Simulations are done on a host computer
executing instructions sequentially Solution is to use time-sharing
Each process or always or initial block gets the simulation engine, in turn, one at a time
Similar to time-sharing on a multi-tasking OS, with one major difference There is no limit on the amount of time a given
process gets the simulation engine Runs until process requests to give it up (e.g. “wait”)
55:035 Computer Architecture and Organization 9
Process Rules If the process has a sensitivity list, the process is
assumed to have an implicit “wait” statement as the last statement Execution will continue (later) at the first statement
A process with a sensitivity list must not contain an explicit wait statement
55:035 Computer Architecture and Organization 10
Sensitivity List
With Explicit ListXYZ_Lbl: process (S1, S2)
begin
S1 <= ‘1’;
S2 <= ‘0’ after 10 ns;
end process XYZ_Lbl;
Without Explicit ListXYZ_Lbl: process
begin
S1 <= ‘1’;
S2 <= ‘0’ after 10 ns;
wait on S1, S2;
end process XYZ_Lbl;
55:035 Computer Architecture and Organization 11
Incomplete Sensitivity Lists Logic simulators use
sensitivity lists to know when to execute a process
Perfectly happy not to execute proc2 when “c” changes
Not simulating a 3-input AND gate though!
What does the synthesizer create?
55:035 Computer Architecture and Organization 12
-- complete
proc1: process (a, b, c)
begin
x <= a and b and c;
end process;
-- incomplete
proc2: process (a, b)
begin
x <= a and b and c;
end process;
Datatypes Verilog has two groups of data types
Net Type – physical connection between structural elements
Value is determined from the value of its drivers, such as a continuous assignment or a gate output
wire/tri, wor/trior, wand/triand, trireg/tri1/tri0, supply0, supply1
Variable (Register) Type – represents an abstract data storage element
Assigned a value in an always or initial statement, value is saved from one assignment to the next
reg, integer, time, real, realtime
55:035 Computer Architecture and Organization 13
Datatypes VHDL categorizes objects in to four classes
Constant – an object whose value cannot be changed Signal – an object with a past history Variable – an object with a single current value File – an object used to represent a file in the host
environment
Each object belongs to a type Scalar (discrete and real) Composite (arrays and records) Access File
55:035 Computer Architecture and Organization 14
Hierarchy Non-trivial designs are developed in a
hierarchical form Complex blocks are composed of simpler blocks
55:035 Computer Architecture and Organization 15
VHDL Verilog
Entity and architecture Module
Function Function
Procedure Task
Package and package body Module
55:035 Computer Architecture and Organization 16
A concurrent language allows for: Multiple concurrent “elements” An event in one element to cause activity in another
An event is an output or state change at a given time Based on interconnection of the element’s ports
Logical concurrency — software True physical concurrency — e.g., “<=” in Verilog
Hardware Simulation
55:035 Computer Architecture and Organization 17
Discrete Time Simulation Models evaluated and state updated only at time
intervals — n Even if there is no change on an input Even if there is no state to be changed Need to execute at finest time granularity Might think of this as cycle accurate — things only happen
@(posedge clock)
You could do logic circuits this way, but either: Lots of gate detail lost — as with cycle accurate above (no
gates!) Lots of simulation where nothing happens — every gate is
executed whether an input changes or not.
55:035 Computer Architecture and Organization 18
Discrete Event (DE) Simulation Discrete Event Simulation…also known as Event-
driven Simulation Only execute models when inputs change Picks up simulation efficiency due to its selective
evaluation
Discrete Event Simulation Events — changes in state at discrete times. These cause
other events to occur Only execute something when an event has occurred at its
input Events are maintained in time order Time advances in discrete steps when all events for a
given time have been processed
55:035 Computer Architecture and Organization 19
Discrete Event (DE) Simulation Quick example
Gate A changes its output. Only then will B and C execute
Observations The elements in the diagram don’t need to be logic
gates DE simulation works because there is a sparseness
to gate execution — maybe only 12% of gates change at any one time.
The overhead of the event list then pays off
A
B
C
55:035 Computer Architecture and Organization 20
Test Benches Testing a design by simulation Use a test bench model
an architecture body that includes an instance of the design under test
applies sequences of test values to inputs monitors values on output signals
either using simulator or with a process that verifies correct operation
55:035 Computer Architecture and Organization 21
Simulation Execution of the processes in the elaborated model Discrete event simulation
time advances in discrete steps when signal values change—events
A processes is sensitive to events on input signals specified in wait statements resumes and schedules new values on output signals
schedules transactions event on a signal if new value different from old value
55:035 Computer Architecture and Organization 22
Simulation Algorithm Initialization phase
each signal is given its initial value simulation time set to 0 for each process
activate execute until a wait statement, then suspend
execution usually involves scheduling transactions on signals for later times
55:035 Computer Architecture and Organization 23
Simulation Algorithm Simulation cycle
Advance simulation time to time of next transaction For each transaction at this time
update signal value event if new value is different from old value
For each process sensitive to any of these events, or whose “wait for …” time-out has expired
resume execute until a wait statement, then suspend
Simulation finishes when there are no further scheduled transactions
55:035 Computer Architecture and Organization 24
Synthesis Translates register-transfer-level (RTL) design
into gate-level netlist Restrictions on coding style for RTL model Tool dependent
55:035 Computer Architecture and Organization 25
Basic VerilogHDL Concepts Interfaces Behavior Structure
A Gate Level Model A Verilog description of an SR latch
module nandLatch
(output q, qBar,
input set, reset);
nand #2
g1 (q, qBar, set),
g2 (qBar, q, reset);
endmodule
A module is defined
name of the module
The module has ports that are typed
primitive gates with names and interconnections
type and delay of primitive gates
2655:035 Computer Architecture and Organization
55:035 Computer Architecture and Organization 27
A Behavioral Model - FSM
X
Q2
Q1
Q2’
D1 Q1
D2 Q2
Z
clock
reset
reset
reset
55:035 Computer Architecture and Organization 28
Verilog Organization for FSM Two always blocks
One for the combinational logic — next state and output logic
One for the state register
55:035 Computer Architecture and Organization 29
module FSM (x, z, clk, reset);input clk, reset, x;output z;reg [1:2] q, d;reg z;
endmodule
Verilog Behavioral Specification
always @(x or q)begin d[1] = q[1] & x | q[2] & x; d[2] = q[1] & x | ~q[2] & x; z = q[1] & q[2];end
always @(posedge clk or negedge reset) if (~reset) q <= 0; else q <= d;
The sequential part (the D flip flop)
The sequential part (the D flip flop)
The combinational logic part
next state
output
The combinational logic part
next state
output
SystemVerilog
55:035 Computer Architecture and Organization 30
Verilog-95
55:035 Computer Architecture and Organization 31
VHDL Much Richer Than Verilog
55:035 Computer Architecture and Organization 32
C Can’t Do Hardware
55:035 Computer Architecture and Organization 33
Verilog-2001
55:035 Computer Architecture and Organization 34
Verification and Modeling
55:035 Computer Architecture and Organization 35
SystemVerilog: Unified Language
55:035 Computer Architecture and Organization 36
Typical Digital System Structure
Execution Unit
(Datapath)
Control Unit
(Control)
Data Inputs
Data Outputs
Control Inputs
Control Outputs
Control Signals
3755:035 Computer Architecture and Organization
Execution Unit (Datapath) Provides All Necessary Resources and
Interconnects Among Them to Perform Specified Task
Examples of Resources Adders, Multipliers, Registers, Memories, etc.
3855:035 Computer Architecture and Organization
Control Unit (Control) Controls Data Movements in an Operational
Circuit by Switching Multiplexers and Enabling or Disabling Resources
Follows Some ‘Program’ or Schedule Often Implemented as Finite State Machine
or collection of Finite State Machines
3955:035 Computer Architecture and Organization
Finite State Machines (FSMs) Any Circuit with Memory Is a Finite State
Machine Even computers can be viewed as huge FSMs
Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization
4055:035 Computer Architecture and Organization
Moore FSM Output Is a Function of a Present State Only
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present StateNext State
Outputs
clock
reset
4155:035 Computer Architecture and Organization
Mealy FSM Output Is a Function of a Present State and
InputsNext State
function
Outputfunction
Inputs
Present StateNext State
Outputs
Present StateRegister
clock
reset
4255:035 Computer Architecture and Organization
Moore Machine
state 1 /output 1
state 2 /output 2
transitioncondition 1
transitioncondition 2
4355:035 Computer Architecture and Organization
Mealy Machine
state 1 state 2
transition condition 1 /output 1
transition condition 2 /output 2
4455:035 Computer Architecture and Organization
Moore vs. Mealy FSM (1) Moore and Mealy FSMs Can Be Functionally
Equivalent Equivalent Mealy FSM can be derived from Moore
FSM and vice versa
Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area
4555:035 Computer Architecture and Organization
Moore vs. Mealy FSM (2) Mealy FSM Computes Outputs as soon as
Inputs Change Mealy FSM responds one clock cycle sooner than
equivalent Moore FSM
Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is more likely to have a shorter critical
path
4655:035 Computer Architecture and Organization
Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
4755:035 Computer Architecture and Organization
Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
4855:035 Computer Architecture and Organization
Moore & Mealy FSMs - Example 1
clock
input
Moore
Mealy
0 1 0 0 0
S0 S1 S2 S0 S0
S0 S1 S0 S0 S0
4955:035 Computer Architecture and Organization
FSMs in VHDL Finite State Machines Can Be Easily Described
With Processes Synthesis Tools Understand FSM Description If
Certain Rules Are Followed State transitions should be described in a process
sensitive to clock and asynchronous reset signals only
Outputs described as concurrent statements outside the clock process
5055:035 Computer Architecture and Organization
Moore FSM
process(clock, reset)
Present StateRegister
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
clock
reset
concurrent statements
5155:035 Computer Architecture and Organization
Mealy FSM
process(clock, reset)
Next Statefunction
Outputfunction
Inputs
Present State
Next State
Outputs
Present StateRegister
clock
reset
concurrent statements
5255:035 Computer Architecture and Organization
Moore FSM - Example 1 Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Meaning of states:
S0: No elements of the sequenceobserved
S1: “1”observed
S2: “10”observed
5355:035 Computer Architecture and Organization
Moore FSM in VHDL (1)TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;
U_Moore: PROCESS (clock, reset)BEGIN
IF(reset = ‘1’) THENMoore_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state IS
WHEN S0 => IF input = ‘1’ THEN
Moore_state <= S1; ELSE Moore_state <= S0; END IF;
5455:035 Computer Architecture and Organization
Moore FSM in VHDL (2) WHEN S1 =>
IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF;
WHEN S2 => IF input = ‘0’ THEN
Moore_state <= S0; ELSE
Moore_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;5555:035 Computer Architecture and Organization
Mealy FSM - Example 1 Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
5655:035 Computer Architecture and Organization
Mealy FSM in VHDL (1)TYPE state IS (S0, S1);SIGNAL Mealy_state: state;
U_Mealy: PROCESS(clock, reset)BEGIN
IF(reset = ‘1’) THENMealy_state <= S0;
ELSIF (clock = ‘1’ AND clock’event) THENCASE Mealy_state IS
WHEN S0 => IF input = ‘1’ THEN
Mealy_state <= S1; ELSE Mealy_state <= S0; END IF;
5755:035 Computer Architecture and Organization
Mealy FSM in VHDL (2)WHEN S1 => IF input = ‘0’ THEN
Mealy_state <= S0; ELSE Mealy_state <= S1; END IF;
END CASE;END IF;
END PROCESS;
Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
5855:035 Computer Architecture and Organization
C z 1 =
resetn
B z 0 = A z 0 = w 0 =
w 1 =
w 1 =
w 0 =
w 0 = w 1 =
Moore FSM - Example 2 State Diagram
5955:035 Computer Architecture and Organization
Present Next state Outputstate w = 0 w = 1 z
A A B 0 B A C 0 C A C 1
Moore FSM - Example 2 State Table
6055:035 Computer Architecture and Organization
Moore FSM
process(clock, reset)
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y
Next State
Output: z
clock
resetn
concurrent statements
6155:035 Computer Architecture and Organization
USE ieee.std_logic_1164.all ;
ENTITY simple ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END simple ;
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;
BEGINPROCESS ( resetn, clock )BEGIN
Moore FSM - Example 2 VHDL (1)
6255:035 Computer Architecture and Organization
IF resetn = '0' THENy <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THENCASE y IS
WHEN A =>IF w = '0' THEN
y <= A ;ELSE
y <= B ;END IF ;
WHEN B =>IF w = '0' THEN
y <= A ;ELSE
y <= C ;END IF ;
Moore FSM - Example 2 VHDL (2)
6355:035 Computer Architecture and Organization
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
Moore FSM - Example 2 VHDL (3)
6455:035 Computer Architecture and Organization
Moore FSM
Present StateRegister
Next Statefunction
Outputfunction
Input: w
Present State: y_present
Next State: y_next
Output: z
clock
resetn
process(w, y_present)
concurrent statements
process(clock, resetn)
6555:035 Computer Architecture and Organization
ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y_present, y_next : State_type ;
BEGINPROCESS ( w, y_present )BEGIN
CASE y_present ISWHEN A =>
IF w = '0' THENy_next <= A ;
ELSEy_next <= B ;
END IF ;
Alternative Example 2 VHDL (1)
6655:035 Computer Architecture and Organization
WHEN B =>IF w = '0' THEN
y_next <= A ;ELSE
y_next <= C ;END IF ;
WHEN C =>IF w = '0' THEN
y_next <= A ;ELSE
y_next <= C ;END IF ;
END CASE ;END PROCESS ;
Alternative Example 2 VHDL (2)
6755:035 Computer Architecture and Organization
PROCESS (clock, resetn)BEGIN
IF resetn = '0' THENy_present <= A ;
ELSIF (clock'EVENT AND clock = '1') THENy_present <= y_next ;
END IF ;END PROCESS ;
z <= '1' WHEN y_present = C ELSE '0' ;END Behavior ;
Alternative Example 2 VHDL (3)
6855:035 Computer Architecture and Organization
A
w 0 = z 0 =
w 1 = z 1 = B w 0 = z 0 =
resetn
w 1 = z 0 =
Mealy FSM - Example 2 State Diagram
6955:035 Computer Architecture and Organization
Present Next state Output z
state w = 0 w = 1 w = 0 w = 1
A A B 0 0 B A B 0 1
Mealy FSM - Example 2 State Table
7055:035 Computer Architecture and Organization
Mealy FSM
process(clock, reset)
Next Statefunction
Outputfunction
Input: w
Present State: yNext State
Output: z
Present StateRegister
clock
resetn
concurrent statements
7155:035 Computer Architecture and Organization
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY Mealy ISPORT ( clock : IN STD_LOGIC ;
resetn : IN STD_LOGIC ; w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;END Mealy ;
ARCHITECTURE Behavior OF Mealy ISTYPE State_type IS (A, B) ;SIGNAL y : State_type ;
BEGIN
Mealy FSM Example 2 VHDL (1)
7255:035 Computer Architecture and Organization
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THENCASE y IS WHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
Mealy FSM Example 2 VHDL (2)
7355:035 Computer Architecture and Organization
WHEN B =>IF w = '0' THEN
y <= A ;ELSE
y <= B ;END IF ;
END CASE ;
END IF ;
END PROCESS ;
WITH y SELECT
z <= w WHEN B,
z <= ‘0’ WHEN others;
END Behavior ;
Mealy FSM Example 2 VHDL (3)
7455:035 Computer Architecture and Organization
State Encoding State Encoding Can Have a Big Influence on
Optimality of the FSM Implementation No methods other than checking all possible
encodings are known to produce optimal circuit Feasible for small circuits only
Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool
7555:035 Computer Architecture and Organization
Types of State Encodings (1) Binary (Sequential) – States Encoded as
Consecutive Binary Numbers Small number of used flip-flops Potentially complex transition functions leading to
slow implementations One-Hot – Only One Bit Is Active
Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs
7655:035 Computer Architecture and Organization
Types of State Encodings (2)
State Binary Code One-Hot CodeS0 000 10000000
S1 001 01000000
S2 010 00100000
S3 011 00010000
S4 100 00001000
S5 101 00000100
S6 110 00000010
S7 111 00000001
7755:035 Computer Architecture and Organization
top related