9-0 multiplexers, decoders, and programmable logic devices powerpoint presentation © 2010. cengage...

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Multiplexers, Decoders, and

Programmable Logic Devices

PowerPoint Presentation

© 2010. Cengage Learning, Engineering. All Rights Reserved.

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UNIT UNIT 99

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Figure 9.1 2-to-1 Multiplexer and Switch Analog

A multiplexer(MUX, or Data selector)

When A is 0, the switch to the upper position, then output Z=I 0

When A is 1, the switch to the lower position, then output Z=I 1

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Figure 9.2 Multiplexers4-to-1 MUX, 8-to-1 MUX, and 2n-to-1 MUX

Take 4-to-1 MUX, it needs 2-control input to select 4-data input. When AB is 00, then we Z=I0. when it is 01,10,11 is corresponding to I1,I2,I3.

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Figure 9.3 Logic Diagram for 8-to-1 MUX

The logic diagram for a 8-to-1 MUX

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Figure 9.4 Quad Multiplexer Used to Select Data

* Multiplexers are frequently used in digital system design to select the data which is to be processed or stored .

*How a quad MUX used to select one of two 4-bit data words… when A=0, X0, X1,X2,X3 is appear to Zo, Z1,Z2,Z3. Otherwise, A=1; Y0, Y1,Y2,Y3 is appear to Zo, Z1,Z2,Z3.

• “Bus” Several logic signals that perform a common function may be grouped together to form a bus.

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Figure 9.6 Gate Circuit with Added Buffer

Gate Circuit with added Buffer

1. A simple buffer may be used to increase the driving capability of a gate output. 2. Two or more gates outputs or other logic device directly connected to each other. When one gate has 0 output(low-voltage), another has 1(high-voltage), then the resulting output don’t clearly represented. Also damage to the gate can occurs.

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Figure 9.7 Three-State BufferA Three-state buffer

When B=1, the output C is equal to AWhen B=0, the output C acts like an open circuit (High-impedance, Hi-Z)

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Figure 9.8 Four Kinds of Three-State Buffers

Four Kinds of Three-state Buffers

Inverted input

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Figure 9.9 Data Selection Using Three-State Buffers

Data-Selection using three-state buffer

This is logically equivalent to using a 2-to-1 MUX.

When select line B is 0, D= AThen B=1, D=C Therefore, D= B’A+ BC

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Figure 9.10 Circuit with two Three-State Buffers

Three-state Buffer shows Hi-Z(open circuit), The possible output is as-below:

Circuit with two three-state buffers

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Figure 9.11 4-Bit Adder with Four Sources for One Operand

A 4-bit adder: setup by a three-state bus buffer

In this circuit, each buffer symbol actually represent 4 three-state buffers that have a common enable signal.

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Figure 9.12 Integrated Circuit with Bi-Directional Input-Output

Pin

Bi-directional pins

The same pin used as input and output, but not both at the same time.

When buffer is Enable, the pin is driven by the output….Then the buffer is disabled, the external source can drive the input…..

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Figure 9.13 A 3-to-8 Line Decoder

Decoder (3-to-8 line Decoder)

Base on the 3 input variables, this decoder generate all of the minterms. Exactly one of the output line is will be 1 for each combination of inputs

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Figure 9.14 A 4-to-10 Line Decoder

Decoder (A 4-to-10 line decoder)

This decoder has inverted outputs exactly one of the output will be 0

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Figure 9.15 Realization of a Multiple-Output Circuit Using a

Decoder

Decoder outputs are inverted

ORing to the output,but for the inverted decoder, the NAND gate used togenerate the function.

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Figure 9.16 An 8-to-3 Priority Encoder

Encoder (A encoder performs the inverse function of a decoder)

A 8x3 encoder

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Priority Encoder (why we need this encoder ?)

When more than one input can be 1 at the same time, the output may not the right. for example, a 8x3 encoder, when A3=1 and A4=1 at the same time, the output is (Y2, Y1, Y0)=(1,1,1). This is not the right output code.

That is the reason why we need a Priority encoder.

If we have y1=1, y4=1, y5=1 at the same time, based on the Priority encoder,the highest numbered input is determined. So y5=1, then output is (101)

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Figure 9.17 An 8-Word X 4-Bit ROM

Read-only Memories(ROM)

1. Each output patterns is stored in the ROM is called a word2. Each input combination serves as an address which can select one of the words stored in the memory.3. We defined a ROM (2n x m ROM), means an array of 2n words and each word is m bits long.

(word)

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Figure 9.18 Read-Only Memory with n inputs and m Outputs

A 2n x m ROM

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Figure 9.19 Basic ROM Structure

A ROM basically consists of a decoder and a memory array

When a pattern is applied to the decoder input, exactly one of the 2n decoder output is 1, this decoder output line selects one of the words in the memory array, and the bit pattern is transferred to the memory output lines.

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Figure 9.20 An 8-Word X 4-Bit ROM

The internal structure of the 8-word x4 bit ROM

The memory array forms the 4 output functions by ORing together selected miniternsFrom previous truth table,

ORing for F0

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Figure 9.22 Hexadecimal-to-ASCII Code Converter

Example: realize a code convertor by using ROMs

Convert a 4-bit binary code to a hexadecimal, and output the 7-bits ASCII code.

A4=A5, A6=A4’ So we only need five ouputs

4 address, creating 16 words; each words shows a 7-bit pattern!

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Figure 9.23 ROM Realization of Code Converter

ROM realization of code convertor

An X indicates that the switching element is present and connected, and no XIndicate that the corresponding element is absent or not connected.

9-24EEPROM

Read-only Memories(ROM)

1. mask-programmable ROMs: a. The data is permanently stored. b. Accomplished by selectively including or omitting the switching elements. by using mask. c. Expensive, not economically feasible.2. Programmable ROMs(PROMs)3. Electrically erasable programmable ROMs(EEPROM): a. using special chage-stroge mechanism to enable or disable the switching elements. b. Suitable for the developmental phase of a digital design. c. EEPROM can be erased and reprogrammed only a limited times(100-1000)

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Figure 9.24 Programmable Logic Array Structure

Programmable logic device (PLD)1.Capable of being programmed to provide a variety of different logic functions.2. Combinational PLD3. Lower cost design

Programmable logic array(PLA) : functions as ROM For a ROM, we implements a truth table; while for a PLA, we implements a sum-of –product expression.

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Figure 9.25 PLA with Three Inputs, Five Product Terms and

Four Outputs

PLA which realized the same function as ROM

For example, F0= A’B’+AC’

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Figure 9.26 AND-OR Array Equivalent to Figure 9.25

PLA which realized the same function as ROM

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Table 9.1 PLA Table for Figure 9.25

PLA table

0: complement1: non-complement- : not present

0: product term not present1: product term present

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Figure 9.27 PLA Realization of Equations (7-23b)

Using PLA to implement the function in Ch7(figure 7-21)

Figure 7-21

Another example of sharing gates among multiple outputs to reduce cost.(From K-map)

f1 = Ʃ m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

f2 = Ʃ m(2, 3, 5, 6, 7, 10, 11, 14, 15)

f3 = Ʃ m(6, 7, 8, 9, 13, 14, 15)

f1 = a′bd + abd + ab′c′ + b′c

f2 = c + a′bd f3 = bc + ab′c′ + abd

Minimal Solution

10 gates 25 gate inputs

8 gates 22 gate inputs

After reduced

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Figure 9.28 PAL Segment

PAL(Programmable Array Logic):One case of PLA, while the OR array is fixed, we only programming the AND array

fixed

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Figure 9.29 Implementation of a Full Adder Using PAL

Example: Programming a PAL to implement a full adder

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Figure 9.30 Architecture of AsXilinx

Complex Programmable Logic Devices (CPLD)

Many PLA or PAL can be included in a CPLD chip and interconnected, a CPLD Is actually a small digital system.

XCR3064XL contain 4 function blocks(as a PLA), each have 16 macrocells.

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Figure 9.31 CPLD Function Block and MarcrocellSelect either combinational out put(G)

or the flip-flop(Q)

Select OR-gate output(F) or it’s complement (F’)

MUX1:

MUX2:

Bi-directional Pin

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Figure 9.32 Layout of a Typical FPGA

Field-programmable gate array (FPGA) FPGA contain an array of logic cells(also called configurable logic blocks, CLB). The user can program the functions based on FPGA.

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Figure 9.33 Simplified Configurable Logic Block (CLB)

A simplified CLB

A 4-input reprogrammable ROM

1. This CLB shows output: X, Y, XQ, YQ2. H1 can select the function generator

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Figure 9.34 Implementation of a Lookup Table (LUT)

The function generator (lookout table, LUT)

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Figure 9.35 Function Expansion Using Kanaugh Map

Decomposition of switching functions Decompose the function into subfunctions where each subfunction requires only 4 variable input.

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Figure 9.36 Realization of 5- and 6-Variable Functions with

Function Generators

The Shannon’s expansion theorem

F (a, b, c, d)= a’ f(0,b,c,d) + a f(1,b,c,d)= a’f0+af1

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Problem 9.32Ch9 HW

9.149.31