a 14b 40msample/s pipelined adc with dfcakxc104/class/cse577/11s/lec/lecture/pipadc.pdf · a 14b...

A 14b 40Msample/s Pipelined ADC with DFCA

Paul Yu, Shereef Shehata, Ashutosh Joharapurkar, Pankaj Chugh, Alex Bugeja, Xiaohong Du, Sung-Ung Kwak, Yiannis Papantonopoulos, Turker Kuyel

Texas Instruments, Inc., Dallas TX

Paul Yu 2 paulyu@alum.mit.edu

Outline

• Description of a Pipelined Architecture

• Error Sources in a Pipelined ADC

• Technique I: DAC and Feedback Capacitor Averaging (DFCA)

• Technique II: Mismatch Noise Cancellation (MNC)

• Conclusion

Paul Yu 3 paulyu@alum.mit.edu

A Pipelined ArchitectureStage 2 Stage 3

m1 bitsMSB

m2 bits

mn bits...

LSB

VRES1VINSHA Σ

m1 bits

Stage 1

2m1-1

ADC DAC

Paul Yu 4 paulyu@alum.mit.edu

Outline

• Description of a Pipelined Architecture

• Error Sources in a Pipelined ADC

• Technique I: DAC and Feedback Capacitor Averaging (DFCA)

• Technique II: Mismatch Noise Cancellation (MNC)

• Conclusion

Paul Yu 5 paulyu@alum.mit.edu

Error Sources in Pipelined ADC Problems• Comparator Offsets• Finite Op-Amp

Gain• kT/C Noise • Capacitor

Mismatch– DAC Error– Interstage Gain

Error

Solutions• Digital Error Correction• High Gain Op-Amps

• Large Cap • Trimming/Calibration, or DFCA, DFCA+MNC (SFDR), (SFDR/SNR)

Paul Yu 6 paulyu@alum.mit.edu

High Resolution ADC TechniquesTechniques Pro ConFactoryCalibration/Trimming

SimpleTest Time,Extra AnalogHardware

Digital SelfCalibration Min. Analog User Burden

BackgroundCalibration

Test Time,Background

DAC orInterstageGain Only

CFCS Simple DNL OnlyProposedDFCA +MNC

Test Time,BackgroundMin. Analog

Extra Digital

Paul Yu 7 paulyu@alum.mit.edu

12

9

14

3 3 3

Block diagram of the ADC

Stage 1 Stage 2 Stage 3 PNG

M N C

Digital Error Correction

33

Stage 6

43

VIN

Chip I with DFCA Chip II with DFCA + MNC

Paul Yu 8 paulyu@alum.mit.edu

Outline

• Description of a Pipelined Architecture

• Error Sources in a Pipelined ADC

• Technique I: DAC and Feedback Capacitor Averaging (DFCA)

• Technique II: Mismatch Noise Cancellation (MNC)

• Conclusion

Paul Yu 9 paulyu@alum.mit.edu

Implementation of 2.8b/Stage

VIN C3

C2

C4

C1

VOUT

C3

C2

C4

C1a VREF

b VREF

c VREF

}{ 10,1,cb,a,:alConvention

−∈

S

Sampling Phase Amplifying Phase

DAC CapacitorsFeedback Capacitor

DFCA

}{ 2, =−∈ f10,1,cb,a,:DFCA

Paul Yu 10 paulyu@alum.mit.edu

DAC Errors Only

DOUT

VRES1

VIN

VIN

IdealC2 = 1 + εC3 = 1 - ε

81

−83

−

REFVC1C2

Paul Yu 11 paulyu@alum.mit.edu

Interstage Gain Error Only

DOUT

VRES1

VIN

VIN

IdealC1 = 1 - εC1 = 1 + ε

81

−83

−

C1

C4

1i∑

Paul Yu 12 paulyu@alum.mit.edu

Parallel Shuffling

c0

c0 b0

c1

f1

PN3PN1

PN2 PN3

f1a1

b1c1

a1

b1

PN3PN1

PN2 PN3

f0a0

b0

a0

f0

C1

C4

C3

C2

6 Pre-Amps

3b ADC

Example:

PN1 = 1, PN2 = 1, PN3 = -1 a1a0 = +1, b1b0 = 0, c1c0 = 0

VREF+

VOUT

VREF-

VCM

Paul Yu 13 paulyu@alum.mit.edu

VREF+Pre-amps

LatchBank

3b ADC

ParallelShufflingNetwork

Analog Domain Shuffling

CapSelectLogic

C3 VOUT

C2

C4

C1

VOUTVIN

VREF-VCM

φ1

φ2

Paul Yu 14 paulyu@alum.mit.edu

0.0 0.5 1.0 1.5 2.0 2.5(MHz)

DFCA SFDR SNR THD

Off 83 dB 77 dB 81 dB

DFCA Results (Chip I) fs = 5MSample/s

DFCA SFDR SNR THD

On 95 dB 74 dB 93 dB

5th

10080604020

0-20-40-600.0 0.5 1.0 1.5 2.0 2.5

(MHz)

5th

fin

3rd 3rd

fin

(dB

)

Paul Yu 15 paulyu@alum.mit.edu

10080604020

0-20-40-600.0 0.5 1.0 1.5 2.0 2.5

(MHz)

5th

fin

3rd

0.0 0.5 1.0 1.5 2.0 2.5(MHz)

DFCA SFDR SNR THD

Off 78 dB 77 dB 77 dB

DFCA Results (Chip I) fs = 40 MSample/s

DFCA SFDR SNR THD

On 84 dB 73 dB 80 dB

5th

fin

3rd(dB

)

Paul Yu 16 paulyu@alum.mit.edu

75

80

85

90

95

0 20 40 60Msample/s

dB

DFCA ONDFCA OFF

SFDR vs. Conversion Speed (Chip I)fin =1MHz

Paul Yu 17 paulyu@alum.mit.edu

Outline

• Description of a Pipelined Architecture

• Error Sources in a Pipelined ADC

• Technique I: DAC and Feedback Capacitor Averaging (DFCA)

• Technique II: Mismatch Noise Cancellation (MNC)

• Conclusion

Paul Yu 18 paulyu@alum.mit.edu

Noise Cancellation CDMA Analogy

X: -1 1 1 -1

PN: -1 1 -1 1

Y: 1 1 -1 -1

Y: 1 1 -1 -1

PN: -1 1 -1 1

X: -1 1 1 -1

Transmit

Receive

Paul Yu 19 paulyu@alum.mit.edu

1

Accum

& Avg

1+∆

DAC Noise Cancellation

Galton, IEEE CAS II, March 2000

ΣVRES1

m1 bits

Stage 1

a

bΣ

PN

∆

=

1-1

ba

•∆•+=

21

PN'VQD2:V Small RESIN

Noise DAC 48476

PN

D2 ∆

ADCD2

Stage 2 ...

2m1-1

ADC

PN

VIN

Paul Yu 20 paulyu@alum.mit.edu

Mismatch Noise Cancellation

VRES1 D2ADC

Stage 2 ...

VIN Σ

m1 bits

Stage 1

2m1-1

ADC DAC

Σ

Gain Noise

DAC Noise

Accum

& Avg

∆i

PNi

D2

PNi

{ }NoiseDACNoise) (Gain 'VQD2 RES1 +=

∆i

VRES1’

Paul Yu 21 paulyu@alum.mit.edu

VRES1

PNi

∆i (Cap Mismatch)

Estimation Logic

Cancellation Logic

3PNi

14

Stage 1 Stages 2-6

Accumulate & Average

123

3

3

MNC Architecture in Chip II

Paul Yu 22 paulyu@alum.mit.edu

MNC Experimental Results (Chip II)

0 5 10 15(MHz)

0 5 10 15(MHz)

-140-120-100

-80-60-40-20

0

0 5 10 15(MHz)

(dB

)

DFCA SFDR SNR

Off 48dB 55dB

DFCA SFDR SNR

ON 80dB 50dB

MNC SFDR SNR

ON 80dB 73dB

Paul Yu 23 paulyu@alum.mit.edu

Chip II Micrograph

M

N

C

Pipelined

Stages 1-6

Clock

Paul Yu 24 paulyu@alum.mit.edu

Conclusion• DFCA Increases SFDR

– Parallel Shuffling• Reduces Number of Switches in Series

– Analog Domain Operation• Minimizes Non-Overlapping Time

• MNC Increases SNR by Digitally Removing both DAC and Gain Noise

• DFCA+MNC

– Background Calibration

– Enables High SFDR, High SNR ADC’s

Paul Yu 25 paulyu@alum.mit.edu

Acknowledgement

• Discussion of DNC and MNC with Dr.

Ian Galton is greatly appreciated.

• Discussion with Dr. Ranjit Gharpurey

and other Members of the Mixed Signal

Product Group at TI is acknowledged.