a survey on reconfigurable computing for signal processing applications

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A survey on Reconfigurable Computing for Signal Processing Applications

Anne Pratoomtong

Spring2002

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History of Reconfigurable Computing

• FPGAs by Xilinx, 1986

Collection of fine grained programmable logic blocks interconnected via wires and programmable switches.

• Programmable digital signal processors (PDSP)

TMS32010 had a hardware multiplier and Harvard architecture with separate on-chip bus for data memory and program memory.

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Reconfigurable computing for DSP

• Pre-Runtime Reconfigurable

• Run-time Reconfigurable (RTR)

-FPGAs base RTR

-Structure Adaptive RTR

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Pre-Runtime Reconfigurable

• Computing system or device logic functionality and interconnect can be customized to suit a specific application through post-fabrication, user-defined programming

• Hardware Platform contains a mix variety of macro module with different characteristic connected via reconfigurable communication network

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Run-time Reconfigurable (RTR)

• System logic and/or interconnect functionality can be modified during application execution

• Useful for DSP applications whose performance and functionality depend on run-time factors such as time-varying noise, runtime environment, computation resources available, or time-varying data set

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FPGAs Base RTR

• The adaptation is done at the hardware level using the FPGA base system.

• Develop methodology for fast and low overhead reconfiguration.

• Software library or driver is developed to handle reconfiguration request

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Structure Adaptive RTR : Self -Adaptive Software

• Digital signal processing system can modify its own structure (i.e. the composition of the signal flow) while it is running.

• Software synthesis tool creates the executable version of SFG.

• Run-time kernel schedules the computational blocks as dictated by the control graph topology and the availability of data and/or request. Each computation blocks are consider as a process which can run in UNIX-based, IBM-PC/DOS etc. platform.

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Structure Adaptive RTR:System-level synthesis

• Extend the capability of the Self-adaptive software.

• Hardware platform is a part of system model and is chosen by the designer.

• Construct system models of all possible aspect of adaptive computing

• Perform synthesis based on the system models to map the application into an execution platform

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Conclusion

• RTR system does not fully utilize the ability to change the structure of the hardware reconfigurable component such as FPGA

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Conclusion

• In some application, the need of RTR is gone when implementation platform consist of multiple computing hardware rather than single computing hardware. The performance factor for the 2 choices depends on communication speed VS reconfigurable overhead, area, and power constraint. In general, the single hardware implementation leads to a more power-area effective system.

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Conclusion

Pre-Runtime RTR

Adaptation Change of application

Change of run-time environment

Flexibility More general Design toward specific application

Complexity Low High

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Conclusion

• Hardware reconfiguration for the RTR system largely occur during the synthesis phase where the real time requirement does not effect the performance. During the runtime, the reconfiguration only occurs in the form of changing the operating mode to minimized the reconfiguration overhead.