ad5260_5262
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1-/2-Channel 15 V Digital Potentiometer AD5260/AD5262
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved.
FEATURES 256 positions AD5260: 1 channel AD5262: 2 channels (independently programmable) Potentiometer replacement
20 kΩ, 50 kΩ, 200 kΩ Low temperature coefficient: 35 ppm/°C 4-wire, SPI-compatible serial data input 5 V to 15 V single-supply; ±5.5 V dual-supply operation Power on midscale preset
APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Stereo channel audio level control Programmable voltage-to-current conversion Programmable filters, delays, time constants Line impedance matching Low resolution DAC replacement
GENERAL DESCRIPTION The AD5260/AD5262 provide a single- or dual-channel, 256-position, digitally controlled variable resistor (VR) device.1 These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5260/AD5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 Ω, 50 Ω, or 200 Ω has a nominal temperature coefficient of 35 ppm/°C. Unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 V or ±5 V provided proper supply voltages are furnished.
Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. The AD5260 contains an 8-bit serial register whereas the AD5262 contains a 9-bit serial register. Each bit is clocked into the register on the positive
FUNCTIONAL BLOCK DIAGRAMS
RDACREGISTER
LOGIC
8
POWER-ONRESET
SERIAL INPUT REGISTER
AD5260SHDN
VDD
VSS
VL
CS
CLKSDI
GND
A W B
SDO
PR
0269
5-00
1
Figure 1. AD5260
RDAC1REGISTER
RDAC2REGISTER
LOGIC
8
POWER-ONRESET
SERIAL INPUT REGISTER
AD5262
SHDN
VDD
VSS
VL
CS
CLKSDI
GND
A1 W1 B1 A2 W2 B2
SDO
PR
0269
5-00
2
Figure 2. AD5262
edge of the CLK pin. The AD5262 address bit determines the corresponding VR latch to be loaded with the last eight bits of the data word during the positive edging of CS strobe. A serial data output pin at the opposite end of the serial register enables simple daisy-chaining in multiple VR applications without additional external decoding logic. An optional reset pin (PR) forces the wiper to the midscale position by loading 0x80 into the VR latch.
The AD5260/AD5262 are available in thin surface-mount 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +85°C. 1 The terms digital potentiometers, VR, and RDAC are used interchangeably.
AD5260/AD5262
Rev. A | Page 2 of 24
TABLE OF CONTENTS Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .. 3
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 14
Theory of Operation ...................................................................... 15
Digital Interfacing ...................................................................... 15
Daisy-Chain Operation ............................................................. 16
RDAC Structure.......................................................................... 16
Programming the Variable Resistor......................................... 16
Programming the Potentiometer Divider ............................... 17
Layout and Power Supply Bypassing ....................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
RDAC Circuit Simulation Model............................................. 18
Macro Model Net List for RDAC ............................................. 18
Applications Information .............................................................. 19
Bipolar DC or AC Operation from Dual Supplies................. 19
Gain Control Compensation .................................................... 19
Programmable Voltage Reference ............................................ 19
8-Bit Bipolar DAC ...................................................................... 19
Bipolar Programmable Gain Amplifier................................... 20
Programmable Voltage Source with Boosted Output ........... 20
Programmable 4 mA-to-20 mA Current Source ................... 20
Programmable Bidirectional Current Source......................... 21
Programmable Low-Pass Filter ................................................ 21
Programmable Oscillator .......................................................... 21
Resistance Scaling ...................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY 8/10—Rev. 0 to Rev. A Updated Format..................................................................Universal Deleted Figure 1; Renumbered Sequentially................................. 1 Changes to General Description Section ...................................... 1 Changes to Conditions of Channel Resistance Matching (AD5262 only) Parameter, Voltage Divider Temperature Coefficient Parameter, Full-Scale Error Parameter, and Zero-Scale Error Parameter, Table 1 ........................................................ 3 Changes to Table 2 and Table 3....................................................... 5 Changes to Table 4............................................................................ 6 Changes to Table 5............................................................................ 7 Changes to Table 6............................................................................ 8
Changes to Figure 11 Caption and Figure 12 ................................9 Changes to Figure 31...................................................................... 12 Changes to Figure 35 Caption ...................................................... 13 Changes to Figure 43 and Figure 46............................................. 14 Deleted Potentiometer Family Selection Guide ......................... 18 Change to Programmable Voltage Source with Boosted Output Section.............................................................................................. 20 Changes to Figure 64...................................................................... 21 Updated Outline Dimensions....................................................... 23 Changes to Ordering Guide .......................................................... 24 3/02—Revision 0: Initial Version
AD5260/AD5262
Rev. A | Page 3 of 24
SPECIFICATIONS ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS VDD = +15 V, VSS = 0 V, or VDD = +5 V, VSS = –5 V; VL = +5 V; VA = +5 V, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil).
Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±¼ +1 LSB Resistor Nonlinearity2 R-INL RWB, VA = no connect −1 ±½ +1 LSB Nominal Resistor Tolerance3 ΔRAB TA = 25°C −30 30 % Resistance Temperature Coefficient ΔRAB/ΔT Wiper = no connect 35 ppm/°C Wiper Resistance RW IW = 1 V/RAB 60 150 Ω Channel Resistance Matching (AD5262 only) ΔRWB/RWB Channel 1 and Channel 2 RWB,
DX = 0x80 0.1 %
Resistance Drift ΔRAB 0.05 %
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution N 8 Bits Differential Nonlinearity4 DNL −1 ±1/4 +1 LSB Integral Nonlinearity4 INL −1 ±1/2 +1 LSB Voltage Divider Temperature Coefficient ΔVW/ΔT Code = half scale 5 ppm/°C Full-Scale Error WFSE Code = full scale −2 −1 +0 LSB Zero-Scale Error VWZSE Code = zero scale 0 1 2 LSB
RESISTOR TERMINALS Voltage Range5 VA, B, W VSS VDD V Ax and Bx Capacitance6 CA,B f = 5 MHz, measured to GND,
code = half scale 25 pF
Wx Capacitance6 CW f = 1 MHz, measured to GND, code = half scale
55 pF
Common-Mode Leakage Current ICM VA = VB = VDD/2 1 nA Shutdown Current7 ISHDN 5 μA
DIGITAL INPUTS and OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL 0.8 V Input Logic High VIH VL = 3 V, VSS = 0 V 2.1 V Input Logic Low VIL VL = 3 V, VSS = 0 V 0.6 V Output Logic High (SDO) VOH RPULL-UP = 2 kΩ to 5 V 4.9 V Output Logic Low (SDO) VOL IOL = 1.6 mA, VLOGIC = 5 V 0.4 V Input Current8 IIL VIN = 0 V or 5 V ±1 μA Input Capacitance6 CIL 5 pF
POWER SUPPLIES Logic Supply VL 2.7 5.5 V Power Single-Supply Range VDD RANGE VSS = 0 V 4.5 16.5 V Power Dual-Supply Range VDD/SS RANGE ±4.5 ±5.5 V Logic Supply Current IL VL = 5 V 60 μA Positive Supply Current IDD VIH = 5 V or VIL = 0 V 1 μA Negative Supply Current ISS VSS= −5 V 1 μA Power Dissipation9 PDISS VIH = 5 V or VIL = 0 V,
VDD = +5 V, VSS = –5 V 0.3 mW
Power Supply Sensitivity PSS ΔVDD= +5 V, ±10% 0.003 0.01 %/%
AD5260/AD5262
Rev. A | Page 4 of 24
Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB BW RAB = 20 kΩ/50 kΩ/200 kΩ 310/130/30 kHz Total Harmonic Distortion THDW VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 20 kΩ 0.014 %
VW Settling Time tS VA = +5 V, VB = −5 V, ±1 LSB error band, RAB = 20 kΩ
5 μs
Crosstalk11 CT VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale code change (AD5262 only)
1 nV-sec
Analog Crosstalk CTA VA1 = VDD, VB1 = 0 V, measure VW1 with VW2 = 5 V p-p at f = 10 kHz, RAB = 20 kΩ/200 kΩ (AD5262 only)
–64 dB
Resistor Noise Voltage eN_WB RWB = 20 kΩ, f = 1 kHz 13 nV/√Hz INTERFACE TIMING CHARACTERISTICS6, 12 Specifications apply to all parts
Clock Frequency fCLK 25 MHz Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 10 ns Data Hold Time tDH 10 ns CLK to SDO Propagation Delay13 tPD RL = 1 kΩ, CL< 20 pF 1 160 ns CS Setup Time tCSS 5 ns
CS High Pulse Width tCSW 20 ns
Reset Pulse Width tRS 50 ns
CLK Fall to CS Rise Hold Time tCSH 0 ns
CS Rise to Clock Rise Setup tCS1 10 ns 1 Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = −5V.
3 VAB = VDD, wiper = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode. 8 Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V. 11 Measured at VW where an adjacent VW is making a full-scale voltage change. 12 See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Switching characteristics are measured using VL = 5 V. 13 Propagation delay depends on value of VDD, RL, and CL.
AD5260/AD5262
Rev. A | Page 5 of 24
TIMING DIAGRAMS
Table 2. AD5260 8-Bit Serial Data Word Format Data
B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 27 26 25 24 23 22 21 20
Table 3. AD5262 9-Bit Serial Data Word Format ADDR Data B8 B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) A0 D7 D6 D5 D4 D3 D2 D1 D0 28 27 26 25 24 23 22 21 20
RDAC REGISTER LOADCS
D7 D6 D5 D4 D3 D2 D1 D0SDI1
0
CLK1
01
0
VOUT1
0
0269
5-00
4
Figure 3. AD5260 Timing Diagram
RDAC REGISTER LOADCS
D7A0 D6 D5 D4 D3 D2 D1 D0SDI1
0
CLK1
01
0
VOUT1
002
695-
005
Figure 4. AD5262 Timing Diagram
1
0
1
0
1
0
1
0
VDDVOUT0V
±1 LSB±1 LSB ERROR BRAND
Ax OR Dx
A'x OR D'x
Dx
D'x
tDS
tCH
tS
tCLtCSS
tPD
tDH
tCSH
tCS1
tCSWCS
SDO(DATA OUT)
SDI(DATA IN)
CLK
0269
5-00
6
Figure 5. Detailed Timing Diagram
PR10
VDD
0V ±1 LSB ERROR BAND±1 LSBD
tRS
tS
0269
5-00
7
Figure 6. Preset Timing Diagram
AD5260/AD5262
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS TA =25°C, unless otherwise noted.
Table 4. Parameter Rating VDD to GND −0.3 V to +17 V VSS to GND 0 V to −7 V VDD to VSS 17 V VL to GND 0 V to +7 V VA, VB, VW to GND VSS, VDD
AX to BX, AX to WX, BX to WX
Intermittent1 ±20 mA Continuous ±5 mA
Digital Inputs and Output Voltage to GND
−0.3 V to VL + 0.3 V, or +7 V (whichever is less)
Operating Temperature Range −40°C to +85°C Maximum Junction Temperature
(TJ MAX) 150°C
Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering,10 sec) 300°C
Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C
Thermal Resistance2 θJA
14-Lead TSSOP 206°C/W 16-Lead TSSOP 150°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance setting.
2 Package power dissipation = (TJ MAX − TA)/θJA.
AD5260/AD5262
Rev. A | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5260
NC = NO CONNECT
1
2
3
4
5
6
7
W
B
VDD
SDI
CLK
SHDN
A 14
13
12
11
10
9
8
NC
VL
VSS
CS
PR
GND
SDO
TOP VIEW(Not to Scale)
0269
5-00
8
Figure 7. AD5260 Pin Configuration
Table 5. AD5260 Pin Function Descriptions Pin No. Mnemonic Description 1 A A Terminal. 2 W Wiper Terminal. 3 B B Terminal. 4 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |VDD| + |VSS| ≤ 15 V). 5 SHDN Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor.
6 CLK Serial Clock Input, Positive Edge Triggered. 7 SDI Serial Data Input. 8 CS Chip Select Input, Active Low. When CS returns high, data is loaded into the RDAC register.
9 PR Active Low Preset to Midscale. Sets RDAC registers to 0x80.
10 GND Ground. 11 VSS Negative Power Supply. Specified for operation from 0 V to −5 V. 12 VL Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260. 13 NC No Connect. Users should not connect anything other than a dummy pad on this pin. 14 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor.
AD5260/AD5262
Rev. A | Page 8 of 24
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD5262TOP VIEW
(Not to Scale)
W1
B1
VDD
SDI
CLK
SHDN
A1 W2
B2
A2SDO
VL
VSS
CS
PR
GND
0269
5-00
9
Figure 8. AD5262 Pin Configuration
Table 6. AD5262 Pin Function Descriptions Pin No. Mnemonic Description 1 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor. 2 A1 A Terminal RDAC 1. 3 W1 Wiper RDAC 1, Address A0 = 0. 4 B1 B Terminal RDAC 1. 5 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V) 6 SHDN Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.
7 CLK Serial Clock Input, Positive Edge Triggered. 8 SDI Serial Data Input. 9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the
Address Bit A0, and loaded into the target RDAC register. 10 PR Active Low Preset to Midscale. Sets RDAC registers to 0x80.
11 GND Ground. 12 VSS Negative Power Supply. Specified for operation at either 0 V or −5 V (sum of |VDD| + |VSS| < 15 V). 13 VL Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262. 14 B2 B Terminal RDAC 2. 15 W2 Wiper RDAC 2, Address A0 = 1. 16 A2 A Terminal RDAC 2.
AD5260/AD5262
Rev. A | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTE
NTI
OM
ETER
MO
DE
DNL
(LSB
)
TA = –40°CTA = +25°C
TA = +85°CTA = +125°C
CODE (Decimal)0 32 64 96 128 160 192 224 256
0269
5-01
3
VDD = +5VVSS = –5VRAB = 20kΩ
CODE (Decimal)
RH
EOST
AT
MO
DE
INL
(LSB
)
–0.2
–0.1
0.1
0
0 32 64 96 128 160 192 224 256
0.2
0.3
0.4
0.5
0.6
0.7
0.8
+15V
+5V
±5V+12V
0269
5-01
0
Figure 12. DNL vs. Code Figure 9. R-INL vs. Code vs. Supply Voltages
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0 32 64 96 128 160 192 224 256
CODE (Decimal)
POTE
NTI
OM
ETER
MO
DE
INL
(LSB
)
+15V
+5V±5V
0269
5-01
4
CODE (Decimal)
RH
EOST
AT
MO
DE
DN
L (L
SB)
–0.250 32 64 96 128 160 192 224 256
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
+15V+12V
+5V±5V
0269
5-01
1
Figure 13. INL vs. Code vs. Supply Voltages Figure 10. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTE
NTI
OM
ETER
MO
DE
DNL
(LSB
)
0 32 64 96 128 160 192 224 256
CODE (Decimal)
+15V+5V
±5V
0269
5-01
5
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 32 64 96 128 160 192 224 256CODE (Decimal)
POTE
NTI
OM
ETER
MO
DE
INL
(LSB
)
VDD = +5VTA = +125°C
TA = +85°CTA = –40°C
TA = +25°C
VSS = –5VRAB = 20kΩ
0269
5-01
2
Figure 14. DNL vs. Code vs. Supply Voltages Figure 11. INL vs. Code
AD5260/AD5262
Rev. A | Page 10 of 24
–1.0
–0.5
0
0.5
1.0
0 5 10 15 20
|VDD – VSS| (V)
POTE
NTI
OM
ETER
MO
DE
INL
(LSB
)
AVG – 3σ
AVG
AVG + 3σ
0269
5-01
6
Figure 15. INL vs. Supply Voltages
–2.0
–1.0
–1.5
–0.5
0
0.5
2.0
1.0
1.5
0 5 10 15 20
|VDD – VSS| (V)
RH
EOST
AT M
OD
E IN
L (L
SB)
AVG – 3σ
AVG
AVG + 3σ
0269
5-01
7
Figure 16. R-INL vs. Supply Voltages
4
24
44
64
84
104
124
–5 –1 3 7 11 15VDD (V)
WIP
ER R
ESIS
TAN
CE
(Ω)
RON @ VDD/VSS = +5V/0V
RON @ VDD/VSS = +5V/–5V
RON @ VDD/VSS = +15V/0V
0269
5-01
8
Figure 17. Wiper On Resistance vs. Bias Voltage
0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 20 40 60 80 100TEMPERATURE (°C)
FSE
(LSB
)
VDD/VSS = +5V/0V
VDD/VSS = +15/0V
VDD/VSS = ±5V
0269
5-01
9
Figure 18. Full-Scale Error vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 20 40 60 80 100TEMPERATURE (°C)
ZSE
(LSB
)
VDD/VSS = +15/0V
VDD/VSS = ±5V
VDD/VSS = +5V/0V
0269
5-02
0
Figure 19. Zero-Scale Error vs. Temperature
0.001
0.01
0.1
1
–40 –7 26 59 92 12TEMPERATURE (°C)
I DD
/I SS
SUPP
LY C
UR
REN
T (µ
A)
5
VLOGIC = 5VVIH = 5VVIL = 0V
VDD/VSS = ±5V
VDD/VSS = +15/0V
0269
5-02
1
Figure 20. Supply Current vs. Temperature
AD5260/AD5262
Rev. A | Page 11 of 24
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
–40 –7 26 59 92 12TEMPERATURE (°C)
I LO
GIC
(µA
)
5
VDD/VSS = ±5V
VDD/VSS = +15/0V
0269
5-02
2
Figure 21. ILOGIC vs. Temperature
10
100
1000
0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0
VIH (V)
I LO
GIC
(µA
)
0269
5-02
3
VDD/VSS = 5V/0VVLOGIC = 5V
VDD/VSS = 5V/0VVLOGIC = 3V
Figure 22. ILOGIC vs. Digital Input Voltage
–20
–10
0
10
20
30
40
50
60
70
80
0 32 64 96 128 160 192 224 256CODE (Decimal)
RH
EOST
AT M
OD
E TE
MPC
O (p
pm/°
C)
50kΩ
20kΩ
200kΩ
0269
5-02
4
Figure 23. Rheostat Mode Tempco ΔRWB /ΔT vs. Code
–60
–40
–20
0
20
40
60
80
100
120
0 32 64 96 128 160 192 224 256CODE (Decimal)
POTE
NTI
OM
ETER
MO
DE
TEM
PCO
(ppm
/°C
)
50kΩ
20kΩ
200kΩ
0269
5-02
5
Figure 24. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
FREQUENCY (Hz)
GA
IN (d
B)
1k 1M
6
–48
–54
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
CODE = 0xFF
0x010x02
0x04
0x08
0x10
0x20
0x40
0x80
TA = 25°C
0269
5-02
6
Figure 25. Gain vs. Frequency vs. Code, RAB = 20 kΩ
FREQUENCY (Hz)
GA
IN (d
B)
1k 1M
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
CODE = 0xFF
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
TA = 25°C
0269
5-02
7
–54
Figure 26. Gain vs. Frequency vs. Code, RAB = 50 kΩ
AD5260/AD5262
Rev. A | Page 12 of 24
FREQUENCY (Hz)
GA
IN (d
B)
1k 1M–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
10k 100k
TA = 25°C CODE = 0xFF
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
0269
5-02
8
Figure 27. Gain vs. Frequency vs. Code, RAB = 200 kΩ
FREQUENCY (Hz)
1k 1M10k 100k
–3dBBANDWIDTHS
VIN = 50mV rmsVDD/VSS= ±5V
f–3dB = 30kHz, R = 200kΩ
f–3dB = 131kHz, R = 50kΩ
f–3dB = 310kHz, R = 20kΩ
GA
IN (d
B)
–54
6
–48
–42
–36
–30
–24
–18
–12
–6
0
0269
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9
Figure 28. −3 dB Bandwidth
FREQUENCY (Hz)
NO
RM
ALI
ZED
GA
IN F
LATN
ESS
(dB
)
100 100k1k
0
0.1
0.2
0.3
–0.4
–0.3
–0.2
–0.7
–0.6
–0.5
–0.1
10k
CODE = 0x80VDD/VSS= ±5VTA = 25°C
R = 200kΩ
R = 50kΩ
R = 20kΩ
0269
5-03
0
Figure 29. Normalized Gain Flatness vs. Frequency
FREQUENCY (Hz)
I LO
GIC
(µA
)
10k 10M100k
600
300
400
500
0
100
200
1M
CODE 0xFF
CODE 0x55
VDD/VSS = ±5V
VDD/VSS = +5V/0V
0269
5-03
1
Figure 30. ILOGIC vs. Frequency
FREQUENCY (Hz)
PSR
R (d
B)
100 1M0
60
10k
10
1k
20
30
40
50
100k
–PSRR @ VDD = ±5V DC ± 10% p-p AC
+PSRR @ VDD = ±5V DC ± 10% p-p AC
CODE = 0x80, VA = VDD, VB = 0V
0269
5-03
2
Figure 31. PSRR vs. Frequency
20mV/DIV
1µs/DIV
5V/DIV
0269
5-03
3
Figure 32. Midscale Glitch Energy, Code 0x80 to 0x7F
AD5260/AD5262
Rev. A | Page 13 of 24
HOURS OF OPERATION AT 150°C
CH
AN
GE
IN T
ERM
INA
L R
ESIS
TAN
CE
(%)
0 5–0.20
0.10
–0.10
0
0.05
00100 200 250 300 350 400 450
AVG – 3σ
50 150
–0.05
–0.15
AVG + 3σ
AVG
0269
5-03
7
CODE = 0x80VDD/VSS= ±5VSAMPLE SIZE = 135 UNITS
5V/DIV
20µs/DIV
5V/DIV
0269
5-03
4
Figure 36. Long-Term Resistance Drift Figure 33. Large Signal Settling Time
CHANNEL-TO-CHANNEL RAB MATCH (%)
FREQ
UEN
CY
–0.500
40
30
CODE SET TO MIDSCALETA = 150°C3 LOTSSAMPLE SIZE = 135 UNITS
20
10
–0.40 –0.30 –0.20 –0.10 0 0.10 0.20
0269
5-03
8
10mV/DIV
40ns/DIV
0269
5-03
5
Figure 34. Digital Feedthrough vs. Time Figure 37. Channel-to-Channel Resistance Matching (AD5262)
CODE (Decimal)
THEO
RET
ICA
L I W
B_M
AX (m
A)
0 20.01
100
0.1
1
10
5632 64 96 128 160 192 224
VA = VB = OPENTA = 25°C
RAB = 20kΩ
RAB = 50kΩ
RAB = 200kΩ
0269
5-03
6
Figure 35. Theoretical Maximum Current vs. Code
AD5260/AD5262
Rev. A | Page 14 of 24
TEST CIRCUITS Figure 38 to Figure 46 define the test conditions used in Table 1.
VMS
AW
B
DUT V+ = VDD1LSB = V+/2N
V+
0269
5-03
9
Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL)
NC
IW
VMS
AW
B
DUT NC = NO CONNECT
0269
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0
Figure 39. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
IW = VDD/RNOMINAL
VMS2VW
VMS1 RW = (VMS1 – VMS2)/IW
AW
B
DUT
0269
5-04
1
Figure 40. Wiper Resistance
PSS (%/%) =
V+ = VDD ± 10%PSRR (dB) = 20 log
∆VMS∆VDD
∆VMS%∆VDD%
( )VDD
VA
VMS
AW
B
V+
0269
5-04
2
Figure 41. Power Supply Sensitivity (PSS, PSSR)
+13V
–13V
W
A
B
VOUTOFFSETGND
DUTAD8610
VIN
0269
5-04
3
Figure 42. Gain vs. Frequency
W
B
VSS TO VDD
DUTCODE = 0x00
RW = 0.1VIW
IW 0.1V
A = NC
0269
5-04
4
Figure 43. Incremental On Resistance
W
B
ICMA
NC
GND
NC
VSS VCM
VDD
DUT
0269
5-04
5
Figure 44. Common-Mode Leakage Current
SDI
CLK
CS
VLOGICILOGIC
DIGITAL INPUTVOLTAGE
0269
5-04
6
Figure 45. VLOGIC Current vs. Digital Input Voltage
A1RDAC1 RDAC2
W1NC
B1
A2
W2
B2
CTA = 20 log (VOUT/VIN)NC = NO CONNECT
VINVOUT
VSS
VDD
0269
5-04
7
Figure 46. Analog Crosstalk
AD5260/AD5262
Rev. A | Page 15 of 24
THEORY OF OPERATION The AD5260/AD5262 provide a single- or dual-channel, 256-position, digitally controlled variable resistor (VR) device and operate up to 15 V maximum voltage. Changing the programmed VR settings is accomplished by clocking an 8-/9-bit serial data word into the SDI (serial data input) pin. For the AD5262, the format of this data word is one address bit. A0 represents the first bit, B8, followed by eight data bits, B7 to B0, with MSB first. Table 2 and Table 3 provide the serial register data word format. See Table 7 for the AD5262 address assignment to decode the location of the VR latch receiving the serial register data in Bit B7 through Bit B0. VR outputs can be changed one at a time in random sequence. The AD5260/AD5262 preset to a midscale, simplifying fault condition recovery at power-up. Midscale can also be achieved at any time by asserting the PR pin. Both parts have an internal power-on preset that places the wiper in a midscale preset condition at power-on. Operation of the power-on preset function depends only on the state of the VL pin.
The AD5260/AD5262 contain a power shutdown SHDN pin that places the RDAC in an almost zero power consumption state where Terminals Ax are open circuited and the Wiper W is connected to B, resulting in only leakage currents being con-sumed in the VR structure. In the shutdown mode, the VR latch settings are maintained so that, when returning to operational mode from power shutdown, the VR settings return to their previous resistance values.
Table 7. AD5262 Address Decode Table A0 Latch Loaded 0 RDAC1 1 RDAC2
DIGITAL INTERFACING The AD5260/AD5262 contain a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). For the AD5260, the 8-bit serial word must be loaded with the MSB first. The format of the word is shown in . For the AD5262, the 9-bit serial word must be loaded with Address Bit A0 first, then the MSB of the data. The format of the word is shown in .
Table 2
Table 3
A0SERREG
D7D6D5D4D3D2D1D0
A1W1B1
VDD
CS
CLK
SDO
A2W2
B2
GND
RDACLATCH
2
PR
RDACLATCH
1PR
PR
SDI
VL
VSS
SHDNPOWER-ON
PRESET
EN
ADDRDEC
0269
5-04
8
Figure 47. AD5262 Block Diagram
The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Stand-ard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 47 shows more detail of the inter-nal digital circuitry. When CS is low, the clock loads data into the serial input register on each positive clock edge (see ). Table 8
Table 8. Truth Table1 CLK CS PR SHDN Register Activity Low Low High High No SR effect, enables SDO pin. ↑ Low High High Shift one bit in from the SDI pin.
The eighth previously entered bit is shifted out of the SDO pin.
X ↑ High High Load SR data into RDAC latch. X High High High No operation. X X Low High Sets all RDAC latches to half
scale, wiper centered, and SDO latch cleared.
X High ↑ High Latches all RDAC latches to 0x80. X High High Low Open circuits all Resistor A
terminals, connects W to B, and turns off SDO output transistor.
1 ↑ = positive edge, X = don’t care, SR = shift register.
The data setup and data hold times in Table 1 determine the data valid time requirements. The AD5260 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. For the AD5262, the last nine bits of the data word entered into the serial register are held when CS returns high. Any extra bits are ignored. At the same time CS goes high, it gates the address decoder, enabling one of two positive edge-triggered AD5262 RDAC latches (see ). Figure 48
AD5260/AD5262
Rev. A | Page 16 of 24
RDAC1
RDAC2
AD5260/AD5262
SDI
CLK
CS ADDRDECODE
SERIALREGISTER
0269
5-04
9
Figure 48. Equivalent Input Control Logic
The target RDAC latch is loaded with the last eight bits of the serial data word completing one RDAC update. For the AD5262, two separate 9-bit data words must be clocked in to change both VR settings.
During shutdown (SHDN), the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. See for the equivalent SDO output circuit schematic.
Figure 49
SDI
CLK
CS
SHDN
PR
SERIALREGISTER
D Q
CK RS
SDO
0269
5-05
0
Figure 49. Detail SDO Output Schematic of the AD5260
All digital inputs are protected with a series input resistor and parallel Zener ESD structure as shown in Figure 50. This applies to the CS, SDI, SDO, PR, SHDN, and CLK digital input pins.
340ΩLOGIC
0269
5-05
1
Figure 50. ESD Protection of Digital Pins
A, B, W
VSS
0269
5-05
2
Figure 51. ESD Protection of Resistor Terminals
DAISY-CHAIN OPERATION The serial data output (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor to transfer data to the SDI pin of the next package. This allows for daisy-chaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be larger than the VDD supply voltage. It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the following device in series because capacitive loading at the daisy-chain node connecting SDO and SDI between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 52). If two AD5260s are daisy-chained, this requires a total of 16 bits of data. The first eight bits, complying with the format shown in Table 2, go to U2, and the second eight bits with the same format go to U1. The CS pin should be kept low until all 16 bits are clocked into their respective serial
registers, and the CS pin is then pulled high to complete the operation.
VDD
CS CLK
SDOSDIMOSI
MICRO-CONTROLLER
SCLK SS
RP2.2kΩ
AD5260 AD5260U1 U2
0269
5-05
5
CS CLK
SDOSDI
Figure 52. Daisy-Chain Configuration
RDAC STRUCTURE The RDAC contains a string of equal resistor segments with an array of analog switches that act as the wiper connection. The number of positions is the resolution of the device. The AD5260/ AD5262 have 256 connection points, allowing it to provide better than 0.4% settability resolution. Figure 53 shows an equivalent structure of the connections between the three terminals that make up one channel of the RDAC. SWA and SWB are always on, while one of the switches SW(0) to SW(2N – 1) is on one at a time, depending on the resistance position decoded from the data bits. Because the switch is not ideal, there is a 60 Ω wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage is, the higher the wiper resistance becomes. Similarly, the higher the temperature is, the higher the wiper resistance becomes. Users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed.
D7D6D5D4D3D2D1D0
RDACLATCH
ANDDECODE
Ax
Wx
BxRS = RAB/2N
RS
RS
RS
RSSHDN
DIGITAL CIRCUITRYOMITTED FOR CLARITY 02
695-
056
Figure 53. Simplified RDAC Architecture
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistances of the RDAC between Terminal A and Terminal B are available with values of 20 kΩ, 50 kΩ, and 200 kΩ. The final three digits of the part number determine the nominal resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, 200 kΩ = 200. The nominal resistance (RAB) of the VR has 256 contact points
AD5260/AD5262
Rev. A | Page 17 of 24
accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 60 Ω wiper contact resistance, such a connection yields a minimum of 60 Ω resistance between Terminal W and Terminal B. The second connection is the first tap point corresponding to 138 Ω (RWB = RAB/256 RW = 78 Ω + 60 Ω) for Data 0x01. The third connection is the next tap point representing 216 Ω (78 × 2 + 60) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19,982 Ω (RAB − 1 LSB + RW). The wiper does not directly connect to the B terminal. See Figure 53 for a simplified diagram of the equivalent RDAC circuit.
The general equation determining the digitally programmed output resistance between W and B is
WABWB RRDDR +×=256
)( (1)
where D is the decimal equivalent of the binary code that is loaded in the 8-bit RDAC register and RAB is the nominal end-to-end resistance.
For example, when RAB = 20 kΩ, VB = 0 V, and the A terminal is open circuit, the following output resistance values of RWB are set for the RDAC latch codes shown in Table 9. The result is the same if Terminal A is tied to W.
Table 9. RWB vs. Code RDAC (Dec) RWB (Ω) Output State 256 19,982 Full scale (RAB – 1 LSB + RW) 128 10,060 Midscale 1 138 1 LSB 0 60 Zero-scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches.
Like the mechanical potentiometer the RDAC replaces, the AD5260/AD5262 are completely symmetrical. The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. Figure 54 shows the symmetrical programmability of the various terminal connec-tions. When RWA is used, the B terminal can be left floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is
WABWA RRDDR +×−
=256
256)( (2)
For example, when RAB = 20 kΩ, VA = 0 V, and the B terminal is open circuit, the following output resistance values of RWA are
set for the RDAC latch codes shown in Table 10. The result is the same if Terminal B is tied to Terminal W.
Table 10. RWA vs. Code RDAC (Dec) RWA (Ω) Output State 256 60 Full scale 128 10,060 Half scale 1 19,982 1 LSB 0 20,060 Zero scale
RWA RWB
RAB = 20kΩ
CODE (Decimal)
20
0 64 128 192 256
RW
A(D
), R
WB
(D) –
kΩ
16
12
8
4
0
0269
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7
Figure 54. AD5260/AD5262 Equivalent RDAC Circuit
The typical distribution of the nominal resistance RAB from channel to channel matches within ±1%. Device-to-device matching is process lot-dependent with the worst case of ±30% variation. However, because the resistance element is processed in thin film technology, the change in RAB with temperature has a low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Ignore the effect of the wiper resistance. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at W-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. Because the AD5260/AD5262 operate from dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltage applied to Terminal A and Terminal B is
BABW VVDDV +×=256
)( (3)
Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors, RWA and RWB, and not the absolute values; therefore, the drift reduces to 5 ppm/°C.
AD5260/AD5262
Rev. A | Page 18 of 24
LAYOUT AND POWER SUPPLY BYPASSING It is good practice to employ a compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (see Figure 55). Note that the digital ground should also be joined remotely to the analog ground to minimize the ground bounce.
VSS
VDD
VSS
VDD
C3
C4
C1
C2
10µF
10µF GND0.1µF
0.1µF
+
+
0269
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3
Figure 55. Power Supply Bypassing
TERMINAL VOLTAGE OPERATING RANGE The AD5260/AD5262 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 56).
VDD
VSS
A
W
B
0269
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4
Figure 56. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5260/AD5262 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the AD5260/AD5262 must be referenced to the device ground pin (GND), and must satisfy the logic level defined in Table 1. An internal level shift circuit ensures that the common-mode
voltage range of the three terminals extends from VSS to VDD regardless of the digital input level.
POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 56), it is important to power VDD/VSS first before applying any voltage to the A, B, and W terminals. Otherwise, the diode becomes forward biased such that VDD/VSS are powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, VDD, VSS, VL, the digital inputs, and VA/VB/VW. The order of powering VA/VB/VW and the digital inputs is not important as long as they are powered after VDD/VSS.
RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the −3 dB bandwidth of the AD5260 (20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides the large signal Bode plot characteristics of the three available resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simula-tion model is shown in Figure 57. The following section provides a macro model net list for the 20 kΩ RDAC.
A B
55pF
CB25pF
CA25pF
CW
RDAC20kΩ
W
0269
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1
Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ
MACRO MODEL NET LIST FOR RDAC PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12 RWA A W (1-D/256)*RDAC+60 CW W 0 55E-12 RWB W B D/256*RDAC+60 CB B 0 25E-12 *
.ENDS DPOT
AD5260/AD5262
Rev. A | Page 19 of 24
APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES The AD5260/AD5262 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as VDD/VSS, can be applied directly across Terminal A and Terminal B with output taken from Terminal W. See Figure 58 for a typical circuit connection.
+5.0V
CLK
CS
GND
VDD
SDIGND
VDD
VSS
–5.0V
SCLK
MOSI
MICROCONTROLLERSS ±5V p-p
±2.5V p-p
D = 0x80
0269
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8
Figure 58. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION Digital potentiometers are commonly used in gain control as in the noninverting gain amplifier shown in Figure 59.
U1 VO
W
B A
R2200kΩ
C24.7pF
Vi
R147kΩ
C125pF
0269
5-05
9
Figure 59. Typical Noninvertng Gain Amplifier
Note that when the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/βO term with +20 dB/dec, whereas a typical op amp gain bandwidth product (GBP) has −20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Therefore, the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input.
Depending on the op amp GBP, reducing the feedback resistor may extend the zero’s frequency far enough to overcome the problem. A better approach, however, is to include a compensa-tion capacitor, C2, to cancel the effect caused by C1. Optimum compensation occurs when R1 × C1 = R2 × C2. This is not an option because of the variation of R2. As a result, the R1 × C1 = R2 × C2 relationship can be used, and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However,
it avoids the ringing or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few picofarads (pF) to no more than a few tenths of pF is usually adequate for the compensation.
Similarly, there are W and A terminal capacitances connected to the output (not shown). Fortunately, their effect at this node is less significant, and the compensation can be avoided in most cases.
PROGRAMMABLE VOLTAGE REFERENCE For voltage divider mode operation, shown in Figure 60, it is common to buffer the output of the digital potentiometer unless the load is much larger than RWB. Not only does the buffer serve the purpose of impedance conversion, but it also allows a heavier load to be driven.
A1
VO
5VVIN
GND
VOUT
5V
AD1582
U1
AD8601
1
2
3A
W
B
AD5260
0269
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0
Figure 60. Programmable Voltage Reference
8-BIT BIPOLAR DAC Figure 61 shows a low cost 8-bit bipolar DAC. It offers the same number of adjustable steps but not the precision of conventional DACs. The linearity and temperature coefficients, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is
REFO VDV ×⎟⎠⎞
⎜⎝⎛ −= 1
2562 (4)
A2 –5V
OP2177
B A
W
W1
A1
VO
+5V
–5V
+5V
U2
+5VREF –5VREF
VIN
VOUT
GNDTRIM
AD5260Vi
ADR425
R R
U1
OP2177
0269
5-06
1
Figure 61. 8-Bit Bipolar DAC
AD5260/AD5262
Rev. A | Page 20 of 24
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER For applications that require bipolar gain, Figure 62 shows one implementation. Digital Potentiometer U1 sets the adjustment range. The wiper voltage at W2 can therefore be programmed between Vi and −KVi at a given U2 setting. Configuring A2 in the noninverting mode allows linear gain and attenuation. The transfer function is
( ) ⎟⎠⎞
⎜⎝⎛ −+××⎟
⎠⎞
⎜⎝⎛ += KKD
R1R2
VV
i
O 1256
21 (5)
where K is the ratio of RWB1/RWA1 set by U1.
–KVi
A1 B1
A2
R1
R2
VDD
VSS
VSS
VDD
OP2177
OP2177
A2 B2W2
U2AD5262
U1AD5262
W1
A1
VO
C1
Vi
0269
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2
Figure 62. Bipolar Programmable Gain Amplifier
Similar to the previous example, in the simpler and more common case, where K = 1, with a single digital potentiometer, AD5260, U1 is replaced by a matched pair of resistors to apply Vi and −Vi at the ends of the digital potentiometer. The relation-ship becomes
iO VDR1R2V ×⎟
⎠⎞
⎜⎝⎛ −⎟⎠⎞
⎜⎝⎛ += 1
256221 (6)
If R2 is large, a few picofarad compensation capacitors may be needed to avoid any gain peaking.
Table 11 shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution.
Table 11. Result of Bipolar Gain Amplifier D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1 0 −1 −2 −10 64 −0.5 −1 −5 128 0 0 0 192 +0.5 +1 +5 255 +0.968 +1.937 +9.680
PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustment such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 63).
Vi
A1
VO
WU1
A
B
CC
IL
5V
SIGNAL LON1
R1 10kΩ P1 RBIAS
U1 = AD5260A1 = AD8601, AD8605, AD8541P1 = FDP360P, NDS9430N1 = FDV301N, 2N7002
0269
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3
Figure 63. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VO to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-channel FET, P1. The N-channel FET, N1, simplifies the op amp driving requirement. A1 must be the rail-to-rail input type. Resistor R1 is needed to prevent P1 from turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn-off time. N1 can be any general-purpose signal FET. However, P1 is driven in the saturation state, and there-fore, its power handling must be adequate to dissipate (Vi − VO) × IL power. This circuit can source a maximum of 100 mA at 5 V supply. Higher current can be achieved with P1 in a larger pack-age. Note that a single N-channel FET can replace P1, N1, and R1 altogether. However, the output swing is limited unless sepa-rate power supplies are used. For a precision application, a voltage reference such as the ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer.
PROGRAMMABLE 4 mA-TO-20 mA CURRENT SOURCE A programmable 4 mA-to-20 mA current source can be implemented with the circuit shown in Figure 64. REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across Terminal B to Terminal W of the digital potentiometer, divided by RS.
S
REFL R
DVI
×= (7)
AD5260/AD5262
Rev. A | Page 21 of 24
–5V
OP1177+
–U2
+5V
RS102Ω
RL100Ω
VL
IL
A
B WAD5260C11µFGND
REF191SLEEP
VS
OUTPUT
+5V
U12
3
4
60V TO (2.048V + VL)
–2.048 TO VL
0269
5-06
4
Figure 64. Programmable 4-to-20 mA Current Source
The circuit is simple, but be aware that dual-supply op amps are ideal because the ground potential of REF191 can swing from −2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system is reduced.
PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 65). If the resistors are matched, the load current is
( )WL V
BRR1BRAR
I ×+
=2
22 (8)
AD8016+15V
–15V
+5V
–5V
OP2177AD5260
A1
W
A
B
C210pF
R1'150kΩ
R1150kΩ
R2'15kΩ
A2
C110pF
R2A14.95kΩ RL
500Ω
RL50Ω
+15V
–15V
VL
IL
0269
5-06
5
Figure 65. Programmable Bidirectional Current Source
PROGRAMMABLE LOW-PASS FILTER Digital Potentiometer AD5262 can be used to construct a second-order, Sallen-Key low-pass filter (see Figure 66). The design equations are
22
2
OO
O
i
O
SQ
SVV
ωωω
++= (9)
R1R2C1C2O1
=ω (10)
R2C2R1C1Q 11
+= (11)
Users can first select any convenient value for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, users can adjust R1 and R2 to the same settings to achieve the desirable bandwidth.
A BVi
AD8601
+2.5V
VO
–2.5V
WR
R2R1A B
WR
C1
C2
ADJUSTED TOSAME SETTINGS 02
695-
066
Figure 66. Sallen Key Low-Pass Filter
PROGRAMMABLE OSCILLATOR In a classic Wien-bridge oscillator (see Figure 67), the Wien network (R, R’, C, C’) provides positive feedback, whereas R1 and R2 provide negative feedback. At the resonant frequency, fo, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B + RDIODE), the oscillation frequency is
RCO1
=ω or RC
f O π21
= (12)
where R is equal to RWA such that
ABRDR256
256−= (13)
At resonance, setting
2=R1R2 (14)
balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. However, the alternate turn-on of the diodes, D1 and D2, ensures R2/R1 to be smaller than 2 momentarily and therefore stabilizes the oscillation.
When the frequency is set, the oscillation amplitude can be tuned by R2B because
DDO VBRIV += 232 (15)
VO, ID, and VD are interdependent variables. With proper selection of R2B, an equilibrium is reached such that VO converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output.
In both circuits in Figure 66 and Figure 67, the frequency tuning requires that both RDACs be adjusted to the same settings. Because the two channels are adjusted one at a time, an intermedi-
AD5260/AD5262
Rev. A | Page 22 of 24
d
ts can be programmed to the same setting simultaneously.
ate state occurs that may not be acceptable for certain applications.As a result, different devices can also be used in daisy-chainemode so that par
In voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in Figure 69. The equivalent resistance becomes
WeqWB RR2R1DR += )//(256_ (16)
+5V
OP1177 VO
–5V
R2A2.1kΩ D1
D2
R2B10kΩ
VN
R11kΩ
ABW
R1 = R1' = R2B = AD5262D1 = D2 = 1N4148
AD5262
C'2.2nF R'
10kΩ
A BW
VP
C2.2nF
FREQUENCYADJUSTMENT
R10kΩ
A
B
W
U1
AMPLITUDE
WeqWA RR2R1DR +⎟⎠⎞
⎜⎝⎛ −= )//(
2561_ (17)
W
A
B
R2 R1
R2 << R1
0269
5-06
9
Figure 69. Lowering the Nominal Resistance
ADJUSTMENT 0269
5-
067
cillator with Amplitude Control
le
o program both channels coherently with the same settings.
Figure 68 and Figure 69 show that the digital potentiometers change steps linearly. However, log taper adjustment is usually preferred in applications like audio control. Figure 70 shows another method of resistance scaling. In this circuit, the smaller R2 is with respect to RAB, the more the pseudo-log taper characteristic behaves.
Figure 67. Programmable Os
RESISTANCE SCALING The AD5260/AD5262 offer 20 kΩ, 50 kΩ, and 200 kΩ nominal resistance. For users who need lower resistance and still main-tain the numbers of step adjustment, they can place multipdevices in parallel. For example, Figure 68 shows a simple scheme of paralleling both channels of the AD5262. To adjust half of the resistance linearly per step, users need t
VOA
BR1
R2
Vi
W
0269
5-07
0
W1
A1
B1W2
A2
B2
V
LD
DD
0269
5-
Figure 70. Resistor Scaling with Log Adjustment Characteristics
068
68. Reduce Resistance by Half with Linear Adjustment Characteristics Figure
AD5260/AD5262
Rev. A | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0619
08-A
8°0°
4.504.404.30
14 8
71
6.40BSC
PIN 1
5.105.004.90
0.65 BSC
0.150.05 0.30
0.19
1.20MAX
1.051.000.80
0.200.09 0.75
0.600.45
COPLANARITY0.10
SEATINGPLANE
Figure 71. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14) Dimensions shown in millimeters
16 9
81
PIN 1
SEATINGPLANE
8°0°
4.504.404.30
6.40BSC
5.105.004.90
0.65BSC
0.150.05
1.20MAX
0.200.09 0.75
0.600.45
0.300.19
COPLANARITY0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 72. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16) Dimensions shown in millimeters
AD5260/AD5262
Rev. A | Page 24 of 24
ORDERING GUIDE Model1 RAB (kΩ) Temperature Package Description Package Option No. of Parts per Container AD5260BRUZ20 20 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ20-RL7 20 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5260BRUZ50 50 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ50-REEL7 50 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5260BRUZ200 200 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ200-RL7 200 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5262BRU20 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU20-REEL7 20 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRU50 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU50-REEL7 50 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRU200 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU200-REEL7 200 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ20 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ20-RL7 20 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ50 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ50-RL7 50 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ200 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ200-RL7 200 −40°C to +85°C 16-Lead TSSOP RU-16 1000 EVAL-AD5262EBZ Evaluation Board 1 Z = RoHS Compliant Part.
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02695-0-8/10(A)
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