an 81gb/s, 1.2v tialaan 81gb/s, 1.2v tiala--retimer in
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An 81Gb/s, 1.2V TIALAAn 81Gb/s, 1.2V TIALA--Retimer in Retimer in St d d 65 CMOS T h lSt d d 65 CMOS T h lStandard 65nm CMOS TechnologyStandard 65nm CMOS Technology
Shahriar Shahramian1
Anthony Chan Carusone1
Peter Schvan2Peter SchvanSorin P. Voinigescu1
1 University of Toronto, 2 Nortel Networksy ,
University of Toronto 1
MotivationMotivation
Emerging nanoscale CMOS with fT and fMAX beyond 200GHz
Low voltage operation and high levels of integrationLow voltage operation and high levels of integration
Wireline, serial 110Gb/s applications in a single chip solution
High speed retimersg p
Wireline transceivers, equalizers, ADCs and CML memory
Static frequency dividers up to 100GHz in 65nm SOI CMOS
Retimer speeds lag behind SiGe and InP technologies
University of Toronto 2
Goal and Design MethodologyGoal and Design Methodology
Demonstrate a record speed TIALA-retimer in a standard 65nm GPLP process
Low-voltage nanoscale CMOS topologies
Optimally sizing and biasing devicesy g g
Optimized circuit cell layout
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TIALATIALA--Retimer Block DiagramRetimer Block Diagram
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TIALA FrontTIALA Front--endend
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TIALA SchematicsTIALA Schematics
CMOS TIA 4‐stage pseudo differential LA
Low-noise, broadband front-end
C bi ti f SVT & HVT d i
g p
Combination of SVT & HVT devices
TIA: 7dB gain and 3dB BW of 80GHz
TIALA: > 20dB of gain and 45GHz BW
Overcome latch metastability
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Overcome latch metastability
SingleSingle--ended to Differential Conversion ended to Differential Conversion
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Differential Buffers SchematicsDifferential Buffers Schematics
Single-ended to differential conversion
O t i f ll it hi dOperates in full switching mode
Series-shunt peaking between stages
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Clock DistributionClock Distribution
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Clock Distribution SchematicsClock Distribution Schematics1.2V 1.2V
150pH
1.2V
55pH 55pH 85pHOutA
25pH
0.8V2kΩ26x1.6µm
SVT150fF
26x0.8µmHVT
26x0.8µmHVTIB
OutB
Clkin 55fF
125pH
150Ω 450pH 450pH 150Ω
26x0.8µmSVT
4mA
IT = 8mA IT = 8mA
125pH
XFMR Input Tuned amplifier chain
Transformer for differential conversion
CMOS TIA
Transformer for differential conversion
CMOS TIA used in the 81GHz clock path
Tuned differential amplifier chain
> 6dB differential gain from 50G-85GHz
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FlipFlip--Flop (Retiming Block)Flop (Retiming Block)
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FlipFlip--Flop SchematicsFlop Schematics
Combination of HVT & LVT devicesCombination of HVT & LVT devices
No current sources are used
Operation from a 1.2V supply
Layout is critical for 81Gb/s operation
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TIALATIALA--Retimer Signal FlowRetimer Signal Flow
V400m
V
n 50
Ω
400m
V I n
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Layout ConsiderationsLayout Considerations
Layout optimized by interdigitating and merging transistors with common sources or drains in a single wellcommon sources or drains in a single well
Latch example:
OutA OutB
InA
1.6µ
B µ ClkA
InB
0.8µ
ClkB
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Chip MicrographChip MicrographDC and Biasing
Output DriverFlip‐flop
DC and Biasing
iff i l i ionInpu
t Outpu
TIALA Differential pairs
Clock
distribu
t i
ut
ClockStandard 65nm GPLP CMOS process
Measure fT and fMAX of an 80x1um x 60nm n-MOSFET is 170GHz and 250GHz respectively measured at VDS = 0.6V
Chip area is 0.56mm x 1.2mm including pads
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p g p
SS--Parameter Measurement ResultsParameter Measurement Results
10
‐5
‐15
‐10
B)
‐20
15
meters (dB
‐25S‐Param
‐30
TIA Measured SP Return LossTIA Simulated SP Return LossDRV Measured SP Return LossDRV Simulated SP Return Loss
‐35
0 20 40 60 80 100Frequency (GHz)
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Frequency (GHz)
SS--Parameter Measurement ResultsParameter Measurement Results
‐5
0
‐10
5
B)
‐15
meters (dB
‐25
‐20
S‐Param
‐30CLK Measured SP Return LossCLK Simulated SP Return Loss
‐35
0 20 40 60 80 100Frequency (GHz)
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Frequency (GHz)
Transient Test Setup Block DiagramTransient Test Setup Block Diagram
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Transient Test Setup PhotographTransient Test Setup Photograph
Channel(24 i h 50G C bl )
81Gb/s TIALA‐Retimer
(24‐inch 50G Cable)
81Gb/s (27 1) PRBS81Gb/s (27 – 1) PRBS Transmitter
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Measurement Results: 75Gb/sMeasurement Results: 75Gb/s
τJRMS ≈ 2.5ps≈5mV
Inpu
t τJRMS 2.5ps
≈315mVput τJRMS ≈ 380fs
≈315mV
Outp
Input eye amplitude is 40mVpp single-ended
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Input eye amplitude is 40mVpp, single ended
Pattern Verification: 75Gb/sPattern Verification: 75Gb/s
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Measurement Results: 78Gb/sMeasurement Results: 78Gb/s
τJRMS ≈ 1.0ps
Inpu
t JRMS p≈12mV
put τJRMS ≈ 370fs
Outp
Input eye amplitude is 60mVpp single-ended
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Input eye amplitude is 60mVpp, single ended
Measurement Results: 81Gb/sMeasurement Results: 81Gb/s
τJRMS ≈ 1.1ps
Inpu
t
≈15mVτJRMS 1.1ps
put
≈320mVτJRMS ≈ 380fs
Outp ≈320mV
Input eye amplitude is 80mVpp single-ended
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Input eye amplitude is 80mVpp, single ended
Pattern Verification: 81Gb/sPattern Verification: 81Gb/s
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Table of ComparisonTable of Comparison
Ref Technology Rate Supply P PRef. Technology Rate (Gb/s)
Supply (V)
PLATCH (mW)
PTotal (mW)
[2] InP HEMT 80 -5.7 N/A 1200[ ]fT = 245GHz
[3] SiGe BiCMOSfT = 150GHz
48 2.5 23 288
[4] 90nm CMOS ProcessfT = 120GHz
40 1.2 10.8 130
This 65nm GPLP CMOS Process 81 1.2 9.6 200Work fT = 170GHz
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ConclusionsConclusionsFastest TIALA-retimer in any technology, operating at 81Gb/s
Latch power consumption is 9 6mWLatch power consumption is 9.6mW
TIA FoM is 118.5µW/Gb/s in differential operation
Combination of LVT, SVT and HVT CMOS from 1.2V supply
Low voltage CMOS nanoscale topologies
Optimized transistor layouts and compact latch layoutOptimized transistor layouts and compact latch layout
Combining low-noise, broadband CMOS TIA and high gain LA
Optimized transistor sizing and biasing
Series-shunt peaking techniques
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p g q
AcknowledgmentsAcknowledgments
We wish to acknowledge Nortel for funding and chip fabrication
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Backup SlidesBackup Slidesac up S desac up S des
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Simulated Clock Tree (SingleSimulated Clock Tree (Single--ended)ended)
5
10
0
5
(dB)
‐5
d AC Gain
‐15
‐10
Simulated
‐20 XFMR AC Gain Clock Tree AC Gain
‐25
35 45 55 65 75 85 95Frequency (GHz)
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Frequency (GHz)
Simulated TIALA AC ResponseSimulated TIALA AC Response
20
25
15
20
(dB)
10
d AC Gain
0
5
Simulated
TIA AC Gain
LA1 AC Gain
‐5
LA2 AC Gain
LA3 AC Gain
LA4 AC Gain
‐10
0 20 40 60 80 100Frequency (GHz)
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Frequency (GHz)
Measurement Results: 81Gb/sMeasurement Results: 81Gb/s
τJRMS ≈ 750fs
Inpu
t τJRMS 750fs
put τJRMS ≈ 350fs
Outp
Input eye amplitude is ~ 300mVpp single-ended
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Input eye amplitude is 300mVpp, single ended
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