aoste aoste models and methods of analysis and optimization for systems with real-time and embedded...

AosteAosteAosteAosteModels and Methods of Analysis and Optimization Models and Methods of Analysis and Optimization

for Systems with Real-time and Embedded for Systems with Real-time and Embedded Constraints Constraints

reated July 2004

2

Robert de SimoneRobert de Simone DR INRIA SophiaDR INRIA Sophia

(Head)

Yves SorelYves Sorel DR INRIA RocquencourtDR INRIA Rocquencourt

(Vice-Head)

Charles AndréCharles André Prof UNSAProf UNSA

Frédéric Mallet

MdC UNSA

Dumitru Potop

CR INRIA Rocq.

Marie-Agnès Peraldi-Frati

MdC UNSA

AostAostee

AostAostee

3

Research domain: Embedded SystemsApplication domains: mobile phones and consumer electronics, automotive/avionics/transportation,mobile robotics…

• Heterogeneous applications– pipelined complex data/signal flow streaming computations– control flow modes and interfaces, protocols

• Heterogeneous execution platform architectures– reconfigurable, flexible HW– systems-on-Chip, Networks-on-Chip, Multicore processors

• Complex design flow – need to allocate application onto architectures– need to optimize resources– satisfying real-time contraints (from different sources)

Formal models to represent applications and architectures, and their optimized implementation

4

TI OMAP

Applications can be dispatched to the ARM11 general-purpose processor (GPP), or theTMS320 DSP, or a mix of both

5

AutoSar

6

Example: Cell quadruple Ring

copyright 2005 S. Tota and L. Casu

7

General Scope

Large current trend: provide « software models » (programs) to simulate the execution platform with the application

Our answer (with others): true Models of Computation (with semantics), leading

from Concurrency Theory to Concurrency practice … Includes optimized compilation mapping, involving

– Spatial distribution – Temporal scheduling

To remain efficient and realistic, we stick to our former domains of expertise

8

Concurrency TheoryConcurrency Theory

Models of Computation and Communication (MoCC)Models of Computation and Communication (MoCC)

Scheduling TheoryScheduling Theory

Model-Driven engineeringModel-Driven engineering

Goal/Need: associate 3 domains

9

Our approach• Start with untimed/asynchronous (or loosely timed)

modeling (events partially ordered)

• Scheduling (dependence, period, preemption, cycle allocation decisions, pipelining, etc) seen as a

Time refinement leading to provable or correct-by-construction discrete logical-time specifications

• With this, solve and fix resource dimensioning (sequencers, memories, surface, buffers for latencies and delays) and cycle allocations

Semantic correctness preservation ?

10

Synchronous formalismsSynchronous formalisms

Esterel + extensionsEsterel + extensions (Verification/Compilation)

Platform-based designPlatform-based design AAA/SynDExAAA/SynDEx

(Optimization/Scheduling)

High-Level modelingHigh-Level modeling Real-Time UML/SyncCharts Real-Time UML/SyncCharts

(Modeling/Analysis)

Starting Point…

Common grounds: Common grounds: Mathematical semantics for Mathematical semantics for formal methods and modelsformal methods and models

11

Platform-based design

Comm & Control Data Computation

Application sideApplication side

Architectural sideArchitectural side

Allocations (operations to resources)

«Meet-in-the-middle»«Meet-in-the-middle»

Esterel, SyncCharts

SCADE/Lustre, Signal, Scicos

HW/SW platform model

SynDEx

Formal models Model-Based DesignModel-Based Design

System-Level DesignSystem-Level Design

Platform-Based DesignPlatform-Based Design

12

Industrial examples: SCADE/SSM

copyright © Esterel-technologies

SyncCharts inside

13

MBDA industrial example: SynDEx

14

Current research topics:

1. High-level modeling• Time modeling

scientific focus available

• Execution platform and Allocation modeling Inspired from SysML and other sources

• Models of Computation (MoCs) « Towards a Synchronous UML profile? », STTT Journal 2006

« MARTE… », UML for SoC design (DAC workshop), 2005 (RS, CA, Mehmood) starting PhD

• Model-driven Engineering Translations towards Models and Tools

« From UML to Petri Nets… », IES 2006

« MARTE to SynDEx » , « from TLM to RTL »

OMG MARTE profile standardization

15

Teaser: Examples of ClockConstraint

crkClk

camClk

1 2

1

3

32

4 5 6(0.5) (1.0) (1.5) (2.0) (2.5)(0.0)

(0.0) (0.5) (1.0)

Coincidence relation

Instant values(° CRK)

Instant values(° CAM)

<<clockConstraint>>{ camClk = crkClk filteredBy 0b(10) }

currentTime( ): Real

resolution: Real {readOnly}

<<clockType>>{ nature = discrete, unitType = TimeUnitKind,resolAttr=resolution, getTime = currentTime }

Chronometric

resolution = 0.01

<<clock>>{ unit = s, standard = UTC }

cc1:Chronometric

resolution = 0.01

<<clock>>{ unit = s, standard = UTC }

cc2:Chronometric

<<clockConstraint>> { kind = required }{ Clock c is idealClk discretizedBy 0.001; cc1 isPeriodicOn c withPeriod 10; cc2 isPeriodicOn c withPeriod 10; cc1 hasStability = 1E-5; cc2 hasStability = 1E-5; cc1,cc2 haveOffset in [0..5] ms on idealClk;}

<<clock>>{ unit = s }

idealClk:IdealClock currentTime( ): Real

<<clockType>>{ nature = dense, unitType = TimeUnitKind,

getTime = currentTime }IdealClock

Imported from MARTE::TimeLibrary

<<timeDomain>>ApplicationTimeDomain

16

Current research topics:

2. Synchronous and GALS formalisms

• Esterel and foundations « The synchronous hypothesis and synchronous languages »,

Embedded Systems Handbook. CRC Press, 2005. « L’approche Synchrone… », Encyclopédie de l’Informatique, Vuibert, 2006 « The Esterel language », Dumitru Potop et al Kluwer ed., in press Olivier Tardieu’s PhD thesis on intermediate models for compilation

• Latency-Insensitive and multiclock design scientific focus available

« Static scheduling of LID systems », EURASIP J. Embedded Systems

CIM PACA Sys2RTL collaborative project

• Endochrony and code distribution « Concurrency in Synchronous systems », FMSD 2006

• Compositional model-checking « Syntax-driven optimizations for Reachable State Space of Esterel programs ».

CAV 2005

17

Teaser: Latency-Insensitive Design in a nutshell

• Hardware implementation of Timed Event Graphs with capacity-2 marked places

• In purple, Shell Wrappers provide clock-gating for firing rule

• In red/green, Relay-stations provide a regular register and an emergency one to accept an extra token when traffic stalled ahead

18

Current research topics:

3. Real-Time distribution and scheduling• Real-time scheduling with multiple constraints

precedences, periods, and latencies in Annals of Operations Research 2006 non-preemptive & preemptive RM with cost of preemption in ECRTS Conf. 2007

scientific focus available

• Multiprocessor real-time scheduling (same constraints) distribution and scheduling: NP-hard problems optimizations: time (latency, period), resources (processors, memory), heuristics inspired from monoprocessor scheduling multiprocessor

scheduling with precedence periodicity and latency constraints in PMS Conf. 2006

• Generation of distributed real-time code macro-processing: architecture independent in MEMOCODE Conf. 2003

• Hardware/software codesign in journal of Supercomputing 2004

• Timed Event-graph based cyclic scheduling

19

TEASER: AOSTE real-time model

Cij = Ci

Cij+1

= Ci + 2α

Ti Ti

sij si

j+10

Operation i

sij: Start time of the jth instance

Ti: Period of the taskCi: Worst Case Execution Time (WCET): cost of the preemption not approximatedα: Cost of one preemption for a given processor

t

… …

A

B

C

D B cannot start its execution before A is completedB cannot preempt ATA < TB

sDj + - sA

j < LADLAD

20

TEASER: Scheduling

• Necessary and sufficient schedulability condition taking into account the exact cost of preemption

– for rate monotonic analysis (RMA)

– for systems with precedence and harmonic periodicity constraints

• Corresponding scheduling algorithms

21

Non-permanent staff• PhD students (6 on the average)

Julien Boucaron [ STM contract, from oct. 2004]

Jean-Vivien Millo [ BDE CIM PACA with STM, from oct. 2005]

Fabrice Peix [ MENESR, until september 2004 ]

Olivier Tardieu [ Corps des Mines, until november 2004 ]

Eric Vecchié [ PACA regional scholarship, until october 2004 ]

François Lagarde [ co-directed with CEA-List, from nov. 2005 ]

Amir Mehmood [Pakistanese Gov. fellowship, from oct. 2006]

Patrick Meumeu Yomsi [ INRIA fellowship, from dec. 2005 ]

Omar Kermia [INRIA fellowship, from jan. 2006 ]

Nicolas Pernet [ INRIA fellowship, until july 2006]

Mickaël Raulet [ co-directed with INSA/Mitsubishi-Electric, until may 2006 ]

Liliana Cucu [ INRIA fellowship, until may 2004 ]

Hamoudi Kalla [ INRIA fellowship, until dec. 2004 ]

Linda Kahouane [ co-directed with ESiEE, until dec. 2004 ]

• Senior collaboratorsGérard Cristau [Thales, Invited Specialist, oct. 2005-oct 2006 ]

Alix Munier [ U. Paris 6, délégation, oct 2004-sept.2006 ]

• Temporary engineers+ 6 human-years on contracts (3 Rocq, 3 Sophia)

+ 1 soft development engineer (SynDEx) at INRIA Rocq.

22

Publications (since 2004)• 1 book• 2 book chapters• 8 PhD thesis defenses

• 9 international Journal papers+ 2 national, + 5 others (Electronic Notes, …)

• 12 international conferences+ 7 international workshops+ 4 national workshops

23

CIM PACACIM PACA design platform design platform

EsterelEsterel (EDA vendors)

SynDEx usersSynDEx users (INRIA distribution)

OMG MARTEOMG MARTE UML profile UML profile PROTES CARROLL, System@ticPROTES CARROLL, System@tic

(UML tool editors)

Technology transfers and contracts…

24

Softwares• SynDEx V6 (in O-Caml)

– Growing user community– Interfaced with Polychrony, UML/MARTE/Eclipse/TopCased – The 3S Package: Scilab/Scicos/SynDEx – Optimized distribution & scheduling and distributed code

production

• MARTE profile implementation (XMI files)– Runs with Eclipse and proprietary tools (IBM RSA,

MagicDraw, Artisan)

• Esterel/SyncCharts contributions– Fast C prototype, rewritten at Esterel Tech.

• Kpassa tool– K-periodic scheduling of Timed Event Graphs and LID

25

Contractual CollaborationsCARROLL PROTES/CORTESS

Thales, CEA List, 3 INRIA teamsRNTL OpenEmbeDD Platform

Thales, FT, Airbus, CS, 5 INRIA teams, VERIMAG, LAAS

RNTL MemVatexSiemens VDO, Embelec, CEA List, UTC

System@tic OpenDevFactoryThales, FT, Airbus, CS, 5 INRIA teams, VERIMAG, LAAS

AAA/SynDEx users: MBDA, Mitsubishi-Electric, RobotSoft, PSA, IFP, …

CIM PACA Sys2RTL project in Design Platfom STM, TI, NXP, EsterelTech, Synopsys, ENST, LEAT

ST Micro ForComentTexas Instruments GrantINRIA HIDES associated team (with Columbia U.)

6th IST NoE ARTIST2

26

Main collaborations• Other INRIA teams

– Espresso (synchronous languages)– DaRT (Model-driven engineering for RT/E)– TRIO (RT scheduling)– Pop-Art (fault tolerance)– Metalau (Scilab/Scicos/SynDEx)– Vasy, Alchemy/Proval, S4, Mascotte, …

• CEA-List (OMG)• LIP6 (Operations Research, SoC design)• ESIEE (Codesign)• Columbia University, Karlsruhe U.

• Esterel community (Synchron, SLAP)+ Esterel Technologies

• Organizing IEEE/ACM MemoCode 2007

27

Teaching • Embedded System option of UNSA STIC Research

Master (strongly involved in creation)

• Research Master SETI Paris 11• Master1 EEA• Master2 Pro Info TIM• L3 Pro UNSA• Engineering schools (ESIEE, ENSTA, ISIA)

Various responsabilities• CIM PACA Scientific council and Design PF CA • Technical IEEE Esterel standardization Committee

28

Perspectives• Still at infancy, needs ROI2 (Return on Intellectual Investment),

mostly in prestigious publications• Once the framework installed, we need to focus on specific

research results (methodology is not the end of it)– Use time models and well-defined semantics in MDE

• Temporal operators, simulation = synthesis

• Integrated edition, transformation, analysis, backward traceability

– Semantics of MoCs• (periodically scheduled) combinations of Kahn PNs and SDF Event Graphs

• From TLM to RTL system-level in formal terms

– Real-time distributed scheduling• Multiple constraints (and multidimensional optimisations)

• Exact cost of preemption

Common belief expressed at DATE’07: scheduling is the main issue in embedded system-level design

29

Thank you !!Questions ?

Suggestions ?

More ?