atharav_resume

ATHARAV 516 Glenrock Avenue, Apt 111, Los Angeles, CA-90024 • 424-293-9395 • atharav@ucla.edu • /site/atharavresume • linkedin.com/in/atharav

EDUCATION

Master of Science, Electrical Engineering (Circuits Track) Spring 2015 University of California, Los Angeles(UCLA) [Continuing for PhD] Advisor: Prof. Behzad Razavi GPA:3.640/4.0 GPA: 3.625/4.0 Courses:EE215A, EE212A, EE215C, EE215B, EE215D, EE215E, EE230A, EE210A, EE209BS, EE209AS, EE210A, EE210B TA: EE115D(Prof.Razavi), EE115A(Prof.Razavi), EE164DA(Prof.Razavi) ,EE115E(Prof.Darabi)

Bachelor of Engineering, Electronics and Communication Engineering July 2012 Birla Institute of Technology and Science, Pilani, Rajasthan INDIA(BITS-Pilani) GPA: 4.0/4.0

INDUSTRY EXPERIENCE• 1.75yrs in Analog/Mixed Signal Circuit Design

Broadcom Ltd., Irvine, US Jun 2015–Sep 2015 •0.25yrs Design Intern, Wideband ADC Guide:Young Shin, Associate Design Director , Broadcom Ltd.

Understanding ENOB vs Sampling Rate Tradeoffs for Front-end samplers of 5Gbps,12-bit SAR-Pipelined ADC.

Designed 5Gbps,13-bit Front-End Samplers employing T-gate & Bootstrapped Switches. Silicon Labs Inc., Sunnyvale, USA Jun 2014 –Sep 2014 •0.25yrs Design Intern, APS Guide: Sid Dutta, Design Director, Silicon Labs Inc.

Designed Low-Power Switched-Capacitor Bandgap Reference with accuracy ±1% from -40°C to 125°C.

Behavioral Modelling of Impact of non-idealities on performance of Switched-Capacitor ΣΔ Modulator.

Implemented Low-Power Fixed-Frequency Ring Oscillator and Relaxation Oscillator. Redpine Signals Inc., Hyderabad, India July 2012 - July 2013 •1yr Analog Design Engineer Guide: Partha Murali, Manager and Architect, Redpine Signals Inc. SAR ADC for WLAN 802.11n

Designed 10-bit SAR ADC @ 80 MS/s with Split Capacitive DAC in tsmc 130nm LP technology.

Formulated MATLAB model and wrote Verilog testbench for Digitally Calibrating Split-CDAC to improve linearity of SAR ADC. Double Tail Dynamic Latch Comparator with Digital Offset Compensation

Developed double-tail dynamic latch comparator of internal offset 5mV in tsmc 40nm technology.

Implemented Digital offset Compensation to cancel the internal offset due to device mismatches. Time-Interleaved SAR ADC for WLAN 802.11ac

Designed 11-bit SAR ADC @ 160 MS/s with asynchronous architecture in tsmc 40nm LP technology.

Implemented novel concepts like asynchronous timing, set and down switching schemes and Time-Interleaved architecture.

Texas Instruments, Bangalore, India Jan 2012 - July 2012 •0.5yrs Engineering Intern Guide: Rishubh Khurana, Senior Analog Circuit Design Engineer, Texas Instruments COMPDAC System for Peak Current Control

Developed high speed, low resolution open-loop comparator to implement Peak Current mode Control (PCMC) technique.

Conceptualized 10-bit interpolating R-string DAC for integration with comparator in COMPDAC.

ACADEMIC PROJECTS

Wireless Temperature Sensor [Master’s Project] [Advisor: Prof. Behzad Razavi] Sept 2014-Jan 2014

Designed Wireless Temperature Monitoring System using Arduino Nano & Bluetooth HC-05.

Employing array of wireless temperature sensors to explore different piconet topologies.[Tools: Arduino] Pipelined ADC for WLAN 802.11n [UCLA EE 215D] [Advisor: Prof. Shervin Moloudi] May 2014-Jun 2014

Designed 10-bit, 80MS/s Pipelined ADC with INL/DNL < 1 LSB and 13.41mW Power Consumption in 45nm CMOS technology.

Employed 1.5 bit/stage MDAC architecture, 2-stage OPAMP 65db Gain-900MHz unity Gain Bandwidth, Strong-Arm Dynamic Latch Comparator, Bootstrapped switches. [Tools: MATLAB, Cadence ic6]

ADC Based Serial I/O Receivers [UCLA EE 215E] [Advisor: Prof. Sudhakar Pamarti] May 2014-Jun 2014

Analysed design trade-offs of specs like sampling rate, resolution, offset, noise and jitter in ADC-based Serial I/O Receivers.

Designed Continuous-Time Linear Equalizers, Comparators, Track and Hold Circuits and DFE for 10Gbps target date rate in ADC-based Receiver .[Tools: MATLAB, CPPSim, Cadence ic6]

2 GHz On-Chip Interconnect with Voltage-Mode Receivers [UCLA EE 215B] [Advisor: Prof.C.K.K Yang] Jan 2014 – Mar 2014

Designed Low-Swing Differential Interconnect with wire length 5mm and latency 1ns in 90nm technology.

Performed comparative study of conventional Interconnect, Low-swing Single-ended & Differential interconnect with Voltage-mode receivers to minimize FOM=Latency*Power*Width-cross section.[Tools: MATLAB, Cadence ic6]

Fractional Delay (FD) Filter [UCLA EE 212A] [Advisor: Prof .Sudhakar Pamarti] Nov 2013 - Dec 2013

Designed Fractional Delay filter with magnitude ripple 0.1 dB and group delay ripple 5% of fractional delay.

Employed Farrow structure with 9 parallel FIR sub filters to make FD Filter programmable for different fractional delays.

AWARDS/HONORS

Highest C.G.P.A in the ECE Department at Birla Institute of Technology & Science, Pilani-Hyderabad.

COMPUTER SKILLS

CAD Tools: Cadence Virtuoso, Calibre, Xilinx ISE, Electric VLSI Design Programming Languages: Verilog-A, Verilog, C, C++ Simulation Tools: Cadence Spectre, CPPSim, Eldo SPICE, BDA AFS, HSPICE, MATLAB