automated 3d integration - fosdem

Automated system partitioning based on

hypergraphs for 3D stacked integrated circuits

FOSDEM 2018 – Quentin Delhaye

Integrated circuits:Let’s go 3D

Building an Integrated Circuit (IC)

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Transistors to build gates

Building an Integrated Circuit (IC)

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Transistors to build gates

Gates to build logic functions

Building an Integrated Circuit (IC)

Transistors to build gates

Gates to build logic functions

Logic functions build ICs

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Building an Integrated Circuit (IC)

Gates to build logic functions

Logic functions build ICs

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Transistors to build gates

Building an Integrated Circuit (IC)

Gates to build logic functions

Logic functions build ICs

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System performance depends on transistor performance and the quality of the system interconnect

Transistors to build gates

What does a 2D IC look like?

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Planar 2D IC: only one transistor layer

Substrate

Gate

Metal

What are its limitations?

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Metal pitch

Gate pitch

Fin pitch

Standardcell

Metallayers

If you want more of them,you need them smaller.

But scaling has physical and financial limitations.

You can’t simply make it bigger

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Larger IC means lower yield

Good die

Bad die

Constant amount of defects per wafer

Split the IC to keep it small

Xilinx split its latest node to keep it relatively affordable.

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FPGA FPGA FPGA

FPIC FPIC FPIC

FPGA

What is a 3D IC?

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What is a 3D IC?

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What is a 3D IC?

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What is a 3D IC?

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Face-to-Back (past)

What is a 3D IC?

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Face-to-Face (present)Face-to-Back (past)

What is a 3D IC?

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Face-to-Face (present)Face-to-Back (past) Transistor-on-transistor(future)

What is a 3D IC?

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Face-to-Face (present)Face-to-Back (past) Transistor-on-transistor(future)

Somebody needs to decide what goes where

3D benefit: shorter connections

Increased performance

Decreased system power consumption

Improved area utilisation

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2D flow...

Hardware description: Verilog, VHDL, ...

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2D flow...

Synthesis: Yosys, ODIN-II, ABC, ...

Yields a netlist.

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2D flow...

Place and route (P&R): QRouter, Graywolf, FGR, ...

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... Extended to 3D

Pick which standard cell or module goes where

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This is not a design.

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Bipartition this system

Objectives:Area balance

Limit 3D interconnectivity

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Clustering: hide the shortest nets

Big clusters:

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Few nets Long nets hidden

Clustering: hide the shortest nets

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Small clusters: Lots of nets Long nets apparent

Graph extraction

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Clusters become vertices

Graph extraction

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Interconnections become edges

Graph extraction

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Extraction complete

Graph extraction

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Single nets are split into different edges

From graph to hypergraph

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Graph extraction

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Single nets are split into different edges

Graph extraction

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Hyperedges maintain their integrity

Hypergraph extraction

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Partitioning

Minimize the crossing nets and maintain area balance

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Split the netlist

Die 1

Die 2

module die1(); module die2();

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Replace the manual partitioning

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Automated 3D flow

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Automated 3D flow

• Export design properties• Design clustering• Export clusters connectivity

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Automated 3D flow

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• From the clustering outputs• Build hyperedges and merge identical ones• Compute graph weights• Format graph and call partitioning tool• Export cut data and partition directives

Automated 3D flow

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hMETIS

PaToH

Karypis Lab, University of Minesota

Ümit Catalyürek, Bilkent University

Automated 3D flow

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• Early development stage• Based on 2D netlist and partitioning directives

Designs tested

LDPC

RISC V (BoomCore)

OpenSparc T2: SPC, CCX and RTX

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3D: up to 77% less total wire length

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Experiments using different

functional blocks from

OpenSPARC T2 SoC

Different partitioning schemes

Different clustering options

3D: Up to 61% shorter critical path

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Experiments using different

functional blocks from

OpenSPARC T2 SoC

Different partitioning schemes

Different clustering options

Open questions

What is the best clustering?

Does the clustering method have a significant impact?

Can we predict the “partitionability” of a design?

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Links: https://fosdem.org/2018/schedule/event/cad_3d_asic/