backplane hsd meeting_may_8th_2012_sharable

Welcome for HSD Success in the Multigigabit/s Era

Dr. Hany Fahmy, Master High-Speed-Digital Application Expert

Agilent EEsof EDA

April 25th , 2012

High-Quality Assurance of Success

• EEsof rides the wave of HSD by wearing the shoes of the HSD

Designers

• Don’t provide “JUST-TOOLS” but Provide “DESIGN-WORKFLOW”

• Understands the “Pain” our Customers in designing Multigigabit

Technology

• Strive to Adapt the needs of our Customers through “Continuous

Improvement” of our Design-Flow

May 8, 2012

Confidentiality Label

Design and Analysis of ATCA 14-Slot Dual

Star 10G ETHERNET Backplane

10GBps per lane (10x10 100GBps)

Towards 25GBps per lane (4x25 100GBps)

May 8, 2012

Agenda

08.05.2012 4

1) Simulation Setup for the Blade

2) I/O driver Setup

3) Blade-2-Blade Investigation

5) Blade-2-Backplane-2-Blade Investigation

6) Backplane Via Structure Sensitivity Analysis and Optimization

7) Conclusion

4) Simulation Setup for the Backplane

Simulation Environment: Blade

Lanes routed TOP-2-Bottom &

TOP-2-Inner

08.05.2012 5

TOP-2-Bottom routing channel

TOP-2-Inner (L10/L12) routing channel

Building blocks of the Blade

IC Package: coupled model w BGA Balls

08.05.2012

Stackup Parameters for the Blade

May 8, 2012

2.4 mm ± 10 %

Num.Name

Thickness

Dielectric

Constant

--- 0.7 4.2

1 TOP Plated Copper Foil 1.6

Prepreg 2.8 4.1

2 L2_GND Copper foil 0.6

Core 4 4

3 L3 Copper foil 0.6

Prepreg 10 4.3

Core 4 4

Prepreg 10 4.3

6 L6_PWR Copper foil 1.2

Core 4 4

※ Prepreg 10 4.3

Core 4 4

9 L9_PWR/GND Copper foil 1.2

Prepreg 10 4.3

Core 4 4

Prepreg 10 4.3

Core 4 4

Prepreg 2.8 4.1

14 BOT Plated Copper Foil 1.6

--- 0.7

93.8 (

2.383 (

Board Thickness (mil)

Total Thickness (mil)

Total Thickness (mm)

SolderMask ---

0.5 oz

Prepreg

0.5 oz

SolderMask ---

PCB Thickness:

Material

RD name: Sam Cheng #1254

Manufacturer: 博智

Model Name: MIC-5332

請板廠依實際

需要微調各疊

層厚度

STUDYING THE TARGET

IMPEDANCE ROUTING OF THE

May 8, 2012

BACKPLANE DESIGN WORKFLOW

STACKUP DEVELOPMENT

May 8, 2012

STACKUP

DEVELOPMENT

PCB MATERIAL

PROPERTIES

2D MOM

IMPEDANCE

TARGET?

Realizing the Stackup in Multi-layer Library in ADS

May 8, 2012

Deck: Impedance_compliance_tests-1

Impedance Analysis

Top Layer Routing on Blade (IC-2-Cap)

4.5/5/4.5 75 Ω (85 Ω – 12%)

08.05.2012 11

08.05.2012 12

Impedance Analysis

Top Layer Routing on Blade (IC-2-Cap)

3.5/10/3.5 90 Ω (100 Ω – 10%)

08.05.2012 12

Impedance Analysis

Inner Layer Routing on Blade (Cap-2-ZD Conn)

7/5/7 75 Ω (85 Ω – 12%)

08.05.2012 13

08.05.2012 14

Impedance Analysis

Inner Layer Routing on Blade (Cap-2-ZD Conn)

5.5/10/5.5 90 Ω (100 Ω – 10%)

08.05.2012 14

Blade Routing (Top-2-Inner Layer 10)

May 8, 2012

Deck: Blade_TOP_2_INNER_FINAL

08.05.2012 16

IC-pad:

21-mils

Mismatch-

TL: 50-mils

Mismatch-

TL: 50-mils

Cap-pads: 28-mils IC-2-Cap-TL:

265-mils

Cap-2-Inner Layer (L10) 3D-Via-Model

08.05.2012 17

Expanded

Inner-VIEW

BLADE-VIA Diff-S-CHARACTERISTICS

May 8, 2012

Good IL/RL up to 10GHz with

worst IL of ~ -2dB

TDR Analysis of the Blade-VIA

May 8, 2012

The Via drops down the impedance to 82-ohms by 18-ohms

DEMO FOR THE BLADE-VIA MODELING IN MOM

May 8, 2012

Bottom layer or Inner-layer routing

08.05.2012 21

Cap-2-ZD Connector-pad TL

Bottom or Inner layers: 1250-

Break-in connector-pad: 975-mils

Mismatch-TL: 50-mils

Bottom-2-Top or

Inner-2-Top ZD Connector PIN-FIELD

08.05.2012 22

BOTTOM-2-TOP VIA FOR

CONNECTOR

INNER-2-TOP VIA FOR

CONNECTOR

DEMO FOR THE BLADE DECK CONSTRUCTION

May 8, 2012

Agenda

08.05.2012 24

2) I/O driver Setup

7) Conclusion

I/O driver Setup

08.05.2012 25

Target Rate is 6.25GB/s

Rise-time=30ps & 20ps

Ron 100-ohms & 90-ohms

De-Emphasis is 5dB with

Tap-interval of 0.4 UI & 0.5 UI

Jitter = 0.01 UI

Test-load

Reference-eye @ 6.25GB/s

08.05.2012 26

Width = 150ps, height = 1V, Jitter P2P=8ps & Jitter RMS = 1.7ps

Agenda

08.05.2012 27

2) I/O driver Setup

7) Conclusion

Blade-2-Blade without Via Transitions

08.05.2012 28

2.5” 2.5”

Blade-2-Blade without # 3 & 9

without connector &

without Backplane

Simulation Results

Blade-2-Blade @ 6.25Gb/s (inner 85 Ω-12%) no Vias

De-Emphasis Tap-Interval = 0.5 UI, Ron=100-ohms

08.05.2012 29

Width = 132ps, height = 521mV, Jitter P2P=27ps & Jitter RMS = 5.3ps

Width = 150ps, height = 1V,

Jitter P2P=8ps & Jitter RMS = 1.6ps

Blade-2-Blade with Via Transitions

08.05.2012 30

2.5” 2.5”

Blade-2-Blade with # 3 & 9

without connector &

without Backplane

Simulation Results

Blade-2-Blade @ 6.25GB/s (inner 85 Ω-12%) WITH Vias

08.05.2012 31

Impact of Blade-Vias

08.05.2012

EKH - EyeKnowHow

VIAs: Width = 100ps, height = 282mV, Jitter P2P=56ps & Jitter RMS = 11.7ps

NO-VIAS: Width = 132ps, height = 521mV, Jitter P2P=27ps & Jitter RMS = 5.3ps

VIAS IMPACT

Blade-2-Blade without Via Transitions

08.05.2012 33

2.5” 2.5”

Blade-2-Blade without # 3 & 9

without connector &

without Backplane

Simulation Results

Blade-2-Blade @ 6.25Gb/s (inner 100 Ω-10%)

08.05.2012 34

Width = 135ps, height = 740mV, Jitter P2P=25ps & Jitter RMS = 5ps

Compare (85Ω-12%) to (100Ω-10%)

WITHOUT THE BLADE VIAS

08.05.2012 35

521mV to 740mV

132ps to 135ps

27ps to 25ps

85W TO 100W

Blade-2-Blade with Via Transitions

08.05.2012 36

2.5” 2.5”

Blade-2-Blade with # 3 & 9

without connector &

without Backplane

Simulation Results

Blade-2-Blade @ 6.25GB/s (inner 100 Ω-10%)

08.05.2012 37

Compare (85Ω-12%) to (100Ω-10%)

WITH THE BLADE VIAS

08.05.2012 38

Eye-heigth:280mV to 516mV

Eye-width: 100ps to 125ps

Jitter-PP: 56ps to 32ps

85W TO 100W

Recommendations for Blade Routing

Target impedance of 100-ohms is better than 85-ohms:

• Width increase by ~ 25ps

• Height increase by 240mV

• Jitter PP reduces by ~ 25ps

Via Transition Modeling is VERY CRITICAL

08.05.2012 39

Recommendations for Blade Routing, Contd.

Via Structure should be optimized

• To target impedance (minimum impedance drop for TDR analysis)

• And include Backdrillling

AC Coupling caps should be optimized (e. g. cutout underneath

for better impedance matching)

Avoid routing near cutouts at connector pin field region

08.05.2012 40

Agenda

08.05.2012 41

2) I/O driver Setup

7) Conclusion

Backplane Routing

Longest Stub: Layer-3 w

Length=9685-mils

08.05.2012 42

Backplane Routing

3D Via modeling

08.05.2012 43

Backplane Routing

layer 3 routing

08.05.2012 44

Stackup of the Backplane with Material Properties

Core & Pre-preg are 8-mils

Dk = 3.8 @ 10GHz

Loss-Tan = 0.008 @ 10GHz

OPTIMIZATION OF THE VIA-BP

08.05.2012

Signal-Launch 6-mils away from the ref-GND plane

08.05.2012 47

Signal-Launch 6-mils

away from ref-GND

plane on Bottom

Via-BP structure without the Extra GND plane at

20-mils from top layer

08.05.2012 48

Diff IL response of the Via-BP without the extra

GND plane

08.05.2012

-9dB @ 10GHz

Adding Supplement-GND plane is also critical to

keep Diff-IL down @ 10GHz

08.05.2012 50

Adding Suppl-GND plane

helps @ 10GHz

Via-BP structure with the

Supplement-GND planes

08.05.2012 51

Diff IL response of the Via-BP with the Supplement

GND plane

08.05.2012

-5.5dB @ 10GHz

CURRENT DENSITY OF THE BP-VIA MOM MODEL

May 8, 2012

BP-CHANNEL PERFORMANCE

08.05.2012

Coupled Simulations of the BP channel

08.05.2012

BP-channel Perf Diff-IL

WITHOUT SUPL-GND Plane

08.05.2012

-26dB @ 10GHz

BP-channel Perf Diff-IL

WITH SUPL-GND Plane

08.05.2012

-20dB @ 10GHz

Do we still have 5/7/5 optimum routing

of BP-channel with Via-BP with

Supplement-GND plane?

08.05.2012

Sweeping width from 3.5-mils to 5.5-mils

Sweeping Spacing from 5-mils to 11-mils

DEMO BACKPLANE CHANNEL CONSTRUCTION

Deck: BP_Channel

May 8, 2012

Conclusion

5/7/5 routing is the optimum routing (sweeping over HVM)

Shifting the Stackup so that the signal-launch is 6-mils away

from the Bottom Ref-GND plane is critical to control the

impedance of the launch

Adding Supplement-GND plane away from the signal-Launch

by 10-mils improve the Via-BP by ~ 4dB and the whole BP-

channel by 6dB @ 10GHz.

08.05.2012 60

Agenda

08.05.2012 61

2) I/O driver Setup

7) Conclusion

Design Focus

• 3D Analysis of the Via-BP as Most-critical Element (minimized

impedance drop to 20-ohms)

• IL & RL Comparison of new-BP Design Compared to

measurements for old-BP

• TDR Analysis of the BP with Connector

• IEEE 802.3ba 2010 Compliance tests of the new BP

• Tx/Rx Equalization Optimization for successful operation at

6.25GBps & 10GBps

• Final Conclusion

Material Properties for FR408HR

08.05.2012

EKH - EyeKnowHow

New Stackup with New Material

Core & Pre-preg are 6-mils

Dk = 3.65 @ 10GHz

Loss-Tan = 0.0095 @ 10GHz

Impedance Compliance for the BP

5/7/5 routing (95-ohms Diff & 54 SE)

Disclaimer: recommend that PCB house build a test-coupon & TDR/TDT the

impedance of the test-sample along with S-parameter Data

How close MOM Estimate to Polar Estimate for

Impedance Calculation?

May 8, 2012

54.6 MOM vs. 52.3 Polar 97.6 MOM vs. 95.5 Polar

2-ohms difference in Estimate

VIA-BP DOMINATES THE

PERFORMANCE OF THE BP

Via-BP structure with the

Supplement-GND planes with FR408HR

Diff IL for the Via-BP up to 15GHz

Dip at ‘m2’ 14GHz

Diff RL for the Via-BP up to 15GHz

10GHz < Max reflection < 15GHz

What is the drop-down-Diff-impedance of the Via-

The via-BP drops the impedance down to 80-ohms

Approximately, it drops the impedance by 20-ohms

BP-Channel Response w/o CONN:

Longest Channel+ longest Stub

Diff IL with 5/7/5 routing

Comparison with measurements

“L13/14/15/16” compared to Simulated IL

(without the connector)

New BP design

without connector

measurements

Comparison with measurements

“L13/14/15/16” compared to Simulated IL

(with the connector)

+6dB Improvement at 10GHz for the new BP Design

compared to measurements

lity u

ts is o

TDR Analysis BP+Connector

Connector H/G-pins

~ 400ps delay

Via-BP

Down by 25-ohms

Measured TDR of the 6-slots BP

08.05.2012

EKH - EyeKnowHow

Almost 70-Ohms dip for

Megatron-6

COMPLIANCE TESTS OF BP

IEEE STANDARD 802.3BA 2010

Insertion Loss (dB)

2 4 6 8 10 12 14 16 180 20

freq, GHz

ax_upper

Measured IL

New-BP is better than old-

BP by +6dB @ 10GHz

Fitted Attenuation (dB)

2 4 6 8 10 12 14 16 180 20

freq, GHz

-9dB @ 6GHz

Measured Fitted Attenuation

08.05.2012

EKH - EyeKnowHow

New-BP is better

than old-BP by

+6dB @ 6GHz

Measured Fitted Attenuation, Contd.

08.05.2012

EKH - EyeKnowHow

New-BP is better

than old-BP by

+6dB @ 6GHz

Insertion Loss Deviation

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.51.0 6.0

freq, GHz

Measured ILD

Much better performance of the

new-BP for ILD

Return Loss (Magnitude)

1E91E8 1E10

freq, Hz

freq[idx_lower::idx_middle], Hz

freq[idx_upper::idx_fmax], Hz

in_upper

10GBASE-KR Return Loss Plots with Limit Lines

BACKPLANE DESIGN WORKFLOW

Meeting the IEEE 802.3ba Target

May 8, 2012

VIA PARAMETERS

PCB MATERIAL

PROPERTIES

& STACKUP

3D MOM

MET BP

COMPLIANCE?

BP TL ROUTING

2D MOM

MULTI-LAYER

LIBRARY

EYE-DIAGRAM CHANNEL

RESPONSE BLADE-BP-BLADE

BLADE IS WORST-CASE 85-W

Eye-Diagram @ 5GBps

Blade-BP-Blade

without Tx/Rx Equalization

Blade routing is worst-case of 85-W

Eye-Diagram @ 5GBps

Blade-BP-Blade

with Rx Equalization (FFE 2/4)

Eye-Diagram @ 6.25GBps

Blade-BP-Blade

with Rx Equalization (DFE 6-taps )

OPTIMIZATION OF DRIVER FIR

EQUALIZER SETTING AND

RECEIVER DFE SETTINGS @

6.25GBPS

Jitter PP Optimized setting:

Tx FIR pre-cursor = ‘3’, post=‘5’

Worst jitter

pp=30ps

Eye-width

Worst eye-

width = 130ps

Eye-height

Worst height

= 1.58V

eye-diagram with all FIR EQ settings

OPTIMIZATION OF TX FIR

EQUALIZATION SETTINGS FOR

10GBPS OPERATION

Jitter PP Min

FIR Setting: pre-cursor ‘1’ post ‘5’

97 Jitter 38ps

Eye-width maximization

98 Width is 62ps

Eye-height max

99 Height is 240mV

eye-diagram combined

Best FIR setting is

Pre-cursor ‘1’ & post ‘5’

DEMO SETTING THE TX FIR EQUALIZATION

PARAMETERS

May 8, 2012

Conclusion

• Via-BP was shown to dominate the performance of the BP especially > 5GBps (new-Via-BP causes ONLY 20-ohms to 25-ohms drop in impedance with TDR analysis)

• New Material + stackup + via-BP +6dB improvement in IL @ 10GHz for worst-BP-channel (longest with longest stub) passes all Compliance tests IEEE 802.3ba 2010

• Tx FIR & Rx DFE Equalization helps open the eye for higher data rates of 6.25GBps and above

• successful FIR settings of Tx & DFE settings of Rx was shown @ 6.25GBps & 10GBps

IBIS-AMI MODELING DISCUSSION

May 8, 2012

In Statistical Channel simulation mode, can we use

RX adaptive DFE in simulation and output DFE

For example, Broadcomm warplite_kr rx AMI

model, there is no Getwave function, but it include

DFE and there is no problem to run DFE channel

simulation. Altera S4/S5 AMI model, under

Statistical channel simulation, it is also OK to

include DFE model.

May 8, 2012

Two Kinds of Tx/Rx Plus

a “Hybrid”

Model’s Init_Returns_Impulse flag

False (“Can’t be

modeled as LTI”)

True (“LTI model

via impulse

response”)

Model’s

GetWave_Exists

flag is:

False (“Model is

pure LTI”)

Empty model: not

allowed

Typical case for

Tx and simple

Rx’s (fixed Eq.

and no CDR)

True (“NLTV

model via

waveform

modification”)

Typical case for

Rx (Adaptive Eq.,

Buyer beware:

LTI approximation

of NLTV device if

used in stat mode

Channel Simulator:

Statistical Mode

Tx model’s Init_Returns_Impulse

flag is:

False (“Tx

cannot be

modeled as

LTI”)

True (“Tx can be

modeled as LTI

AMI_Init()”)

Rx model’s

Init_Returns_Impulse

flag is:

False (“Rx

cannot be

modeled as LTI”)

True (“Rx can be

modeled as LTI

using AMI_Init()”)

“Case 1”

Channel Simulator:

Bit-by-bit mode

Tx model’s GetWave_Exists flag is:

False (“Tx has

no NLTV

character”)

True (“Tx

models NLTV by

modifying

waveform”)

Rx model’s

GetWave_Exists

flag is:

False (“Rx has

no NLTV

character”)

“Case 2” “Case 5”

(Practically never

True (“Rx

models NLTV by

modifying

waveform”)

“Case 3” (Most

common case)

“Case 4”

Five Cases

Mode Bit pattern? Tx Analog &

Channel

1 Statistical None: stochastic

properties of

infinite bit pattern

LTI LTI LTI

2 Bit-by-bit Any finite bit

pattern

LTI LTI* LTI

pattern

LTI LTI* NLTV

pattern

NLTV LTI* NLTV

pattern

NLTV LTI LTI

*ADS can handle NLTV mid-channel repeaters

using a proprietary extension

1. Analog and

channel impulse

response

2. “Smart” convolve

with Tx

3. “Smart” convolve

with Rx

Pre-Work for Thru Channel: All 5 Cases

Case 1: Statistical Mode

Tx and Rx modeled by their impulse responses

Eye pattern diagram (density, BER contours, bathtubs)

calculated directly from pre-work:

…using statistical methods that include jitter and crosstalk

handling

Case 3: Bit-by-bit Mode: Tx modeled by impulse

response, Rx modeled by waveform modification

1. Bit pattern:

2. Convolve with composite analog/channel/Tx impulse:

3. Modify waveform using Rx model algorithm:

4. Eye pattern diagram from Rx output waveform

• Details of jitter handling in next slide…

Two Methods of Handling Rx Jitter

1) When clock ticks are available:

bit-by-bit and clock ticks available from Rx

GetWave

…waveform segments between [tick, tick+UI]

are used to construct the eye to capture Rx

sample time jitter. Eye is centered at tick+UI/2.

2) When clock ticks are not available, Rx_Clock_PDF is convolved with

eye pattern diagram:

• Statistical mode

• Bit-by-bit mode but no clock ticks

tick 1

tick 2

tick 3 eye center @ tick+UI/2

backplane hsd meeting_may_8th_2012_sharable

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