basic organization. our progress covered level 0 ch 4: – preview level 2 – level 1

Basic Organization

Our Progress

• Covered level 0• Ch 4:

– Preview level 2– Level 1

CPU Basics

• Primary CPU structures : datapath and the control unit

– Datapath : arithmetic-logic unit and storage (registers/memory) interconnected by a data bus

CPU Basics

• Primary CPU structures : datapath and the control unit

– Control Unit : Selects andsequences active circuits.Hardware or software based.

Registers

• Registers hold data for rapid access– Register : immediate– Main memory : ~60ns / ~200 clock cycles

• Implemented using D flip-flops

• The control unit determines whichregisters active

ALU

• Arithmetic-logic unit (ALU)– Two input busses, one output bus– Control unit sends function select

Busses

• Bus : set of wire that simultaneously convey a set of related bits– Classify by

• Type : point-to-point vs multipoint• Width : parallel vs serial• Timing : synchronous vs asynchronous

Busses

• Bus connections

Point to Point: Multipoint:

Bus Arbitration

• Strategies for controlling who talks:• Distributed using self-

detection: Devices decide which gets the bus among themselves

• Distributed using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again

• Daisy chain:

Pass authorization from hi priority to low

• Centralized parallel: Each device is directly connected to an arbitration circuit

Busses

• Bus connections

Parallel: Serial:

Bus Organization

• Efficiency through special purpose sub-busses– Data – Address – Control

Busses

• Bus timing– Synchronous : Clock based

• Must avoid skew• Strict timing window

– Asynchronous : Handshake based• Protocol based communication

– I'm ready to talk– OK, I'm ready, send– Send data– Acknowledge data

Part B

Clock

Part A

Bus Length

• Electrical signals limited to about 1/2 speed of light:~15 cm/nanosecond

• Given 3 Gigahertz clock – 3 billion ticks per second– 0.33 ns/clock tick

– Signal only travels 5cm per clock tick

Clocks

• Different subsystems, different clocks

Pentium II i7

Clock

• Clock speed != performance– Just one factor

Clock Length(Inverse of speed)

Pentium Ivy Bridge

Clock

Speed of instructions

Clock

Expressive powerof instructions

Can I multiply in one instruction?

Can I add two whole arrays in one instruction?

Memory Organization

• Idealized memory vs reality

x

Memory Organization

• Memory size– Addresses x size of addressable unit– 512K x 8bits– 4 mega bits total data

512K = 512 * 1024 = 29 * 210

= 219

= 19 bit addresses

x

Other Memory

• Other ways to make 4 mega bits

– 4M x 1bit• 4M addresses = 22 bit address, word size 1 bit

– 256K x 16bits• 256K addresses = 18 bit address, word size 16 bits

– 128K x 32bits• 128K addresses = 17 bit address, word size 32 bits

RAM

• Ram "sticks" from chips• Main memory :

1+ sticks

Simple memory

• 8 chips, each with 4 addresses• 32 possible address

– Each number = address of byte

Simple memory

• 32 = 25 = 5 bit addresses

Simple memory

• 32 = 25 = 5 bit addresses

• 8 chips = 23 = 3 bits to pick chip• 4 address per chip = 22 = 2 bits for offest

Simple memory

Address Module Number

Byte on ModuleDec Binary

1 0 0 0 0 1 0 1

14 0 1 1 1 0 3 2

20 1 0 1 0 0 5 0

7 0 0 1 1 1 1 3

31 1 1 1 1 1 7 3

Simple memory

• High-Order Interleaving

• Low-Order Interleaving

Low-Order Address

High order bits now byte on module

Address Byte on Module

Module NumberDec Binary

1 0 0 0 0 1 0 1

14 0 1 1 1 0 1 6

20 1 0 1 0 0 2 4

Bigger Scale

• 2GBytes byte addressable memory made from 128M x 32 bit chips– How many chips?– What do addresses look like?

Bigger Scale

Each chip has word size 32, 128M addresses:= 128M x 32 bits= 128M x 4 bytes = 512MB

Total : 2GB = 21 * 230 = 231

Per Chip : 512MB = 29 * 220 = 229

231 / 229 = 22 = 4

Four 128M x 32 chips for 2GB byte addressable

Bigger Scale

Addresses:– 2GBytes = 21 * 230 = 231 total addresses

31 bits

– Each chip:512MBytes = 29 * 220 = 229 addresses29 bits

– Chip select:4 chips = 22 2 bits

Bigger Scale

• 31 bit address– 2 bit chip select – 29 bits for offset on chip

Chip ByteBits 30-29 Bits 28-0

2 4 Decoder 29 512M Decoder