btev front end readout links - €¦ · front-end readout architecture analog de tector sign al...
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B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 1
BTeV Front End Readout&
Links
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 2
BTeV Front End Systems Summary
System Channels FEBs FEB Components
Muon 69120 32ch overthreshold ASDQs, DACs, ADCs
RICH 349146 163ch overthreshold IDE, DACs, ADCs
EM Cal 23712 32ch @ 11 bits each QIE, FADC, DACs, ADCs
Straws 118464 32ch @ 6 bits each ADSQs, TDCs, DACs, ADCs
Pixel
Strips
Six BTeV detector sub systems:
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 3
Front-End Readout Architecture
Ana
log
Det
ecto
r Sig
nal
Front End Boards
Data Combiner
Board
Hi Speed SerialData Link to L1Buffer or Trigger
Control/Timing and Monitor
Link
Short Cable
• Front-End Boards (FEBs) digitize multiple analogdetector signals
• Data Combiner Boards sparsify, combine, and formatthe data into data blocks for each BXNG.
• Data blocks are sent via high speed serial link withBXNG time stamp.
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 4
Muon System Example
• Digitized detector data is overthreshold (ASDQ)
• Each FEB is 32 channels. 32 channels equals 1 plank.
• 69120 System Channels Total
• 2160 FEBs
• 13 FEBs for each DCB. 13 FEBs equals 1 octant.
• 167 DCBs
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 5
Muon System Example
32 ChannelAnalog FEBs
13 FEBs per Octant
416 Channel Data CombinerBoards (DCBs) connecing 13 FEBs
1 DCB Per Octant
Octant 0
Octant 1
Octant 2
BTeV Muon System Readout
Architecture
2Gbps OpticalData Link to TriggerSystem
Control/Timing andMonitor Links
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 6
Data Combiner Board (MuonDCB Shown)
PR
OM
8B/
10B
Enc
oder
Monitor TX
G bps Data T X
DC toDC
VXOX8
Plank 8
Plank 9Plank 10
Plank 11Plank 12
Serializer FPGAs
PR
OM
TMC FPGA2
Control & Clk RX
Plank 0Plank 1
Plank 2Plank 3
Plank 4
Pin-Diode andFiber Connectorfor Control Link.
2 Gbps VCSELand Fiber Connectorfor Data Link
80 Pin Connector
53MHz SystemClock RecoveryComponentsPower input
Level Translator
TestConnectors
Plank 5 Plank 7Plank 6
VCSEL and FiberConnector for Monitoring Link.
• System clock recovery
• Receive/decode controlcommands
• Combine/format data from 13FEBs (TMC2 FPGA)
• Return MonitoringData
• Different sizedboards for differentsystems
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 7
TMC2 FPGA
Timing, Controland
Monitoring
Data Combining
Da
ta F
orm
atti
ng
416 Channelsof FEB DataEvery BXNG
Formatted DataBlocks to High SpeedSeriali zer
Serialized MonitorData to Monitor Link
Serialized ControlData with 53Mhz SystemClock Embedded
Return Data from FEB Components
Contro l Data from FEB Components
TMC FPGA2Muon DCB
• TMC2 = Timing, Monitoring, Control, and Combining
• Different size and slightly different firmware for eachsystem
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 8
Optical Links
Muon DCB 8B/10B Encoder and serializer @ ~2Gbps
VCSEL and Fiber Connectorfor 2Gbps Data Link
VCSEL and Fiber Connectorfor Slow Speed Monitor Link
PIN Diode and Fiber Connectorfor Timing/Monitoring Link
• Optical links will be standard across all systems
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 9
Summary of Other Systems
• RICH: DCB combines 6 FEBs. Each FEB is 163 channels.
• Straws: DCB combines 8 FEBs. Each FEB is 32 channels.
• EM Calorimeter: DCB and FEB are combined into asingle board. Each DCB/FEB is 32 channels.
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 10
FEB/DCB Functional Summary
• Front End Boards (FEBs) digitize detector data every beamcrossing (132ns) and send all data to a Data CombinerBoard (DCB).
• DCBs connect multiple FEBs. They receive the digitizeddetector data, combine all data (sparsified) from the sameBXNG and send it as a data block to the L1 Buffer (ortrigger) via a 2Gbps optical serial link.
• DCBs receive timing and control commands from acontrol/timing link, control FEB components, and returnmonitoring information back to the BTeV Timing/Controland Monitoring System.
B. Hall 17 Aug 2000 BTeV Front End Readout & Links Page 11
Key Advantages
• Greatly reduce cable mass by combining data frommany detector channels close to the detector into asingle high speed optical data link.
• Architecture allows for “simple” FEBs resulting inhigher reliability in difficult to access areas.
• Standard optical components (data link,control/timing link, and monitoring link) allow forinterchangeable parts across systems and lessdevelopment/debug time.
• TMC2 FPGA is functionally similar across eachsystem allowing for common firmware resulting inless development/debug time.
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