cmos process flow. important modules in cmos flow isolation wells gate stack junctions interconnects...

CMOS Process Flow

Important modules in CMOS Flow

• Isolation

• Wells

• Gate Stack

• Junctions

• Interconnects

We use a variety of “unit processes” and put them togetherin an appropriate sequence for CMOS “process integration”

Chemical Cleaning• Silicon wafer must be cleaned at every step• RCA cleaning, invented in 1965, and its variants have been the basis of almost all the cleaning procedures today• All chemicals are CMOS grade, high purity• Water used is De-Ionized (DI) Water r > 18 M-ohm cm

I. Organic clean : 5:1:1 H2O:H2O2:NH4OH, @75oC for 10min

II. Oxide strip: 50:1 H2O:HF , @25oC for 1 min

III. Ionic clean : 6:1:1 H2O:H2O2:HCL, @75oC for 10min

IV. Oxide strip: 50:1 H2O:HF , @25oC for 1 min

V. DI water dump rinse & dry

Oxidation

Si + O2 SiO2

T > 800oC

Thermal Oxidation

Deal-Grove Model

Tox

t

tBAToxTox 2

B and B/A are parabolic and linear rate constants

f(Temperature, Pressure, Oxygen dilution, …)

Ion implantationAnalytical versus Monte-Carlo modeling

C(cm-3)

xUser defined parameter: Species, Dose, Energy, Tilt, RotationAnalytical: Gaussian, Skewed Gaussian, Pearson distributionsTable look-up in simulator

Monte-Carlo: Statistical simulation of random collision eventsEncountered by implanted species in Silicon substrateComputationally inefficient

B, As, P, In, Sb

DiffusionSolution of Diffusion Equation (Conservation of matter)

xCD

xkT

q

x

txCD

t

txC 2

2 ),(),(

D = Diffusivity = f(Temp,Background,Interstitials,Vacancy)

Ø = Potential

C = Concentration of diffusing impurity

Simulator should have accurate model for diffusivity D

Deposition classification

Physical Vapour Deposition Chemical Vapour Deposition

Sputtering

Evaporation

Mostly used for Metals

Low temperature processbut step coverage is not good

Oxide, Nitride, Poly-Silicon

LPCVD, APCVD

Plasma Enhanced (PECVD)is attractive for low thermal budget

Excellent step coverage can beachieved

LPCVD Oxide deposition

SiH4 + O2 SiO2 + H2

T ~ 400oCLTO:

TEOS:

Si(OC2H5)4 + O2 SiO2 + byproductsT ~ 700oC

User defined parameters: Process type, Temperature, Pressure,Concentration of reactants…

Model requirement: Deposition rate as a function ofconstituent variables

Nitride & Poly-Si deposition

3SiCl2H2 + 4NH3 Si3N4 + 6HCl + 6H2

SiH4 Si + H2

Nitride:

Poly-Si:

T~ 800oC

T~ 600oC

Model requirement: Predict deposition thickness, step coverage, resistivity (Poly-Si)

Poly-Si resistivity can be modulated in the range 106-10-3 ohm-cm

Etching classification

Wet Dry (Plasma)

Isotropic Anisotropic

User defined parameters: Type of etching, Concentration ofchemicals/gases, pressure, RF power…

Model requirement: Predict the etch rate, etch profile

Other constraint: Selectivity to etch stop material

Photolithography

Contact (1:1) and/or Projection (N:1) Printing, using UV lightthrough a chrome coated quartz/glass mask with opaque and transparent region, defining features in the design

Optics for projection

Photoresist : Light sensitive organic material

Projection litho is industry standard for CMOS

Si

Poly-Si

PhotolithographyPhotoresist (PR) : Organic, light sensitive film

Positive PR : Weakens when exposed to UV light and thengets etched away in developer solution

Negative PR : Hardens when exposed to UV light and thendoes not etch away in developer solution

Positive PR is the industry standard for CMOS, since it generally better well defined smaller features

UV source evolution : 1980s and early 1990s, Hg arc lamp436 nm (g line), 365 nm (i line)Late 1990s to present : Deep UV , excimer laser248 nm KrF, 193 nm ArF

Resolution enhancement techniques (computational nano-litho) : Phase shift litho (R=k1l/NA; phase of light)Immersion litho (R=k1l/n*sina ; air vs water, n=1 vs 1.44)Proximity correctionSub wavelength features for assisting

ISOLATION MODULE

• LOCal Oxidation of Silicon (LOCOS)• Shallow Trench Isolation

SiO2 is used to isolate two transistors

LOCOS Isolation~10nm Pad SiO2

Dry oxide

Si

~15nm Si3N4

LPCVD

Si

Active Litho, Dry etch

Si

~500nm Field SiO2

Wet oxide

Si

Strip nitride, oxideWet etch

Si Si

Scalability is an issuedue to Bird’s beak

Not suitable for < 250nm

Shallow Trench Isolation~10nm Pad SiO2

Dry oxide

Si

~15nm Si3N4

LPCVD

Si

Active Litho, Dry etch~350nm depth

Si

Si

Liner oxide (~10nm) HDPECVD trench fillTEOS chemistry

Si

Chemical MechanicalPolishing, HF dip,Nitride strip

Well Module

Requirements

Si

Prevent Deep Punch Through

Account for highfields at trench corner

Adjust Vt, bySCE control

USE CHAIN OF IMPLANTS

Well Implant Chain

Boron ~ 200 KeV, 1012 – 1013 /cm2

Boron ~100 KeV, 1012 – 1013 /cm2

Boron ~50 KeV, 1012 – 1013 /cm2

Boron ~ 15 KeV, 1012 – 1013 /cm2

Indium ~ 120 KeV, 1012 – 1013 /cm2

Phosphorus ~ 600 KeV, 1012 – 1013 /cm2

Phosphorus ~300 KeV, 1012 – 1013 /cm2

Phosphorus ~ 50 KeV, 1012 – 1013 /cm2

Phosphorus ~ 15 KeV, 1012 – 1013 /cm2

Antimony ~ 150 KeV, 1012 – 1013 /cm2

P-Well N-Well

Additional Well masks & Implants for Multiple Vt Technology

Gate Stack Module

• SiO2, Dual Polysilicon Gate

Drawn channel lengthLD

LMASK

Upsizing on reticle based on optical projection ratio

Printed channel length

Optics for projection

LMASK

LPRINT

LPRINT need not be equal to LD due to optical bias

(Poly) Gate length

LG

LG need not be equal to LD due to etch biasTypically LG < LD

Metallurgic channel length

LG

LM

LM < LG due to the lateral diffusion of source/drain implants

Effective channel length

LG

LM

Leff is electrically measured length from I-V characteristics

Leff < = LM

Pitch scaling has become increasingly Difficult

Dimension scaling leads pitch scaling

Definition of technology node has become very fuzzy

Dimension vs Pitch Scaling

Source : ITRS

Technology Life Cycle

International Technology Roadmap for Semiconductors (ITRS) trends

www.itrs.net

Intel’s Technology node vs minimum feature

S. Thomson et. al. , IEDM 2002 , pp. 61-64

INTEL’s 22nm CMOS Technology

FinFET

Single FinFET

SRAMArray

High K, Metal gate, Strained Silicon, Cu and low-k

Debate at IEDM 2012 on Intel’s claim of 22nm CMOS

Year of Production 2013 2016 2019 2022 2025

Technology Node (nm)(DRAM Half pitch)

28 20 14.2 10 7.1

Transistor Gate Length in Microprocessors circuits (nm)

20 15.3 11.7 8.9 6.6

Wafer diameter (inch) 12 18 18 18 18

Transistors density in Microprocessor (billion / cm2)

1.59 3.19 6.38 12.77 25.54

Number of interconnect wiring levels in the Microprocessor

12 13 14 15 16

Operating voltage (V) 0.85 0.77 0.71 0.64 0.59

ITRS Projections

The distribution across Technologies

Polysilicon Gate stack

Si

Phase Shift LithoResist Trim

Si

Poly Etch

Si

i-PolySiliconLPCVD

Si

Dry, 800C, O2+N2

Nitridation

Si

RCA Clean

Junction Module

NMOS Halo and Extension

Si

Si

Arsenic, 0o tilt, ~1014, 5KeV

Si

Boron, 45o tilt, ~1012, 15KeVNMOS S/D Litho

PMOS Halo and Extension

Si

Phosphorus, 45o tilt, ~1012, 35KeV

Si

BF2, 0o tilt, ~1014, 3 KeV

Si

PMOS S/D Litho

Spacer FormationDeposit 10nm Oxide, 40nm nitride

Si

Anisotropic nitride etchSi

Deep S/D Implant and AnnealNMOS S/D LithoArsenic, 15 KeV, ~1015

Si

PMOS S/D LithoBoron, 5 KeV, ~1015

Si

Si

RTA

Trade off between poly depletion,versusJunction depth & Boron Penetration

Silicide Formation

PVD MetalRTAETCH METAL

S D

G

Parasitic Channel Resistance

Si

Interconnect Module

ILD0 , Contact and Metal1

Si

ILD0 CVDContact Litho & EtchW CVD and CMPAluminum PVDMetal Litho & EtchForming gas anneal

Same process continues for Via1, Metal2, Via2, Metal3 …

Interconnect delay in Nano CMOS

Delay

0.50.350.250.18

Technology node (mm)

Intrinsic gate delay

Interconnect delay

Gate delay decreases due to decrease in gate capacitance

Interconnect delay increases due to decreasing metal line widthand increasing intra-metal coupling capacitance

Interconnects are no longer afterthought in Nano CMOS

Copper Interconnects

ILD CVD (thickness for via and metal)Litho Via holes and etch via holeLitho Metal trenches and etch metal trenchCopper Electroplating and CMP

Si

Dual Damascene Process