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Computer System Hardware

Reading:Silberschatzchapter 2

Additional Reading:Stallingschapter 1, 2

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OutlineComputer HardwareCPU ComponentsRegistersInstruction ExecutionInterrupt and TrapMemory

HierarchyCache

Dual Mode OperationProtection

HardwareMemoryCPU, I/O

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Key ElementsCPU or ProcessorMain Memory

typically volatilealso referred as real memory or primary memory

I/O modulessecondary memory devicescommunications equipmentterminals

System buscommunication among processors, memory, and I/O modules

Why study hardware?OS exploits hardware resources to provide set of services

Computer Hardware

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CPU Components

Computer Components: Top-Level View

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User-Visible registersHelps programmer to minimize main memory referencesTypically two types of registers1. Data registers 2. Address registers

IndexSegment pointerStack pointer

Processor Registers

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Data registersGeneral purpose (programmers or machine)May be dedicated (floating-point and integer operations)

Address registersIndex

Involves adding an index to base value to get effective address

Segment pointerWhen memory is divided into segments, memory is referenced by a segment and an offset

Stack pointerPoints to top of stack

User-Visible Registers

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Program CounterContains the address of instruction to be fetched

Instruction RegisterContains the instruction most recently fetched

Program Status Word (PSW)Condition codesInterrupt enable/disableSupervisor/user mode

Control and Status RegistersMostly not visible to user, organization is machine specific

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Condition Codes or FlagsBits set by the processor hardware as a result of operationsExamples

Positive resultNegative resultZeroOverflow

Control and Status Registers

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Instruction ExecutionInstruction Cycle – processing required for single instruction

Two step processing in simplest formProcessor reads instructions from memory one at time

FetchesProcessor executes each instruction

Basic Instruction Cycle

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Instruction Fetch and ExecuteThe processor fetches the instruction from memoryProgram counter (PC) holds address of the instruction to be fetched nextProcessor increments the PC after each fetch

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Instruction RegisterFetched instruction is loaded in IRInstruction categories

Processor-memoryTransfer data between processor and memory

Processor-I/OData transferred to or from a peripheral device

Data processingArithmetic or logic operation on data

ControlAlter sequence of execution

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InterruptsCommon Class of Interrupts

ProgramResult of instruction execution, e.g. arithmetic overflow, division by zero or illegal memory reference

TimerProcessors timer, functions on regular basis

I/OGenerated by I/O controller, signal or error

Hardware FailurePower failure or memory parity error

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Interrupt and TrapMechanisms to interrupt the normal processing of processor

TrapTrap is the notification of an internal event, highest priorityTraps are immediate and occur synchronously with the current activity of processor (result of program execution)

InterruptInterrupt is the notification of an external eventOccur asynchronously with the current activity of processor

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Program Flow of Control

(a) No Interrupts (c) Interrupts; long I/O wait(b) Interrupts; short I/O wait

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Interrupts

Simple Interrupt Processing

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Multiple Interrupts

Sequential interrupt processing

Disable new interrupts while an interrupt is being processed

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Multiple InterruptsDisadvantages of sequential interrupt processing

Does not account for relative priority or time critical needsI/O device may fill and overflow

Define priorities and serve in order

Nested interrupt processing

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Multiple Interrupts

Example: Time sequence of multiple interrupts with priorities

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Memory HierarchyDesign Constraints

How much?Open ended, large capacity

How fast?Mach the processor, do not wish to wait

How expensive?Reasonable relationship to other components

Tradeoff among three componentsFaster access time, greater cost per bitGreater capacity, smaller cost per bitGreater capacity, slower access speed

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Memory Hierarchy

As one goes downDecreasing cost per bitIncreasing capacityIncreasing access time

Key to success – Decrease the frequency of access

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CachingCopying information into faster storage system; main memory can be viewed as a fast cache for secondary storageUse of high-speed memory to hold recently-accessed dataRequires a cache management policy

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Caching

Cache Read Operation

Cache sizeReplacement policy

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Typical Memory Hierarchy

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Hardware ProtectionSharing of Resources → Utilization and Problems

OS must ensure that an incorrect program cannot cause other programs to execute incorrectly

Hardware ProtectionDual-Mode OperationI/O ProtectionMemory ProtectionCPU Protection

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Dual-Mode OperationProvide hardware support to differentiate between at least two modes of operations

User Mode → execution done on behalf of a user

Monitor Mode (also kernel mode or system mode) →execution done on behalf of operating system

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Dual-Mode OperationMode bit added to computer hardware to indicate current mode: Monitor (0) or User (1)When an interrupt or fault occurs hardware switches to monitor mode

Privileged instructions can be issued only in monitor modeMSDOS (8088 architecture) – No Mode bitWin 2000, IBM OS/2 (advanced versions of Intel CPU, Pentium)

provide dual-mode operation

Monitor User

Interrupt/fault

set user mode

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I/O ProtectionAll I/O instructions → privileged instructions

Must ensure that a user program could never gain control of the computer in monitor mode

All I/O instructions → through OS, checks if valid

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Use of system call to perform I/O

I/O Protection

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Memory ProtectionMemory protection → Prevent interrupt vector and interrupt service routines from user program

Range of legal addresses - two registersBase register → holds the smallest legal physical memory addressLimit register → contains the size of the range

Memory outside the defined range is protected

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Use of base and limit register

Memory Protection

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Hardware Address Protection

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Hardware ProtectionThe load instructions for the base and limitregisters are privileged instructions

When executing in monitor mode, OS has unrestricted access to both monitor and user’s memory

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CPU ProtectionPrevent user program from struck in infinite loopor never returning control to OSTimer – interrupts computer after specified period to ensure OS system maintains control

Timer is decremented every clock tickWhen timer reaches the value 0, an interrupt occurs

Timer commonly used to implement time sharingLoad-timer is a privileged instruction