confidential material max 10 fpgas - overview tom schulte low cost product marketing 5/9/2014
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Confidential Material
MAX 10 FPGAs - Overview
Tom Schulte
Low Cost Product Marketing
5/9/2014
Innovation Leader Across the Board
PLDsLowest Cost,Lowest Power
PowerSoCsHigh-efficiency
Power Management
FPGAsCost/Power BalanceSoC & Transceivers
DesignSoftware
DevelopmentKits
Embedded Soft andHard Processors
FPGAsMid-range FPGAs
SoC & Transceivers
R E S O U R C E S
FPGAsOptimized for
High Bandwidth
IntellectualProperty (IP)
IndustrialComputingEnterprise
2
Low Cost Families – Altera Continues Focus & Investment
More performance,features, or density
2000
3
2013
MAX® IIMAX® IICPLD Products
MAX VMAX V
FPGA Products
Cyclone®Cyclone®
Cyclone IICyclone II
Cyclone IIICyclone III
Cyclone IVCyclone IV
In Design
NextGeneration
MAX 10MAX 10
Cyclone VCyclone V
Cyclone VSoC
Cyclone VSoC
Product Planning
Future
Delivering
Next Generation
Products
MAX 10 FPGAs: Revolutionizing Non-Volatile Integration
FPGA Capabilities- Up to 50,000 Logic Elements- Analog Block with ADC- Internal SRAM- PLLs- DSP Blocks- External Memory Interface (e.g. DDR3)- Dual Image Configuration- Nios II Embedded Processor- LVDS, PCI, and 30+ other I/O Standards- Design Security- Sleep Mode
Non-volatile Features- Instant-On - User Flash Memory- Voltage Regulator- Internal Oscillator
4
MAX 10 FPGAs Simplify FPGA Systems
5
Traditional FPGA
(Up to 50k LE)
ADC
3.3V I/ODual Image
Configuration Device
Analog
1.2V 2.5V3.3V
MAX 10 FPGA(Up to 50k LE)
3.3V I/O
Analog
3.3V
LDO LDO
Analog Block
Dual ImageConfiguration Memory
Instant-OnConfiguration
Vsupply
LDO
Vsupply
Traditional FPGA MAX 10 FPGAs
Standard Configuration Time
CPLD
MAX 10 FPGAs Increase Capabilities of CPLD Systems
6
3.3V I/O
MAX 10 FPGA
3.3V I/O
AnalogAnalog Block
SingleImage
CPLD MAX 10 FPGAs
Logic Elements 240 – 8,000 2,000 – 50,000
Instant-On Images Single Dual
DSP No Yes
DDR3 SDRAM No Yes
Analog Block w/ADC No Yes
Embedded Processor No Nios II
External MemoryInterface
Single Image Dual
Image
DSP
User Flash(Nios code)
MAX 10 vs. Prior Family – Higher Single Chip Integration
Feature MAX V CPLDs MAX 10 FPGAs
Process Technology 180 nm 55 nm
User Logic (max.) 2,000 LE’s 50,000 LE’s
On-chip Configuration Single Image Dual Image, AES
User I/O 271 Up to 500
User Flash Memory 8 Kb Up to 512 Kb
On-chip hard IP blocks -Embedded RAM, DSP,
ADC, PLL
Remote System Upgrade No Yes
7
Lowering System Cost & Increasing Reliability
MAX 10 FPGA - Floorplan
Main Architecture Modules- Logic array
- On-chip RAM & FLASH
- DSP blocks
- Up to two analog blocks
- Up to eight I/O banks
- Up to four PLL’s
- Oscillator & Clocks
- Soft IP functionality
Nios® II 32-bit processor, Ethernet MAC, PCIe MAC, Video IP Suite, etc.
RAM Blocks
PLL’SExternal Memory Interfaces
Analog Blocks
DSP Blocks
Logic Array Blocks
Config.
Flash
User Flash
8
Control Block
MAX 10 FPGA – Family Plan
9
Device LEsBlock
Memory(Kb)
UserFlash 1
(Kb)
18x18Mults PLLs Internal
Config.ADC 4, TSD
ExternalRAMI/F
10M02 2,000 108 96 16 1, 2 Single - Yes 2
10M04 4,000 189 128 19 1, 2 Dual 1, 1 Yes 2
10M08 8,000 378 256 24 1, 2 Dual 1, 1 Yes 2
10M16 16,000 549 256 45 1, 4 Dual 1, 1 Yes 3
10M25 25,000 756 256 61 1, 4 Dual 2, 1 Yes 3
10M40 40,000 1,260 512 125 1, 4 Dual 2, 1 Yes 3
10M50 50,000 1,638 512 144 1, 4 Dual 2, 1 Yes 3
Preliminary and subject to change without notice.
Notes:1. Additional User Flash may be available, depending on configuration options.2. SDR SDRAM or SRAM only.3. SDR SDRAM, SRAM, DDR3, DDR2, or LPDDR2.4. ADC blocks available on die but may not be available in low pin count packages.
MAX 10 FPGA - Feature Set Options
Three Feature Set VariantsTo Order From
Feature Set C: Compact F: Flash A: Analog
Single Image Yes Yes Yes
Dual Image w/Remote System Upgrade
- Yes Yes
Analog Features Block - - Yes
“C” “F” “A”
10
Package Plan & Available I/O (Dual Power Supply: 1.2V/2.5V)
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ProductLine
36-WLCSP3x3mm2
0.4mm Pitch
81-WLCSP4x4mm2
0.4mm Pitch
256-FBGA17x17mm2
1.0mm Pitch
324-UBGA15x15mm2
0.8mm Pitch
484-FBGA23x23mm2
1.0mm Pitch
672-FBGA27x27mm2
1.0mm Pitch
10M02 “D” C (27) - - C (160) - -10M04 “D” - - C/F/A (178) C/F/A (246) - -10M08 “D” - C/F (56) C/F/A (178) C/F/A (246) C/F/A (250) -10M16 “D” - - C/F/A (178) C/F/A (246) C/F/A (320) -10M25 “D” - - C/F/A (178) - C/F/A (360) C/F/A (380)10M40 “D” - - C/F/A (178) - C/F/A (360) C/F/A (500)10M50 “D” - - C/F/A (178) - C/F/A (360) C/F/A (500)
C: Compact
F: Flash
A: Analog
Preliminary and subject to change without notice
Wide Variety of Sizes & Available I/O
WLCSP xBGAU = 0.8mm ball spacingF = 1.0mm ball spacing
BareDie
Note: Selected items = Pro-active automotive p/n rollout.Other product line/package combinations available upon request & sufficient ROI.
Package Plan & Available I/O (Single Power Supply: 3.3V)
12
ProductLine
144-EQFP16x16 mm2
0.4 mm Pitch
153-MBGA8x8mm2
0.5mm(1)
169-UBGA11x11mm2
0.8mm
10M02 “S” C (101) C (112) C (130)10M04 “S” C/F/A (101) C/F/A (112) C/F/A (130)10M08 “S” C/F/A (101) C/F/A (112) C/F/A (130)10M16 “S” C/F/A (101) - C/F/A (130)10M25 “S” C/F/A (101) - -10M40 “S” C/F/A (101) - -10M50 “S” C/F/A (101) - -
C: Compact
F: Flash
A: Analog
Preliminary and subject to change without noticeNotes: 1 – “Easy PCB” utilizes 0.8mm PCB design rules2 - Items in blue = Pro-active automotive p/n’s.Others available upon request & sufficient ROI.
Single Supply Option forSimplicity & Convenience
xBGAM = 0.5mm ball spacingU = 0.8mm ball spacing
EQFPBareDie
MAX 10 FPGA Ordering Information
13
10M 16 x x u484 i 7 x ßß
Family 10M: MAX 10 FPGA
ProductLine
02: 2K LE’s04: 4K LE’s08: 8K LE’s16: 16K LE’s25: 25K LE’s40: 40K LE’s50: 50K LE’s
PowerSupply
S: Single VoltageD: Dual Voltage
Package Type& Ball Count
V: Wafer level chip-scaleE: EQFPM: MBGAU: UBGAF: FBGA
36, 81144153169, 324256, 484, 672
Grade /Temperature
C: Commercial (TJ = 0°C to +85°C)I: Industrial (TJ = -40°C to +100°C)A: Automotive (TJ = -40°C to +125°C)
Speed
6, 7, 86 = fastest,8 = slowest
ESG = RoHS 6P = Leadedßß = Special processing
OptionalSuffix
FeatureOption
C: Compact featuresF: Flash featuresA: Analog features
MAX 10 FPGA I/O Standard Support
I/O Standard Variant Toggle Rate 1 (MHz) Max Strength Load Application
Single-Ended
LVTTL/LVCMOS 3.3V 2 mA 10 pF General purposeLVTTL/LVCMOS 3.0V 250 16 mA 10 pF General purposeLVTTL/LVCMOS 2.5V 250 16 mA 10 pF General purposeLVTTL/LVCMOS 1.8V 250 12 mA 10 pF General purposeLVTTL/LVCMOS 1.5V 250 8 mA 10 pF General purposeLVTTL/LVCMOS 1.2V 200 8 mA 10 pF General purpose
PCI 250 - 10 pF General purposeSchmitt Trigger (RX only) 200 - - General purpose
External Memory Interfaces
(& Voltage Referenced I/O)
SSTL2 Class I 250 12mA/50 W 7 pF DDR1SSTL2 Class II 250 16 mA/25 W 7 pF DDR1SSTL18 Class I 300 12mA/50 W 7 pF DDR2SSTL18 Class II 300 16 mA/25 W 7 pF DDR2SSTL15 Class I 300 12mA/50 W 7 pF DDR3SSTL15 Class II 300 16 mA/25 W 7 pF DDR3
SSTL15 300 34 W 7 pF DDR3SSTL135 300 34 W 7 pF DDR3LHSUL12 200 34 W 7 pF LPDDR2
HSTL18 Class I 300 12mA/50 W 7 pF DDR2+/QDR2+/RLDRAM2HSTL18 Class II 300 16 mA/25 W 7 pF DDR2+/QDR2+/RLDRAM2HSTL15 Class I 300 12mA/50 W 7 pF DDR2+/QDR2/QDR2+/RLDRAM2HSTL15 Class II 300 16 mA/25 W 7 pF DDR2+/QDR2/QDR2+/RLDRAM2HSTL12 Cass I 200 12 mA/50 W 7 pF General purposeHSTL12 Class II 200 14 mA/25 W 7 pF General purpose
LVDS
Dedicated LVDS (RX/TX) 3 830/800 Mbps - 6 pF 2 Dedicated Mini-LVDS (TX) 3 380 Mbps - 6 pF 2
Dedicated RSDS (TX) 3 340 Mbps - 6 pF 2 Dedicated PPDS (TX) 3 420 Mbps - 6 pF 2
External Resistor LVDS (TX) 600 Mbps - 6 pF 2 External Resistor Mini-LVDS (TX) 380 Mbps - 6 pF 2 External Resistor RSDS (1R) (TX) 170 Mbps - 6 pF 2 External Resistor RSDS (3R) (TX) 342 Mbps - 6 pF 2
External Resistor PPDS (TX) 420 Mbps - 6 pF 2 LVPECL (RX only) 830 Mbps 6 pF 2 BLVDS (RX/TX) 830/475 Mbps 16 mA 6 pF 2
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Notes:1. Toggle rate (maximum) assumes max.
drive strength, fastest slew rate setting for the specified load, and fastest speed grade (–c6).
2. Measured on a single pin, not pair.3. Only available on the bottom I/O banks
(Bank3, Bank4).
Rev.
14.1
15
2013
Early Device Program Limited # of customers ES and/or EAP device shipments
10M04, 08, 40, and 50 ES p/n’s Early .POF / .SOF support
2014
Early Software Program Limited # of customers Hidden S/W in v13.1 (10M08 only) Production S/W in v14.0 (all
devices) Compilation & early timing EPE
Early Information Program Unlimited # of customers Monthly bulletins Advanced Info. Brief Preliminary handbook Other “specials”
Jul. Aug. Sept. Oct. Nov. Dec. Jan. Feb. Mar. Apr. May Jun. Jul. Aug. Sept. Oct. Nov. Dec.
#1 - EIP
#3 - EDP
MAX 10 FPGADevice Handbook
3 Early Access Programs for MAX 10 FPGA
Rev.
14.0
Rev.
13.1#2 - ESP
MAX 10 FPGAs Summary
MAX 10 FPGAs revolutionize non-volatile integration- Single-chip, non-volatile solution with the smallest footprint- Only dual-persona single-ship, non-volatile solution- Integrated ADC and other system-cost saving hard IP- Up to 95% dynamic power savings via sleep mode- Ideal for both datapath and control plane applications
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MAX 10 FPGA
Devices
Non-VolatileFPGA
What’s Next?
1H 2014 Early Information Program
2H 2014 Devices & Dev Kits Shipping
17
Would you sign-up for monthly email updates on MAX 10 FPGAs
(with valid NDA)?
Confidential Material
Back-Up Information
MAX 10 FPGA M153 Package – “Easy PCB” Footprint
19 Click to return to page 13
Intentionally created gaps in ball grid array to allow space for PCB traces
and/or through-hole via’s.
Goal: “Easy” PCB board design1. Use 0.8mm pitch design rules
instead of 0.5mm rules.• 2 layer signal breakout (SMD on
both component and PCB)• 3 mil line/space• 16 mil PTH• Shared P/G PTH
2. Avoiding use of blind or buried via’s.
3. Minimize the number of PCB layers needed to route to all device pins.
Note: Altera recommended PCB layout (preliminary) in 4Q 2013
8mm
8mm
0.5mm
Thank YouThank You
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