control unit: binary multiplier - departamento de...
Post on 04-Oct-2018
222 Views
Preview:
TRANSCRIPT
Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Control Unit: Binary Multiplier
Arturo Díaz-PérezDepartamento de Computación
Laboratorio de Tecnologías de InformaciónCINVESTAV-IPN
2Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Example: Binary MultiplierTwo versions
Hardwired controlMicroprogrammed
Multiplies two unsigned binary numbers
3Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Multiplication Algorithm
Either select multiplicand or zeroShift left one every timeSum all to get productResult size 2n
4Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
MultiplicationMultiplication can’t be that hard!
It’s just repeated addition.If we have adders, we can do multiplication also.
Remember that the AND operation is equivalent to multiplication on two bits:
a b ab0 0 00 1 01 0 01 1 1
a b a×b0 0 00 1 01 0 01 1 1
5Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Binary multiplication example
Since we always multiply by either 0 or 1, the partial products are always either 0000 or the multiplicand (1101 in this example).There are four partial products which are added to form the result.
We can add them in pairs, using three adders.Even though the product has up to 8 bits, we can use 4-bit adders if we “stagger” them leftwards, like the partial products themselves.
1 1 0 1 Multiplicandx 0 1 1 0 Multiplier
0 0 0 0 Partial products1 1 0 1
1 1 0 1+ 0 0 0 0
1 0 0 1 1 1 0 Product
6Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
A 2x2 binary multiplierThe AND gates produce the partial products.For a 2-bit by 2-bit multiplier, we can just use two half adders to sum the partial products. In general, though, we’ll need full adders.Here C3-C0 are the product, not carries!
B1 B0
x A1 A0
A0B1 A0B0
+ A1B1 A1B0
C3 C2 C1 C0
8Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
More on multipliersNotice that this 4-bit multiplier produces an 8-bit result.
We could just keep all 8 bits.Or, if we needed a 4-bit result, we could ignore C4-C7, and consider it an overflow condition if the result is longer than 4bits.
Multipliers are very complex circuits. In general, when multiplying an m-bit number by an n-bit number:
There are n partial products, one for each bit of the multiplier.This requires n-1 adders, each of which can add m bits (the size of the multiplicand).
The circuit for 32-bit or 64-bit multiplication would be huge!
9Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Multiplication: a special caseIn decimal, an easy way to multiply by 10 is to shift all the digits to the left, and tack a 0 to the right end.
128 x 10 = 1280
We can do the same thing in binary. Shifting left is equivalent to multiplying by 2:
11 x 10 = 110 (in decimal, 3 x 2 = 6)
Shifting left twice is equivalent to multiplying by 4:
11 x 100 = 1100 (in decimal, 3 x 4 = 12)
As an aside, shifting to the right is equivalent to dividing by 2.
110 ÷ 10 = 11 (in decimal, 6 ÷ 2 = 3)
10Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Hardware-Friendly Variation
Partial productRight shiftOnly n bit adder instead of 2nEach step either add/shift or just shift
11Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
ASM Chart
Look at it in parts
12Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
IdleWait until G assertedThen clear C and A, and set P to n-1Then multiplication begins
13Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
MultiplicationTo IDLE
Test Q0If 1, add B
Recall that MUL1 done all at same time
What happens to C?
Test counter zero
14Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Create Control Signals from ASM
Can look at it one set at a time
15Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
DatapathCounter size –ceiling of log n Holds multiplier as
well as shifted result. How?
16Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
More Counter preset to n-1. Counts down.
Signals when it
hits zero.
17Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Hardwired ControlTwo aspects to control
1. Control of the microoperations• Generating signals, such as those for the
ALU operations, register numbers, etc.
2. Sequencing• What happens next?• The order of any microoperations• Like states of our locks
18Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Register A
All microoperations on Reg ALast column is combinational expression that controls microoperationName is just assigned by designer
19Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Register B
LOADB is not listed on ASM chartIt’s an external signal that commands reg to load
20Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Flip-Flop C
Why is Load repeated?
21Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Register Q
SimilarExternal loadShift same as for Reg A
22Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Counter P
Both of counter’s Ops happen with others, so no new signals
23Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Sequencing
Now can look purely at sequencingOnly decisions affecting next state are left
Q0 did not affect state
27Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
What We Need to DoHave decided how to generate control signalsHave separated control of timing
Now: implement in logic
28Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Sequence Register and Decoder
Make register with enough bits to represent statesAdd decoder to generate signal for each stateFor our example (3 states) need
2-bit register2-to-4 decoder (only need 3 lines of it)
29Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
State Table
Let’s recall how this works by stepping through
30Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Generate Signals Using Tables
32Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Another ApproachOne Flip-Flop per state
Only one of the FFs has value 1The single 1 propagates, controlled by combinational logic
Seems wasteful at first glanceNeed n FFs instead of log n
However, it’s easy to design
33Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Design from ASMJust use transformation rules to convert ASM to logicHere’s state box
34Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Decision Box
Represents both possibilities
35Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
JunctionJunction just an OR gate
36Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Conditional OutputThe action is triggered by the generated control line
37Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Circuit from Chart
FFs labeled 1, decisions 2, junctions 3, control 4
38Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
VHDL Description of a Binary Multiplier (1)
library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity binary_multiplier is
port( CLK, RESET, G, LOADB, LOADQ: in std_logic;MULT_IN: in std_logic_vector(3 downto 0);MULT_OUT: out std_logic_vector(7 downto 0) );
end binary_multiplier;
architecture behavior_4 of binary_multiplier is type state_type is (IDLE, MUL0, MUL1);signal state, next_state : state_type;signal A, B, Q: std_logic_vector(3 downto 0);signal P: std_logic_vector(1 downto 0);signal C, Z: std_logic;begin
Z <= P(1) NOR P(0); MULT_OUT <= A & Q;state_register: process (CLK, RESET)begin
if (RESET = '1') thenstate <= IDLE;
elsif (CLK’event and CLK = '1') thenstate <= next_state;
end if;end process;
39Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
VHDL Description of a Binary Multiplier (2)
next_state_func: process (G, Z, state)begin
case state is when IDLE =>
if G = '1' thennext_state <= MUL0;
else next_state <= IDLE;
end if;when MUL0 =>
next_state <= MUL1;when MUL1 =>
if Z = '1' thennext_state <= IDLE;
else next_state <= MUL0;
end if;end case;
end process;
40Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
VHDL Description of a Binary Multiplier (3)
datapath_func: process (CLK)variable CA: std_logic_vector(4 downto 0);begin
if (CLK’event and CLK = '1') thenif LOADB = '1' thenB <= MULT_IN;
end if;if LOADQ = '1' then
Q <= MULT_IN;end if;case state is
when IDLE => if G = '1' then
C <= '0';A <= "0000";P <= "11";
end if;when MUL0 =>
if Q(0) = '1' thenCA := ('0' & A) + ('0' & B);
else CA := C & A;
end if;C <= CA(4);A <= CA(3 downto 0);
when MUL1 =>C <= '0'; A <= C & A(3 downto 1);Q <= A(0) & Q(3 downto 1);P <= P - "01";
end case;end if;
end process;end behavior 4;
41Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Microprogrammed Approach
Control values stored in a memory
Job of instructions is to generate control signals to datapath and output
42Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Nomenclature and Characteristics
Word of memory called microinstructionThe set of instructions called microprogramSometimes in ROM, sometimes loadableOften wide word
43Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Microprogrammed Control Unit
Control Address Register (CAR) equivalent to PCSequencer
Part of instruction sent to next-address generator to determine next instruction addr
44Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Control Data Register
Pipelining approach to break up the delay in the addrgen and ROMNot used in example
45Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Status Bits
Notice that they go only to sequencerCan only affect next control wordSo, conditional output boxes not allowed in this architecture
47Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Microinstruction
Word format
Addresses of potential next instructionsFields for next instruction selectionFields for datapath control
48Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Datapath Control SignalsDoesn’t include load reg inst.Look at ASM to see where they are asserted
49Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Mapping to Microinstruction
Have only 4 signalsCould encode (2 bits)Would cost a decoder
Just a design tradeoffThis design has tiny ROM anyway
50Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Sequencer Design
Probably most important part of this processThis design provides 2 addrs
SEL field and control logic choose one
Other possibility is one addr fieldChoice is to go to next sequential addr (like PC), orUsing control signals go to addr specified
52Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Result5 words in ROMROM is 12 bits wideDesign next
53Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Microprog Design for Mult
MUX1 chooses addr1 or addr2
MUX2 control from datapath status and external signals.
Next slide
54Aritmética Computacional 2007 Caso de Estudio: Multiplicador Secuencial
Detail of Control
NXTADD1
NXTADD0
top related