copyright © 1997 altera corporation 9/12/97 asynchronous vs synchronous circuit design danny mok...

Asynchronous vs SynchronousCircuit Design

Danny Mok

Altera HK FAE

(dmok@altera.com)

Asynchronous Circuit Design

Mainly use Combinational Logic to do the decoding– Address decoder

– Fifo/Ram Read or Write pulse

The output logic does not have any relationship with any clocking signal

Usually the Decoding Glitch can be monitored at the output signal

Synchronous Circuit Design

Usually the circuit design will involve with different kind of Flip-Flop– D type, JK type, RS type or T type

The output logic is fully control by the rising edge or falling edge of the same clocking signal

No Glitch will be experienced at the output signal

Asynchronous Design Example

Binary Counter : LLLL LLLH LLHL LLHH .......... HHHH

BCD to DEC : LLLL -> HHHHHHHHHL LLLH -> HHHHHHHHLH LLHL -> HHHHHHHLHH LLHH -> HHHHHHLHHH .......... -> ............................ HLLH -> LHHHHHHHHH

Expect Output

This is the IDLE output waveformbut

what will we get reallywhat will we get really ?

Functional Simulation Output

What is this ?

Timing Simulation Output

It get worst !!! What is going on ? Engineer Design problem or Altera DeviceProblem ? But ..... It works with 74xx TTL logic and fail with Altera Device, itmust be Altera Device Problem ..........

What is Happening

Let us take a closer look of the 74390 and 7442

In order to have Glitch Free Q[9..0]N Output :

1.) IF the output of 74390 reach the NAND4 at the same time

2.) IF Trace Delay A equal to Trace Delay B

and equal to Trace Delay C

and equal to Trace Delay D

Does the IF is reasonable ?

2.) IF Trace Delay A equal to Trace Delay B

and equal to Trace Delay C

and equal to Trace Delay D

This condition is OK from The Delay Matrix

How about this IF condition ?

1.) IF the output of the 74390 reach the NAND4 at the same time

74390 All four DFF clocking by DIFFERENT CCLLOOCCKK SOURCE

What it course by different Clock Source

The DFFs clocking by Four different Clock Source– the output of the DFF will come out at different time

The output of 74390 goes to the 7442 at different time will cause Decoding Glitch– detail of Combinational Circuit Decoding Glitch, please refer to

the Design of Combinational Circuit presentation material

How to solve the problem ?– 1.) play around with the trace delay - BAD SOLUTION

– 2.) change the design from Asynchronous Circuit to Synchronous Circuit - PERFECT SOLUTION

How is the circuit work ?

Let us analysis the circuit : after RESET the value of 74390 and 7442 output value is LLLL HHHHHHHHHL1.) first clock come in, output will change to LLLH HHHHHHHHLH2.) second clock come in, output will change to LLHL HHHHHHHLHH3.) third clock come in, output will change to LLHH HHHHHHLHHH.....................................................................

This is Combinational Circuit Output, so Glitchwill be generated. So I shall change this circuitto Synchronous Circuit

Asynchronous and Synchronous Circuit74390 7442LLLL HHHHL LLLH HHHLH LLHL HHLHH LLHH HLHHH LHLL LHHHH

RESET 74390 m7442LLLL HHHHL LLLH HHHLH LLHL HHLHH LLHH HLHHH LHLL LHHHH

Asynchronous 7442 Output

Synchronous m7442 Output

Synchronous m7742

SUBDESIGN m7442( RESET : INPUT; A, B, C, D : INPUT; CLK : INPUT; Q0N, Q1N, Q2N, Q3N, Q4N, Q5N, Q6N, Q7N, Q8N, Q9N : OUTPUT;)VARIABLE QOUT[9..0] : DFF;BEGINQOUT[9..1].PRN = !RESET;QOUT[0].CLRN = !RESET;QOUT[].CLK = CLK;IF (!D & !C & !B & !A) THENQOUT[] = B"1111111101";ELSIF (!D & !C & !B & A) THENQOUT[] = B"1111111011";ELSIF (!D & !C & B & !A) THENQOUT[] = B"1111110111";ELSIF (!D & !C & B & A) THENQOUT[] = B"1111101110";ELSIF (!D & C & !B & !A) THEN

QOUT[] = B"1111011111";ELSIF (!D & C & !B & A) THENQOUT[] = B"1110111111";ELSIF (!D & C & B & !A) THENQOUT[] = B"1101111111";ELSIF (!D & C & B & A) THENQOUT[] = B"1011111111";ELSIF (D & !C & !B & !A) THENQOUT[] = B"0111111111";ELSEQOUT[] = B"1111111111";END IF;Q0N = QOUT[0];Q1N = QOUT[1];Q2N = QOUT[2];Q3N = QOUT[3];Q4N = QOUT[4];Q5N = QOUT[5];Q6N = QOUT[6];Q7N = QOUT[7];Q8N = QOUT[8];Q9N = QOUT[9];END;

Synchornous m7442 Circuit Design

Everything the same except change 7442 to Synchronous m7742

All the outputs are synchronouswith the same clocking source

Simulation Output

Functional Simulation

Timing Simulation

Synchronous is good but

Synchronous is good but will it use more gate count than the Asynchronous cirucit– the answer is No but may be also yes

Asynchronous circuit will use combinational logic (AND, OR gate ) only but

Synchronous circuit will use both combinational logic and Flip-FlopFlip-Flop

So Synchronous Design MUSTMUST use more gate than the Asynchronous Circuit

ASIC vs FPGA/CPLD Approach

ASIC gate count calculation– 1 gate count = 1 two input NAND gate– 7 gate count = 1 D type Flip-Flop

For 4 input NAND gate implement in ASIC, the gate count is equal to 3 gate count

So Asynchronous cirucit 7442 gate counts are– Q0N = 4 input NAND = 3 gate counts

Synchronous circuit m7442 gate counts are– Q0N = 4 input NAND + 1 DFF = 3 + 7 = 10 gate counts

So Synchronous gate count > Asynchronous circuit in ASIC implementation

BUT ..........BUT ..........

CPLD/EPLD/FPGA Approach

But gate count calculaiton in CPLD/EPLD/FPGA are total different

Altera 7000/9000 (EPLD) are Macro Cell base (MC) Altera 8000/10K/6000 (CPLD) are Logical Cell base (LC) Each MC and LC has a Flip-Flop come from FREE

MC (FF) LC(FF)

Asynchronous Circuit design– 1 four input NAND will use 1 MC

Synchronous Circuit design– 1 four input NAND + 1 D type FF also use 1 MC

Both Asynchronous and Synchronous Circuit design use the same number of MC

Please note that each MC or LC has a Flip-Flop, the Flip-Flop already in the device, no matter you use it or not

For this example, the Asynchronous and Synchronous, no increase in MC for the design

Wait ............

Now I understand why Glitch is generated and kill my cirucit, but .........

Altera also not good because my circuit work perfectly fine with 74xx series and already work for a long time, it must be either– Altera Device is not good and having problem

– Altera Provide the Library is not good and having problem

Let us take a look of the design

Are you sure this is all your circuit

Are you sure this is all your circuit ? YESYES or NO ?NO ?

No, I don’t add this capacitor in my circuit,where is it come from ? What is the value ofthis capacitor ?

The Capacitor comes from ......

The junction between IC pin (7~10pf) and PCB + PCB material

Can I ......

What is the value of this Capacitor– it is undetermine value, general speaking is around 10~35pf, it

depends on the solidering material and PCB materials

Can I remove this Capacitor– No. You can only mininize the capacitor value by using some

better conductivity materials

Meaningless to me !!!!

Why I need to know about this Capacitor as far as I use the 74xx series work fine ? There is no Glitch

The Glitch only happen when I use Altera Device!!!

Closer Look of the function of the Capacitor

The resistance of the Capacitor is – a function of (Frequency) and (Capacitor value)

Resistance of the Capacitor = (magic number constant) * (Capacitor value)/(Frequency of the Signal)

Resistance of the Capacitor when Capacitor value

Resistance of the Capacitor when Frequency of the Signal

That means during VERY HIGH FREQUENCY, the Capacitor will behaviour as a SHORT CIRCUITAssume the Glitch is 2ns width, it is equivalent to 250MHz frequency signal

PCB Capacitor act as Filter

Your circuit by using 74xx also will generate Glitch but it FILTER OUT by the PCB Capacitor, so yourcircuit work fine. Your circuit work just because of LUCK.So, if something work doesn’t means it design right. If the engineer does not understand why it works, itjust like paly Black Jack - grambling

2ns pulse width => 250MhzYour circuit work becausethe rest of the system does not see this Glitch

But if you

CPLD/FPGA

X The PCB Capacitor isno longer exist

The rest of the system stillcan see this Glitch and this Glitch kill your design

Glitch will be remove by PCB capacitor butwill cause problem within any CPLD/FPGA

Words from Friend

This kind of Decoding Glitch not only happen at Altera Device, this is characteristic of all IC

This kind of Decoding Glitch will be easier to show up and kill your design when the Processing Technology migrate to smaller and smaller geometry– 1.2um -> 1.0um -. 0.8um -> 0.65um -> 0.5um -> 0.35um

– now industry technology is talking about 0.25um and 0.15um

1.2um work fine, why need to migrate to smaller geometry

Because– this is the only way to get Higher Speed Grade CPLD/FPGA

and Lower Cost (all engineers asking for this)

– there is no free lunch, Higher Speed Grade and Lower Cost device means you need to be more careful when you do your design

Someone tell you the true story of the Glitch is your friend

I want to share my experience with you, purchase my device or not is not the only thing between you and me

If someone tell you that company X.... device or L.... device never generate Decoding Glitch....You better ask him why ? Because decoding Glitch is the IC characteristic.If he can not give you a good reason, may be he just want........

I just want you to purchase my device, that is the only thing between you and me

Conclusion

All kind of circuit design may involve both Asynchronous and Synchronous module

Asynchronous circuit module usually will experience Decoding Glitch at the output signal

Synchronous circuit module usually will not experience Decoding Glitch at the output signal– but if setup/hold time does not take good care, metastable will

experience at the output signal

If the output signal is used to control the RESET, CLEAR, PRESET etc....., please consider to use Synchronous instead of Asynchronous circuit

D ec is ion F low C h art

M ake su re th a t th e ou tp u to f th e c ircu it d oes n o t u sefo r R E S E T, C L E A R e tc .... .

A syn ch ron ou s c ircu it d es in gis O K

C ircu it ru n m oreS tab le

b ecau se it is G litch F ree

Th e am ou n t o f th e F lip -F lopu sag e w ill b e in c rease

B u t it is free fo rA lte ra D evice

C h an g e th e c ircu it toS yn ch ron ou s C ircu it

Th e ou tp u t o f th e log ic m u s t b eG lic th F ree ?

No Yes

copyright © 1997 altera corporation 9/12/97 asynchronous vs synchronous circuit design danny mok...

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