counters as state machines lecture l9.1 handout section 9.1

Counters as State Machines

Lecture L9.1

Handout Section 9.1

Counters as State Machines

• Divide by 8 Counter

• A Divide-by-16 Counter with Count Enable

CLK

D Q

!Q

CLK

D Q

!Q

CLK

D Q

!Q

Q0Q0.D

Q1

Q2

Q1.D

Q2.D

s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Divide-by-8 Counter

s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Divide-by-8 Counter

Q2

Q1 Q000 01 11 10

0

1 1 11

1

Q2.D

Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Divide-by-8 Counter

Q2

Q1 Q000 01 11 10

0

1

1

11

1

Q1.D

Q1.D = !Q1 & Q0 # Q1 & !Q0

s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Divide-by-8 Counter

Q2

Q1 Q000 01 11 10

0

1

1

11

1

Q0.D

Q0.D = ! Q0

Divide-by-8 Counter

000 001 010 011

111 110 101 100

A state machine for a divide by 8 counter

Divide-by-8 Counter

A state-transition table

s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0

State Q2 Q1 Q0 Q2.D Q1.D Q0.D

Divide-by-8 Counter

A Divide by 8 counterCircuit using D Flip-flops

D Q

!QCLK

D Q

!QCLK

D Q

!QCLK

Q2

Q1

Q0

Q2

Q1

Q0

CLK

MODULE div8cntsTITLE 'Divide by 8 Counter using State Machine' DECLARATIONShex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]);d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS "CLK PIN 12; " 1 Hz clock (jumper)clear PIN 11; " switch 1 " OUTPUT PINS "Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16Q = [Q2..Q0]; " 3-bit output vector [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

div8cnts.abl

" DefinitionsQSTATE = [Q2,Q1,Q0];s0 = [0,0,0];s1 = [0,0,1];s2 = [0,1,0];s3 = [0,1,1];s4 = [1,0,0];s5 = [1,0,1];s6 = [1,1,0];s7 = [1,1,1]; state_diagram QSTATE state s0: GOTO s1; state s1: GOTO s2; state s2: GOTO s3; state s3: GOTO s4; state s4: GOTO s5; state s5: GOTO s6; state s6: GOTO s7; state s7: GOTO s0;

000 001 010 011

111 110 101 100

Define the states;Associate a variable nameWith a numerical representation

Define the transitionsbetween the states

div8cnts.abl (cont.)

EQUATIONS Q.AR = clear;Q.C = CLK; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g];d7R.[D2..D0] = Q;d7R.D3 = 0;

Connect the clock

Connect the 7-segment display

div8cnts.abl (cont.)

div8cnts.abl (cont.)

test_vectors([CLK, clear] -> Q)[.C.,1] -> 0;[.C.,0] -> 1;[.C.,0] -> 2;[.C.,0] -> 3;[.C.,0] -> 4;[.C.,0] -> 5;[.C.,0] -> 6;[.C.,0] -> 7;[.C.,0] -> 0;[.C.,0] -> 1;[.C.,0] -> 2;[.C.,0] -> 3;[.C.,0] -> 4; END div8cnts

Counters as State Machines

• Divide by 8 Counter

• A Divide-by-16 Counter with Count Enable

A Divide-by-16 Counter with Count Enable

div16cnt

Q0

Q1

Q2

Q3

Coutclear

CLK

count

count = 1 Counter countscount = 0 Counter stops countingCout = 1 if [Q3..Q0] = [1,1,1,1]

s15 s0 s1

s2

s3

s14

s13

s12

s11

s10

s9 s8 s7 s6

s5

s4

count count

count

count

count

count

count

countcountcount

countcount

count

count

count

count

!count !count !count !count

!count !count!count!count

!count

!count

!count

!count !count

!count

!count

!count

State Diagram for a Divide-by-16 Counter with Count Enable

div16cnt.ablMODULE div16cntinterface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]);TITLE 'Divide by 16 (4-bit) Counter using State Machine' DECLARATIONS " INPUT PINS "CLK PIN ; " clock inputclear PIN ; " asynchronous clearcount PIN ; " count enable " OUTPUT PINS "Q3..Q0 PIN ISTYPE 'reg'; Q = [Q3..Q0]; " 3-bit output vectorCout PIN ISTYPE 'com'; " Carry out 

" DefinitionsQSTATE = [Q3,Q2,Q1,Q0];s0 = [0,0,0,0];s1 = [0,0,0,1];s2 = [0,0,1,0];s3 = [0,0,1,1];s4 = [0,1,0,0];s5 = [0,1,0,1];s6 = [0,1,1,0];s7 = [0,1,1,1];s8 = [1,0,0,0];s9 = [1,0,0,1];s10 = [1,0,1,0];s11 = [1,0,1,1];s12 = [1,1,0,0];s13 = [1,1,0,1];s14 = [1,1,1,0];s15 = [1,1,1,1];

div16cnt.abl (cont.)

state_diagram QSTATE state s0: if count then s1 else s0; state s1: if count then s2; else s1; state s2: if count then s3; else s2; state s3: if count then s4; else s3; state s4: if count then s5; else s4; state s5: if count then s6; else s5; state s6: if count then s7; else s6; state s7: if count then s8; else s7;

Use If..Then statements toimplement the count

div16cnt.abl (cont.)

div16cnt.abl (cont.) state s8: if count then s9 else s8; state s9: if count then s10; else s9; state s10: if count then s11; else s10; state s11: if count then s12; else s11; state s12: if count then s13; else s12; state s13: if count then s14; else s13; state s14: if count then s15; else s14; state s15: if count then s0; else s15;

div16cnt.abl (cont.)

EQUATIONS Q.C = CLK;Q.AR = clear;Cout = Q3 & Q2 & Q1 & Q0; END div16cnt

8-Bit Counter

div16cnt

Q4

Q5

Q6

Q7

Coutclear

count

div16cnt

Q0

Q1

Q2

Q3

Coutclear

CLK

count1