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RECENT DEVELOPMENT AND TESTS ON DEPLETED CMOS SENSORS PROTOTYPES IN
CPPMPatrick Pangaud, Patrick Breugnon, Pierre Barillon, Marlon Barbero, Amr HabibZongde Chen, Siddharth Bhat, Mei Zhao
28 November of 2019
Overview
• Design approches of Monolithic CMOS sensors.
• LFoundry DMAPS prototyping line.
• LF-MONOPIX1, lab and irrad results
• MONOPIX2: Towerjazz and Lfoundry technologies (next step)
• Serial Powering, Shunt-LDO and results
• Summary
28 November of 2019 Recent development on Depleted CMOS in CPPM 2
3
Monolithic CMOS Sensor option
Two design approaches
PROS: Short drift distances� Radiation
tolerant
CONS: Large sensor capacitance � Noise &
speed (power) penalties
PROS: Small sensor capacitance � Low
power consumption and noise
CONS: Long drift distances � Less
radiation hard
Electronics inside charge collection wellElectronics outside charge collection well
� “Small Collection Diode” design: Towerjazz technology
� “Large Collection Diode” design: AMS/TSI and LFoundry
28 November of 2019 Recent development on Depleted CMOS in CPPM
28 November of 2019 Recent development on Depleted CMOS in CPPM 4
LFoundry DMAPS prototyping line
5mm
5m
m
CCPD_LFCCPD_LF
10mm
9.5
mm
LF-CPIX(Demonstrator)
LF-CPIX(Demonstrator)
10mm
9.5
mm
LF-Monopix1(Monolithic)LF-Monopix1(Monolithic)
CCPD_LF
• Subm. in Sep. 2014
• 33 x 125 µm2 pixels
• Standalone R/O for test
• Fast R/O coupled to FE-I4
• Bonn/CPPM/KIT
LF-CPIX (DEMO)
• Subm. in Mar. 2016
• 50 x 250 µm2 pixels
• Standalone R/O for test
• Fast R/O coupled to FE-I4
• New Sensor Guard-Ring
• Bonn/CPPM/IRFU
LF-Monopix1
• Subm. in Aug. 2016
• 50 x 250 µm2 pixels
• Fast column drain R/O
• Bonn/CPPM/IRFU
LF-Monopix2
• Being designed
• 50 x 150 µm2 pixels
• Full height matrix
• Fast column drain R/O
• Bonn/CERN/CPPM/IRFU
20
mm
10mm
LF-Monopix2
• Breakdown @ -280 V => up to ~ 300 µm depletion depth
• Gain 10 -12 µV/e-
• Typical ENC ~ 200 e-
• Tunable threshold down to 1400 e-
– dispersion ~ 100e- after tuning (4bits DAC)
• ToT calibrated with sources: 241Am, terbium
5
LF-MONOPIX1 : Laboratory results
Gain
Noise
ToT vs. Injection Response to sources
I. Caicedo @Bonn
28 November of 2019 Recent development on Depleted CMOS in CPPM
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Setup under proton beam @ CERN PS
6
USB Python Setup in lab @ CPPM
Setup @ CERN PS20 m
IRRAD SETUP
LAB SETUP
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LF-MONOPIX1 results
Proton irradiation
Chip irradiated to 160 Mrad, 80 days room temperature annealing
Measured at -12 ℃, HV = -40 V
NMOS pre-amplifier + Discriminator V2
Noise ~ 250 e-
The threshold dispersion can be tuned to ~ 150e-
Un-irradiated : Breakdown @ -280 V => up to ~ 300 µm depletion
Neutron irradiation10E15neq/cm²
Z.Chen@CPPM
T.Hirono@Bonn
Test beam with ELSA telescope
Next step: the “Monopix2” chips
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- Chip size 2 × 1 cm2
- Pixel size 50 × 150 µm2
- Matrix size 340 × 56
LF_Monopix2TJ_Monopix2
- Smaller pixels- Larger matrix- Analog FE improvement- Pixel layout improvement- Develop digital chip assemblyflow & chip verification flow
- Technological fixes- Larger matrix- Even smaller pixel- Analog FE improvement + Thres. Tuning- Downstream data processing
e.g. data buffering and triggering- Serial Powering Strategy
- Chip size 2 × 2 cm2
- Pixel size 33.04×33.04 µm2
- Matrix size 512× 512
Expected submission: beginning of 2020
Test Structures� Enhanced edgeless Chip Guarding• Bandgap Circuit• Small pixel study ( 50µm x50µm)• New sensor study (>400V)• …
9
Small pixel size approach with LFoundry 150nm technology
250µm 50µm
Current Pixel cross-section (250µm× 50µm x 100µm) Smaller size of the pixel (50µm× 50µm x 50µm)
Motivation to decrease the pixel size- Increase the granularity � Better track parameter resolution, avoid in-pixel pile-up at high particle rates.- Decrease the sensor capacitance � Resulting in low noise and better efficiency detection.
The total Voltage potential ( top tobottom) at 100 V is achieved andthe substrate is fully depleted(50µm)
DNW= +30v
M ZHAO, CPPM
100µm 50µm
28 November of 2019 Recent development on Depleted CMOS in CPPM
SHUNT-LDO regulator: principle� Designed to meet serial powering specifications in CMOS TowerJazz 0.18 µm technology.
Submitted in 8/2018. Received 1/2019.
� The shunt regulator takes a constant current and delivers a regulated output voltage, allows the chips to be polarized serially.
� Serial powering allows great reduction in power losses in cables, as well as significant reduction in material budget (less power, less cables)
� The regulator has a modular structure. One module is composed of a shunt regulator followed by a low drop-out voltage LDO regulator.
Main idea � PWELL & PSUB modules allow
testing individual single
modules.(limited to 10mA)
� The main domain is constituted
of 126 modules divided in 4
groups can deliver up to 2A
� Each domain has its own
Bandgap (internal reference
voltage).
28 November of 2019 Recent development on Depleted CMOS in CPPM 10
A.Habib@CPPM
SHUNT-LDO regulator: main results
• Tests consist in input current scans in various conditions/configurations and monitoring of the voltage input, voltage output and reference voltages (bandGap).
• Performances compatible with simulation for a single module (3 mA to 18 mA) and the Main domain (up to 2 A with cooling).
• Up to 4 chips were tested successfully in serial powering mode. (main domain)
• Applying passive loads on 1 to 4 boards (5 to 33ohms, 50 to 300mA): proper start up of all the boards, whatever the load or the number of boards with load and good regulation of the output voltages for all boards.
• A chip was Xray irradiated up to 125 Mrad and found still functioning with a stable behavior (<<1% decrease) of the input and output voltages with respect to the total dose.
28 November of 2019 Recent development on Depleted CMOS in CPPM 11
Summary
• LF-Monopix1: fully functional demonstrator chip with column drain readout.
– Good breakdown voltage characteristics (-280 V).
– Limited threshold dispersion (can be tuned within 110~148 e- depending on flavor).
– ENC for different flavors is between 190 to 280 e-.
– Good irradiation performances:
• TID=164 MRad and NIEL=3.6× 1015 neq·cm-2 reached
• Limited leakage current increase after 164 MRad.
• Limited ENC increase.
• Serial powering currently/near future: continuation of the serial mode tests (transient, tests with Shunt LDO boards powering chips, tests with mal-functioning boards, etc). Integration in the next large demonstrator TJ-Monopix2.
• Small size pixels in LFoundry 150nm technology are under design and will be tested in 2020
• The value of this technology for future applications makes no doubt
• Work continues with other targets: Future application in ATLAS? CepC, FCC-ee, Belle experiment, future hadron circular collider?
• Strong collaboration with our partners in various framework
(Bonn/CPPM/CERN/KIT/CEA-IRFU collaboration, CERN RD50…)
28 November of 2019 Recent development on Depleted CMOS in CPPM 12
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