crkit rf control winlab – rutgers university date : june 9 2010 authors : prasanthi maddala,...
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CRKit RF Control
WINLAB – Rutgers University
Date : June 9 2010
Authors :
Prasanthi Maddala, prasanthi.m@gmail.com
Khanh Le, kle@winlab.rutgers.edu
SPI – Serial Peripheral Interface
Synchronous serial data link standard.
Operates in master/slave mode.
SPI specifies 4 logic signals
SCLK — Serial Clock (output from master)
MOSI/SIMO — Master Output, Slave Input (output from master)
MISO/SOMI — Master Input, Slave Output (output from slave)
SS — Slave Select (active low; output from master)
Some SPI slave devices do not have a data output port (No MISO) and a few devices use a bidirectional data port (MOSI/MISO).
Data Transmission
- Master configures the clock; uses a frequency < max. freq supported by the slave
- Pulls the slave select low
- During each clock cycle the Master sends a bit on MOSI and slave sends a bit on MISO – not all transmissions result in meaningful rd/wr s.
Clock polarity and phase - In addition to setting the clock frequency, the master must also configure the clock polarity(cpol) and phase(cpha) with respect to the data.
SPI (contd.) At CPOL=0 base value of the clock is zero
For CPHA=0 (first edge), data is read on the clock's rising edge and data is changed on a falling edge
For CPHA=1 (second edge), data is read on the clock's falling edge and data is changed on a rising edge. At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
For CPHA=0, data is read on clock's falling edge and data is changed on a rising edge.
For CPHA=1, data is read on clock's rising edge and data is changed on a falling edge.
This timing applies to both the master and the slave device.
Range Of RF Boards
RF Board No.of RF modules Parts of RF module* No.of SPI Devices
SDR 1 or 2 DiBo 1
WiBo 2 (shared bus)
eSDR 1 DiBo 1
WiBo 2 (shared bus)
FreeBo 3 (shared bus)
WDR 1-4 WDR 14 (shared bus)
*Each “part” of an RF module has its own SPI data bus
OCRP RF Control (R3/ocrp_rf_ctl.vhd)
OCRP RF Control block supports up to 4 RF modules (SDR/ SDR with FreeBo/ WDR/XDR(?))
Generics:
RF_BOARD – SDR/SDRwithFreeBo/WDR/XDR
NO_OF_RF_CARDS - 1 or 2 for SDR, 1 for SDR with FreeBo(eSDR), 1-4 for WDR, 1-4 for XDR
SPI_PER_CARD_SHARED (TRUE by default)
- User can choose to share an spi master among different spi slaves, even when they have independent SPI buses. In SDR, DiBo and WiBo have independent SPI buses. When SPI_PER_CARD_SHARED = TRUE, a single SPI master is used to generate the SPI signals, that are routed to the required bus, using an intermediate block.
- TRUE or FALSE for SDR, SDRwith FreeBo(eSDR),always TRUE for WDR, XDR
Made up of OCRP SPI blocks (up to 4), each of which is controlled through an RMAP interface (RMAP Inf x) as shown above.
OCRP RF Control – RMAP Interface
Signal Name In/Out Width Description
i_rfctl_wr_data In 40 Data to be sent to the SPI device serially – MSB first
i_spi_cycle_len In 6 Length of the SPI communication cycle - Ex: length of valid write data for an SPI wr cycle.
i_sel In 4 SPI device code
i_en In 1 Rising edge on this signal indicates a request for start of SPI transmission
i_mode In 2 SPI mode – cpol&cpha
i_freq_div In 4 Freq. of sclk = Freq. of i_clk / (2 ^ i_freq_div)
i_stall_start In 6 No.of sclk cycles after which sclk has to be stalled. 0 – no clock stalling
i_stall_stop In 6 No.of sclk cycles after which sclk comes out of stall mode and runs normally.
o_rfctl_rd_data Out 32 Data read from the SPI device during an SPI communication cycle.
o_done Out 1 Rising edge on this signal indicates the completion of an SPI communication cycle.
SPI Devices on SDR
Device No. per card
Comm. Cycle width
Type of SPI
DiBo AD9862 (ADC/DAC on DiBo)
1 16 (or 24) 4-wire . Allows 2 word write. MSB(dflt) or LSB first. Max sclk- 16 MHz. Data read on rising edge, clocked out on falling edge. 16 Comm. Cycle width should be used e.g. 8-bit instruction and 8-bit data.
WiBo MAX2829 (RF Transceiver on WiBo)
1 18 3-wire, MSB first. No read. Max sclk-40 MHz(?). Data read on rising edge.4-bit address + 14-bit data
MM74HC595(U2- RF Control Register
on WiBo)
1 8 Can be thought of as a 3-wire SPI device with sclk connected to the shift register clock and cs connected to the storage register clock. Data read on rising edge.No address field, shift register data content is available on CRKit wiki (under SDR section)
Antenna Switches are controlled from the common RMAP directly just like the LEDs – they don’t go through the RF control block
RF Control for SDROCRP RF CTL
(RF_BOARD=SDR, NO_OF_RF_CARDS=1, SPI_PER_CARD_SHARED=TRUE)
OCRP RF CTL (RF_BOARD=SDR, NO_OF_RF_CARDS=2, SPI_PER_CARD_SHARED=TRUE)
OCRP RF CTL (RF_BOARD=SDR, NO_OF_RF_CARDS=1, SPI_PER_CARD_SHARED=FALSE)
OCRP RF CTL (RF_BOARD=SDR, NO_OF_RF_CARDS=2, SPI_PER_CARD_SHARED=FALSE)
By default and preferably SPI_PER_CARD_SHARED = TRUE
RF Control for SDR(Contd.)
Generic SPI
SLAVE_SEL_ENCODED - FALSE NO_OF_SLAVE_SEL_OUTPUTS – 1
DELAY_TO_SLAVE – 1 (since SDR RF inf involves a delay of 1 sclk cycle)
RF Control for SDR(Contd.)
Generic SPI (OCRP SPI – WIBO)
SLAVE_SEL_ENCODED – FALSE NO_OF_SLAVE_SEL_OUTPUTS – 2 DELAY_TO_SLAVE – 0
Generic SPI (OCRP SPI – DIBO)
SLAVE_SEL_ENCODED – FALSE NO_OF_SLAVE_SEL_OUTPUTS – 1 DELAY_TO_SLAVE – 0
Generic SPI
Generics
MAX_SPI_CYCLE_LEN (40 for OCRP)
MAX_SPI_CYCLE_LEN_BITS (6 for OCRP)
NO_OF_SLAVE_SEL_INPUT_BITS (4 for OCRP)
SLAVE_SEL_ENCODED (depends on RF)
NO_OF_SLAVE_SEL_OUTPUTS (depends on RF)
DELAY_TO_SLAVE (depends on RF) - 0 if the SPI master core is directly connected to the slave. If its output is being processed before connecting to the slave, specify the delay involved in terms of sclk cycles.
Generic SPI output
Signal Name In/Out Width Description
o_sclk Out 1 Serial clock to the slave
o_sdi Out 1 Serial data out
i_sdo In 1 Serial data in
o_cs Out NO_OF_SLAVE_SEL_OUTPUTS
Chip selects for slaves – this bus gives individual chip select lines or encoded chip select depending on the SLAVE_SEL_ENCODED generic.
Ex: NO_OF_SLAVE_SEL_OUTPUTS = 4 SLAVE_SEL_ENCODED = TRUE - the master can select up to 15 slave devices (with one idle ?)
o_sclk_x2_ce Out 1 This is a clock enable output with freq. double that of sclk. It can be used by a block between the master and the slaves.
Ex: DELAY_TO_SLAVE = 1, the intermediate block consists of 2 reg. stages which use o_sclk_x2_ce
o_sel Out NO_OF_SLAVE_SEL_INPUT_BITS
SPI master can give multiple chip select lines directly to the slaves or give a single chip select that is further passed through a demux to select among various slaves. o_sel can be used by such a demux. (o_sel = i_sel)
RMAP settings for SDR(rmap_cmn_ctl.xls)
spi_configuration spi_control
Rf_id Stall_start Stall_stop Freq_div mode Cycle_len Sel
AD9862 (DIBO) b0000 b000000 b000000 b0011* b00 b010000(16)** b0000
MAX2829 (WIBO) b0000 b000000 b000000 b0011 b00 b010010(18) b0010
MM74HC595(WIBO-U2)
b0000 b000000 b000000 b0011 b00 b001000(8) b0011
*freq_div = 3. this gives sclk of 12.5 MHz when i_clk i.e., the system clock is 100 MHz
** AD9862 supports two word write, in which case cycle_len = 24. We always use single word write. So, cycle_len = 16
Since the spi_config register remains the same for all the devices on SDR, just write it once.
SPI Devices on eSDR
Device No. per card
Comm. Cycle width
Type of SPI
DiBo AD9862 (ADC/DAC on DiBo)
1 16 (or 24) 4-wire . Allows 2 word write. MSB(dflt) or LSB first. Max sclk- 16 MHz. Data read on rising edge, clocked out on falling edge(cpol = 0, cpha = 0)
WiBo MAX2829 (RF Transceiver on WiBo)
1 18 3-wire, MSB first. No read. Max sclk-40 MHz(?). Data read on rising edge(cpol = 0, cpha = 0)
MM74HC595(U2- RF Control Register on
WiBo)
1 8 Can be thought of as a 3-wire SPI device with sclk connected to the shift register clock and cs connected to the storage register clock. Data read on rising edge(cpol = 0, cpha = 0)
FreeBo ADF4350(LO on FreeBo)
1 32 3-wire, MSB first. No read. Max sclk – 20 MHz. 29 bit data + 3 bit address. Data read on rising edge (cpol = 0, cpha = 0)
MAX7301(FreeBo)
1 16 4-wire, MSB first, Max sclk-26/50 MHz (?). Data read on rising edge, clocked out on falling edge (cpol = 0, cpha = 0)
HMC629(Attenuator on FreeBo)
2(daisy
chained??)
4(8 for 2
devices??)
3-wire, MSB first. Max sclk = 10 MHz. Data read on rising edge (cpol = 0, cpha = 0)REVISIT!!
RF Control for eSDR
OCRP RF CTL (RF_BOARD=eSDR, NO_OF_RF_CARDS=1, SPI_PER_CARD_SHARED=TRUE)
OCRP RF CTL (RF_BOARD=eSDR, NO_OF_RF_CARDS=1, SPI_PER_CARD_SHARED=FALSE)
By default and preferably SPI_PER_CARD_SHARED = TRUE
RF Control for eSDR(Contd.)
Generic SPI
SLAVE_SEL_ENCODED - FALSE NO_OF_SLAVE_SEL_OUTPUTS – 1
DELAY_TO_SLAVE – 1 (since eSDR RF inf involves a delay of 1 sclk cycle)
RF Control for eSDR(Contd.)
Generic SPI (OCRP SPI – WIBO) SLAVE_SEL_ENCODED – FALSE NO_OF_SLAVE_SEL_OUTPUTS – 2 DELAY_TO_SLAVE – 0
Generic SPI (OCRP SPI – DIBO) SLAVE_SEL_ENCODED – FALSE NO_OF_SLAVE_SEL_OUTPUTS – 1 DELAY_TO_SLAVE – 0
Generic SPI (OCRP SPI – FreeBo) SLAVE_SEL_ENCODED – FALSE NO_OF_SLAVE_SEL_OUTPUTS – 3 DELAY_TO_SLAVE – 0
RMAP settings for eSDR(rmap_cmn_ctl.xls)
spi_configuration spi_control
Rf_id Stall_start Stall_stop Freq_div mode Cycle_len Sel
AD9862 (DIBO) b0001 b000000 b000000 b0011* b00 b010000(16)** b0000
MAX2829 (WIBO) b0001 b000000 b000000 b0011 b00 b010010(18) b0010
MM74HC595(WIBO-U2)
b0001 b000000 b000000 b0011 b00 b001000(8) b0011
ADF4350(FreeBo) b0001 b000000 b000000 b0011 b00 b100000(32) b0100
MAX7301(FreeBo) b0001 b000000 b000000 b0011 b00 b010000(16) b0101
HMC629 (FreeBo) b0001 b000000 b000000 b0100 b00 b001000(8) ?? b0110
*freq_div = 3. this gives sclk of 12.5 MHz when i_clk i.e., the system clock is 100 MHz
** AD9862 supports two word write, in which case cycle_len = 24. We always use single word write. So, cycle_len = 16
Since the spi_config register remains the same for all the devices on SDR, just write it once.
SPI Devices on WDR
Device No. per card
Comm. Cycle width
Type of SPI
AT45DB161D(16 MB Data flash)
1 4-wire, MSB first, Max sclk-50/66 (?) MHz. Data read on rising edge, clocked out on falling edge
MAX7301 (IO Expander)
3 16 4-wire, MSB first, Max sclk-26 MHz. Data read on rising edge, clocked out on falling edge.
AD9863 (primary AD/DA)
1 16 , 24 (dual word) 4-wire . Allows 2 word write. MSB(dflt) or LSB first. Max sclk-30 MHz. Data read on rising edge, clocked out on falling edge.
ADS7951 (Aux ADC)
2 16 4-wire, MSB first. Max sclk – 20 MHz. Data read on rising edge, clocked out on falling edge.
AD5624R (Aux DAC)
2 24 3-wire. No read. Max sclk-50 MHz. Data read on falling edge.
MAX2829 (Tx/Rx IF)
2 18 3-wire, MSB first. No read. Max sclk-40 MHz(?). Data read on rising edge.
AD9959 (DDS)
1 Min 16, max 40 4-wire. MSB(dflt) or LSB first. Max sclk-200 MHz. Data read on rising edge, clocked out on falling edge.
Tx/Rx LO (?) 2
RF Control for WDR
OCRP RF CTL (RF_BOARD=WDR, NO_OF_RF_CARDS=n (n = 1/2/3/4),
SPI_PER_CARD_SHARED= x )
By default and preferably SPI_PER_CARD_SHARED = TRUE
OCRP SPI
RF_BOARD = WDR SPI_SHARED = x
PART_OF_CARD = x
RMAP Inf 1 RF1 Inf
OCRP SPI
RF_BOARD = WDR SPI_SHARED = x
PART_OF_CARD = x
RMAP Inf n RFn Inf
.
.
.
RF Control for WDR(Contd.)
Generic SPI
SLAVE_SEL_ENCODED - TRUE NO_OF_SLAVE_SEL_OUTPUTS – 4
DELAY_TO_SLAVE – 0
OCRP SPI
RF_BOARD = WDR SPI_SHARED = x
PART_OF_CARD = x
RMAP Inf 1 RF1 Inf
Generic SPI
o_sclk
o_sdi
o_cs[3:0]
i_sdo
i_rfctl_wr_data[39:0]
i_spi_cycle_len[5:0]
o_rfctl_rd_data[31:0]
o_done
i_sel[3:0]
i_en
i_mode[1:0]
i_freq_div[3:0]
i_stall_start[5:0]
i_stall_stop[5:0]
RMAP Inf 1
o_board_out[5:0]
i_board_in
RF1 Inf
o_sclk_x2_ce
o_sel[3:0]not used with WDR
OCRP SPI
RMAP settings for WDR(rmap_cmn_ctl.xls)
spi_configuration spi_control
Rf_id Stall_start Stall_stop Freq_div mode Cycle_len Sel
AT45DB161D(Data Flash) b0010 b000000 b000000 b0001(50) b00 b0001
AD9863 (AD/DA) b0010 b000000 b000000 b0010(25) b00 b010000(16) b0010
MAX2829(RxIF) b0010 b000000 b000000 b0010(25) b00 b010010(18) b0011
MAX2829(TxIF) b0010 b000000 b000000 b0010(25) b00 b010010(18) b0100
RxLO b0101
TxLO b0110
AD9959(DDS) b0010 b000000 b000000 b0000(100) b00 16 - 40 b0111
ADS7951(Aux ADC1) b0010 b000000 b000000 b0011(12.5) b00 b010000(16) b1000
ADS7951(Aux ADC2) b0010 b000000 b000000 b0011(12.5) b00 b010000(16) b1001
AD5624R(Aux DAC1) b0010 b000000 b000000 b0001(50) b01 b011000(24) b1010
AD5624R(Aux DAC2) b0010 b000000 b000000 b0001(50) b01 b011000(24) b1011
MAX7301(IO Exp 1) b0010 b000000 b000000 b0010(25) b00 b010000(16) b1100
MAX7301(IO Exp 2) b0010 b000000 b000000 b0010(25) b00 b010000(16) b1101
MAX7301(IO Exp 3) b0010 b000000 b000000 b0010(25) b00 b010000(16) b1110
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