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REV:A0_J 2015-12-15
DescripD8042
Resonant(PSR) PWprecision applicatio
In CV
Mode QRAM (Amp(Frequencimprove sCC modeand load Cachieve faCable Drocan provid
D8042
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Typica
ption 2D is a hight (QR) Prim
WM power CV/CC cons.
mode, D80R Control w
litude Modcy Modulatsystem effic, the IC usCC compeast dynamiop Compende excellen
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REV:A0_J 2015-12-15
Pin CoThe pi
Pin Def
Pin No.
1
2
3
4
5,6
7
Absolu
M
nfiguran map is s
finition
. Nam
VDD
FB
NC
CS
HV
GND
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HV PIN D
VDD D
VDD D
CS, BA
FB
RθJA
Maximum J
tion shown as b
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imum R
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m Voltage
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V
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REV:A0_J 2015-12-15
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REV:A0_J 2015-12-15
Electric
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VDD_OF
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REV:A0_J 2015-12-15
On-Chip
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Note1: St
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Note2. Th
Note3. Gu
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REV:A0_J 2015-12-15
PERAT
D8042
Side Regu
high level
applicatio
System S
Before
allows a la
flowing th
voltage D
begins sw
hold-up ca
takes the
TION DE
2D is a hig
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protection
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C bus. Wh
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n features m
Operation
arts to wor
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startup res
hen VDD re
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ontinues to
VDD volta
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ance, mult
ower switch
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sistor charg
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o supply VD
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6
ti mode, hig
h. The built
uitable for
umes only
e used to m
ges the VD
VLO turn-o
urrent is in
DD before
Fig. 1
ghly integr
t-in high pr
offline sma
startup cur
minimize th
DD hold-up
n voltage o
creased to
the auxilia
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recision CV
all power c
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of 12V (typ
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nt Primary
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which
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42D
The
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REV:A0_J 2015-12-15
Once
operating
power los
Quasi Re
In Prim
winding d
timing wa
(QR) trigg
sample/ho
Error Amp
(QR-CVM
the QR-CV
trimmed to
During
for Cable
demagnet
“demagne
voltage; R
Ns and Na
D8042D e
current is
ss.
esonant PS
mary Side
uring the t
veform of
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old (S&H) c
plifier (EA)
M) for CV re
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g the CV s
Drop Com
tization pro
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R1 and R2
a are seco
enters very
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SR CV Mo
Regulation
ransfer of
CV sampli
n D8042D
circuit capt
. The outp
egulation. A
which is de
high accur
ampling pr
mpensation
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ateau”, wh
is the resis
ondary wind
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o be 500uA
odulation (
n (PSR) co
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ng signal,
. When the
tures the e
ut of EA is
A valley is
etermined
acy.
rocess, an
(CDC). Th
shown in F
here Vo an
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ding and a
7
ency FM (
A typically,
(QR-CVM)
ontrol, the
er energy t
demagnet
e CV samp
error signa
s sent to th
selected to
by the load
Fig. 2
internal va
hus, there
Fig.2. Fig.2
d VF is the
r connecte
auxiliary wi
Frequency
which hel
)
output volt
to the seco
tization sig
pling proce
l and ampl
e Quasi Re
o trigger ne
d. The inter
ariable cur
is a step a
2 also illust
e output vo
ed from the
nding resp
Powe
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ps to redu
tage is sen
ondary. Fig
nal (DEM)
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rnal refere
rent source
at FB pin in
rates the e
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e auxiliary w
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) and quas
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SR CV Mo
cycle by the
nce voltag
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n the transf
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the
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i-resonant
nal
nternal
odulator
e output of
e for EA is
g to FB pin
former
or
ward
FB Pin,
f
s
n
REV:A0_J 2015-12-15
WhenEA output
PSR Con
Timing
regulation
increased
Ipp(max),
Refer
demagnet
average o
output cur
regulation
IC operate
output vol
keep VDD
In D80
average o
n heavy loat will switch
stant Cur
g informat
n of the sec
d in CV reg
as shown
ring to Fig
tization tim
output curr
rrent is sho
n reference
es in pulse
ltage at or
D above the
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output curr
ad conditioh to CC Mo
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condary av
gulation and
in Fig.3.
.3 above, t
me (Tdem),
ent Iout. Ig
own in Fig.
e in the Prim
e frequency
below the
e UVLO tu
ratio betwe
ent can be
n, the Modode autom
ulation (PS
FB pin and
verage cur
d approach
the primary
, and switc
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.3. When t
mary Side
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voltage re
urn-off thre
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e expresse
8
de Selectormatically.
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d current in
rent. The c
hing CC re
Fig.3
y peak cur
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he average
Constant C
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shold.
and Tsw i
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r (as shown
nformation
control law
egulation th
rrent, trans
d (Tsw) de
ctance effe
e output cu
Current Mo
mode to co
arget as lon
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Powe
n in “Block
at the CS
w dictates th
he primary
former turn
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urrent Iout
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hat as pow
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econdary
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REV:A0_J 2015-12-15
In the
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To me
consumpt
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conditions
efficiency
power red
Programm
In sm
a cable w
voltage. In
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from full lo
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programm
equation a
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. When the
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charger ap
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switching p
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ary side wi
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ode
ment of ave
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shown in th
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the no-load
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voltage is
shown in F
period, thus
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inding to s
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eraged sys
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he Fig 4.
rates in FM
mode to ach
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Fig. 4
ation (CDC
the battery
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Fig.5) flowi
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loss can b
set voltage
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n the powe
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ption can b
4
C) in CV M
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s of voltage
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rsely propo
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ble loss co
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Powe
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mplitude mo
When norm
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rates in FM
e less than
Mode
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by an inte
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ortional to
sated. As t
will increas
ompensatio
given by
D80
er Mos Electrowww.Po
ng.
tter to GND
o load pow
odulation (A
mal to light l
ation and h
M again for
n 70mW.
d to the ad
the actual b
rnal curren
ivider. The
the output
the load de
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load
high
r standby
dapter with
battery
nt source
e current is
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s
REV:A0_J 2015-12-15
For ex
given by:
Optimize
In D80
requireme
On Chip T
When
temperatu
Audio No
As me
frequency
voltage m
CS peak v
loading to
xample, R1
d Dynami
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ents.
Thermal S
n the IC tem
ure drops t
oise Free O
entioned a
y modulatio
modulation.
voltage mo
o zero load
1=3K Ω ,
c Respon
dynamic re
Shutdown
mperature
to 140 ℃,
Operation
bove, the m
on. An inte
In D8042D
odulation a
ing.
R2=18K
se
esponse p
(OTP)
is over 155
IC will rest
multi-mode
rnal curren
D, the optim
algorithm c
10
Ω , The p
Fig. 5
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5 ℃, the I
tart.
e CV contr
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mized com
can provide
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mbination o
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CS pin rea
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D80
er Mos Electrowww.Po
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et USB ch
when the I
M and AM
lizes CS p
cy modulati
eration fro
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ensation is
arge
IC
provides
eak
ion and
om full
REV:A0_J 2015-12-15
Dynamic
D8042
BJT base
according
based cur
Fig.6
Short Loa
In D80
UVP (0.65
In D80
Protection
VDD Ove
When
cause VD
restart up
damage.
BJT Base
2D drives a
drive curr
g to the pow
rrent. Spec
ad Protect
042D, the
5V typically
042D, whe
n (SLP) mo
er Voltage
n VDD volta
DD fall dow
again. An
e Drive
a power BJ
ent ranges
wer supply
cifically, the
tion (SLP)
output is s
y) after an
en sensed
ode, in whi
Protectio
age is high
wn to be low
internal 28
JT with dyn
s from 12m
y load chan
e base cur
)
sampled on
internal bl
FB voltage
ch the IC w
n (OVP) a
her than 26
wer than V
8V (typical
11
namic bas
mA to 35mA
nge. The h
rrent is rela
Fig.6
n FB pin an
anking tim
e is below
will enter in
nd Zener
6.5V (typica
DD_OFF (
l) zener cla
e drive con
A (typical),
igher the o
ated to CS
nd then co
me (10ms ty
0.6V, the I
nto auto re
Clamp
al), the IC
(typical 6.5
amp is inte
Powe
ntrol to opt
and is dyn
output pow
peak volta
mpared wi
ypical).
IC will ente
ecovery pro
will stop sw
5V) and the
egrated to p
D80
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timize effic
namically c
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age, as sho
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otection mo
witching. T
en the syst
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iency. The
controlled
her the
own in
hold of
ort Load
ode.
This will
tem will
e IC from
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REV:A0_J 2015-12-15
PhysicSOP-7
Symbo
A A1 A2 b c D e
E1 E L θ
cal Dime
ol D
1.27
ensions
DimensionMin
1.350 0.100 1.350 0.330 0.170 4.700
70(BSC)
5.800
0.400 0º
s
ns In Millim
0
005
0.0506
3.800
12
meters Max 1.750 0.250 1.5500.5100.250 5.100 0(BSC)
6.200
1.270 8º
Powe
Dimensio
A A1 A2bc D e
E1 4
L θ
D80
er Mos Electrowww.Po
ns In InchM
1.0.1.0.0.4.
1.2705.
.000 0.
042D
onics Limitedwermos.com
hes Min 350 100 350330170 700 (BSC)
800
400 0º
REV:A0_J 2015-12-15
日期
Date
2015-12
期
e
版
Ver
2-15 A0
版本
sion
0_J
说明
Descript
/
13
ion T
排版
Typeseting
Jasper
Powe
g
工程
Engi
/
D80
er Mos Electrowww.Po
程师
ineer
/
042D
onics Limitedwermos.com
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