design and implementation of vlsi systems (en1600) lecture 30: array subsystems (dram/rom)

S. Reda EN1600 SP’08

Design and Implementation of VLSI Systems(EN1600)

Lecture 30: Array Subsystems (DRAM/ROM)

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN1600 SP’08

Lecture outline

• Last time– Memory periphery (row/column circuitry)– Core cell: SRAM cells

• This time (different core cells)– DRAM cells– ROM cells– Non Volatile Read Write (NVRW) cells

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3T DRAM cell

X Vdd-Vt

BL1Vdd

WWL write

RWL read

BL2 Vdd-Vt V

No constraints on device sizes (ratioless) Reads are non-destructive Value stored at node X when writing a “1” is VWWL - Vtn

M1 M2

M3

X

BL1 BL2

WWL

RWL

Cs

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1T DRAM Cell

M1 X

BL

WL

CsCBL

X Vdd-Vt

WLwrite“1”

BL Vdd

read“1”

Vdd/2 sensing

Write: Cs is charged (or discharged) by asserting WL and BLRead: Charge redistribution occurs between CBL and Cs

Read is destructive, so must refresh after readLeakage cause stored values to “disappear” → refresh periodically

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The bit line is precharged to VDD/2

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How DRAM cells are manufactured?

Trenchcapacitor

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DRAM subarray architectures

sensitive to noise

rejects common mode noise

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ROMs

• Read-Only Memories are nonvolatile– Retain their contents when power is removed

• Mask-programmed ROMs use one transistor per bit– Presence or absence determines 1 or 0

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NOR ROMs

ROM Array

2:4DEC

A0A1

Y0Y1Y2Y3Y4Y5

weakpseudo-nMOS

pullups

• 4-word x 6-bit ROM– Represented with dot diagram– Dots indicate 1’s in ROM

Word 0: 010101

Word 1: 011001

Word 2: 100101

Word 3: 101010

Looks like 6 4-input pseudo-nMOS NORs Dot diagram

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NAND ROM

• All word lines high by default with exception of selected row• No transistor with the selected word -> bitline pulled down • Transistor with the selected word -> bitline remain high

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]

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Non Volatile Read/Write (NVRW) memories

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D

• Same architecture as ROM structures• A floating transistor gate is used

• similar to traditional MOS, except that an extra polysilicon strip is inserted between the gate and channel• allow the threshold voltage to be progammable

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Floating gate transistor programming

0 V

-5 V 0 V

DS

Removing programming voltage leaves charge trapped

5 V

- 2.5 V 5 V

DS

Programming results in higher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection

Process is self-timing- Effectively increases Threshold voltage

Floating gate is surrounded by an insulator material traps the electrons

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Flash Electrically Erasable ROMs

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1source n1drainprogramming

To erase: ground the gate and apply a 12V at the source

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Basic Operations in a NOR Flash Memory―Erase

S D

12 VG

cell arrayBL0 BL1

open open

WL0

WL1

0 V

0 V

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Basic Operations in a NOR Flash Memory―Write

S D

12 V

6 VG

BL0 BL1

6 V 0 V

WL0

WL1

12 V

0 V

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Basic Operations in a NOR Flash Memory―Read

5 V

1 VG

S D

BL0 BL1

1 V 0 V

WL0

WL1

5 V

0 V