design of software package for incorporation of random

DESIGN OF SOFTWARE PACKAGE FORINCORPORATION OF RANDOM LOAD TESTINGAND DATA PROCESSING ON MATERIALS

TESTING SYSTEM MACHINE.

Frederick Martin Blakely

NAVAL POSTGRADUATE SCHOOL

Monterey, California

THESISDESIGN OF SOFTWARE PACKAGE FOR INCORPORATIONOF RANDOM LOAD TESTING AND DATA PROCESSING

ON MATERIALS TESTING SYSTEM MACHINE

Frederick Martin Blakely, Jr.

June 1978

Thesis Advisor: G. H. Lindsey

Approved for public release; distribution unlimited

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4. TITLE (end Subtitle)

Design of Software Package for Incorpor'ation of Random Load Testing and DataProcessing on Materials Testing SystemMachine

5. TYPE OF REPORT ft PERIOD COVERED

Master's Thesis:June 1978

«. PERFORMING ORG. REPORT NUMBER

7. AUTHOR^

Frederick Martin Blakely

• • CONTRACT OR GRANT NUMBERS

9. PERFORMING ORGANIZATION NAME AND ADDRESS

Naval Postgraduate SchoolMonterey, California 93940

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12. REPORT DATEJune 1978

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IB. SUPPLEMENTARY NOTES

19. KEY WORDS (Continue on referee tide II neceeeery end Identity by block number)

Sequence LoadingWORDS (Continue on reveree eld*

Spectrum LoadingFatigue MonitorMicrocomputerMicroprocessor

Materials Testing SystemData Acquisition System

20. ABSTRACT (Continue on arr and Identity by block number)

This thesis describes the software design and implementationof a microprocessor-based, random load drive and data acquisitionsystem on a Material Testing System (MTS) machine.

A microprocessor, combination analog input/output module,magnetic cassette tape recorder, and strain gage network form astrain data acquisition system for recording sequential strainpeaks and troughs on specimens subjected to flight load histories

'™n 1473

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The data will be used to estimate the fraction of the fatiguelife expended in a test specimen.

A high speed digital computer is linked by telephone lineto a microcomputer development system to create the randomiza-tion of fatigue loads specified in Mil Spec 8866 Spectrum Afor use by the MTS machine.

DD Form 1473 UNCLASSIFIEDI o

S/N 0102-014-6601 z> kcu«itv cl*mi»ic*tio«i or tmii Main** m» *"'•"«

Approved for public release; distribution unlimited

Design of Software Package for Incorporationof Random Load Testing and Data Processing

on Materials Testing System Machine

Frederick Martin BlakelyLieutenant Commander, United States NavyB.S., Naval Postgraduate School, 1970

Submitted in partial fulfillment of therequirements for the degree of

MASTER OF SCIENCE IN AERONAUTICAL ENGINEERING

from the

NAVAL POSTGRADUATE SCHOOL

June 1978

ABSTRACT

This thesis describes the software design and implementa-

tion of a microprocessor- based, random load drive and data

acquisition system on a Material Testing System (MTS) machine.

A microprocessor, combination analog input/output module,

magnetic cassette tape recorder, and strain gage network form

a strain data acquisition system for recording sequential

strain peaks and troughs on specimens subjected to flight load

histories. The data will be used to estimate the fraction of

the fatigue life expended in a test specimen.

A high speed digital computer is linked by telephone line

to a microcomputer development system to create the randomiza-

tion of fatigue loads specified in Mil Spec 8866 Spectrum A

for use by the MTS machine.

TABLE OF CONTENTS

I. INTRODUCTION 11

II. STRAIN DATA RECORDING 14

A. HARDWARE COMPONENTS 14

1. Intel System 80/10 Microcomputer 14

2. System 80/10 Monitor Program 16

3. 8255 Programmable Peripheral InterfaceDevice 16

4. SBC-732 Combination Analog Input/OutputBoard 21

5. Memodyne Model 173 Cassette Recorder 21

B. SOFTWARE PACKAGE 24

1. Tape File Format 24

2. The Write Program 27

a. Write a Record Subroutine 28

b. Write a Character Subroutine 28

5. The Read Program 29

a. Read a Record Subroutine 29

b. Read a Character Subroutine 30

4. ADC and DAC Programming 30

a. General Description 30

b. Read/Write Formats 32

c. Command Register Format 32

d. Status Register Format 32

e. ADC Data 56

f. DAC Data 36

III. RANDOM LOAD TESTING 39

A. LOAD SEQUENCE RANDOMIZATION TECHNIQUE 3 9

B. RANDOM LOAD ACCURACY AND FORMAT 39

1. 8080A CPU Double Precision Accuracy 40

2. ADC and DAC Data Word Format 40

3. Conversion of Loads to Voltages 41

4. Example 43

C. COMMUNICATIONS LINK BETWEEN IBM- 3 60AND MDS-8 00 VIA TELEPHONE LINE 4 4

1. CP/CMS Control Program- 67/CambridgeMonitor System 44

2. MDS-800 Microcomputer Development System 44

3. Disk Operating System 44

4. Hexlink Program 45

5. CP/CMS DumpF Command 46

D. PUNCHING LOAD DATA ON PAPER TAPE 47

1. CP/M 47

2. CP/M Dump Command Modification (Dumpl) 48

3. Punching Paper Tape Command 48

IV. SYSTEM OPERATION 49

A. SUBROUTINES 49

1. VALDT Subroutine 49

2. SGLCHN Subroutine 50

3. HEADING Subroutine 51

4. Display File Subroutine (DSFILE) 53

5. RAMP Subroutine 55

B. EXECUTIVE ROUTINES 56

1. MAIN Executive 56

2. SORCLD Executive 58

3. LOAD Executive 60

4. ADCCHN Executive 61

5. ADCMXM Executive 62

6. MASTER Executive 62

7. READ Executive 63

C. PRELIMINARY SYSTEM QUALIFICATION 64

1. DC Calibration 64

2. Incremental DC Volt Step Test 64

3. Sinusoidal Signal Reconstruction 65

4. Peak and Troughs Test 65

5. Driver Test 65

V. CONCLUSIONS AND RECOMMENDATIONS 6 7

APPENDIX A: Glossary 68

APPENDIX B: Memory Map 7

APPENDIX C: Source Listings 71

APPENDIX D: Hexlink Program 108

APPENDIX E: Randomized Mil Spec 8866 Spectrum A Loads- -128

LIST OF REFERENCES 151

INITIAL DISTRIBUTION LIST 132

LIST OF TABLES

I. Features of Peripheral Interface Lines 17

II. Port Assignment 8255 20

III. SBC 732 Board Specifications 23

IIIA. SBC 732 Analog Output/Input Pin Assignment 31

IV. SBC 732 iMemory Address Assignments 33

V. Programmable Gain vs. ADC Full-Scale Range 34

VI. Frequency of Maneuver Loads 40

LIST OF FIGURES

1. Materials Testing System (MTS) 12

2. Single Board Computer 80/10 15

3. 8255 #2 Mode Control Word 19

4. SBC-732 Combination Analog- Input/Output Board 22

5. Memodyne Model 173 Cassette Recorder 25

6. Tape File Format -26

7. MUX Address and Gain Format -34

8. Command Register Format -35

9. Status Register Format 35

10. ADC Data Format -37

11. DAC Data Format -37

12. ADC and DAC Data Word -41

13. SBC-80/10 Front Panel with ADC and DACBNC Connectors 60

ACKNOWLEDGEMENTS

The author would like to express his sincere appreciation

to all those who provided background material and technical

information in the microprocessor and computer science fields.

Particular thanks are due to Dr. Gerald H. Lindsey, thesis

advisor, for his direction and counsel; to LT. Cleveland D.

Englehart, USN, for his technical knowledge and software

programming techniques; to Mr. Ted Dunton, Chief Technician,

for his tireless and cheerful troubleshooting; to Mr. John

Drakeford, Industrial Control Project Manager, and Mr. Tom

Rossi, System Design Engineer, Intel Corporation, for their

aid in software application and product support.

Most of all, thanks to my family for their endless support

and understanding.

I. INTRODUCTION

With the greater complexity and cost of new weapon systems,

together with the general economic pressures to control expend-

itures, there is an urgent need to obtain maximum use from the

operational lives of aircraft.

Currently, fatigue monitoring of naval aircraft is based

on the total number of g readings recorded at four selected

levels by an exceedence level counting accelerometer . Using

microprocessors, it will soon be possible to record in sequence

each maximum and minimum load level experienced by an aircraft.

The data collected can be used to monitor the fatigue life of

a structure via the determination of damage accumulated at a

point found to be critical in a structural test of a prototype.

The objective of this research work was to design a soft-

ware package to incorporate random load testing and data pro-

cessing on a Materials Testing System (MTS) machine (Figure 1).

The random load history would come from either monitored flight

data or computer generated sequences.

The entire software package was written in two phases.

The first phase consists of software for a single channel

strain data acquisition system. This acquisition system is

designed to process and record in sequence data originating

from strain gages located at fatigue critical points. The

data obtained will be sequential peaks and troughs that will

be used to estimate the fraction of the fatigue life of the

structure that has been expended.

Figure 1 Materials Testing System (MTS)

The system developed is composed of two major subsystems:

the Write subsystem and the Read subsystem. The Write sub-

system is tasked with the collection of data. It makes use

of a microprocessor, analog to digital converter, a magnetic

tape recorder, and a strain gage network to monitor strain-

generated signals, identify significant events and record the

collected data. The Read subsystem is tasked with the retrieval

and display of the data from the Write subsystem recorder.

Phase two of the software package consists of software

necessary to incorporate randomization of MIL SPEC 8866

SPECTRUM A loads into a material testing system.

This system creates random loads on the IBM 360 computer,

transmits load data via telephone line to the MDS 800 micro-

computer development system, and finally punches the load data

on punch paper tape, which supplies the random load sequence

for the MTS.

The entire software package represents a smooth interface

between the high level Fortran language used by the IBM system

360 and the low level assembly language of the system 80/10

microcomputer

A glossary of terms commonly used in the instrumentation

engineering, data processing and computing disciplines is

presented in Appendix A.

II. STRAIN DATA RECORDING

A. HARDWARE COMPONENTS

1 . Intel System 80/10 Microcomputer

The Intel 80/10 Microcomputer System is self-contained,

utilizing the SBC-80/10 single board computer. The standard

system 80/10 contains IK (IK - 1024 bytes) of 8-bit read/write,

Random Access Memory (RAM). Sockets for up to 4K of 8-bit

words of non-volatile Read-Only-Memory (ROM) are provided in

the system. The 8-bit Intel 8080A CPU is the central proces-

sor for the system 80/10. [Figure 2].

The 8080A contains six 8-bit general purpose registers

and an accumulator. The six general purpose registers may be

addressed individually or in pairs, providing both single and

double precision operators.

The 8080A has a 16-bit program counter, which allows

direct addressing of up to 64K bytes of memory. An external

stack at memory location 7FFFH may be used as a last in/first

out stack to store the contents of the program counter, flags,

accumulator, and all of the six general purpose registers. A

16-bit stack pointer addresses the external stack. This pro-

vides subroutine nesting that is bounded only by memory size.

The system 80/10 contains 48 programmable parallel

input/output (I/O) lines implemented by two Intel 8255 Pro-

grammable Peripheral Interface (PPI) devices. Software is

used to configure the I/O lines in combinations of undirect ional

3a,6ou

fi•HCO

•Htin

parts and bidirectional parts. Section 3 will discuss in

detail the setup of the Intel 8255 PPI devices used for this

thesis

2. Svstem 80/10 Monitor Program

A standard feature of the system 80/10 is a software

monitor, which is programmed in two ROM's. The monitor pro-

vides two basic capabilities: (1) it accesses console input/

output routines as well as paper tape input/output control

software; (2) the monitor, along with a teletype (TTY) or a

cathode ray tube (CRT) , provides the user with a console that

furnishes immediate access to both memory and registers. It

also has control commands to begin execution, display, or

alter the contents of the memory or registers. The system

monitor ROM's are positioned in the first two ROM sockets of

the SBC-80/10 computer, occupying memory locations to 2048.

A more complete description of monitor commands is given in

Ref . [1] .

8255 Programmable Peripheral Interface Device

The peripheral interface section of Group 2 contains

24 peripheral interface lines, buffers, and control logic.

The characteristics and functions of the interface lines are

determined by the operating mode selected under program con-

trol; three modes of operation may be selected:

MODE - BASIC INPUT/OUTPUT

MODE 1 - STROBED INPUT/OUTPUT WITH INTERRUPT SUPPORT

MODE 2 - BIDIRECTIONAL BUS WITH INTERRUPT SUPPORT

Table I lists the basic features of the peripheral

interface lines within each mode group. This thesis will

utilize the mode basic input/output mode only.

TABLE I

Features of Peripheral Interface Lines

Mode — Basic Input/Output

Two 8-bit ports

Two 4-bit ports with bit set/reset capability

Outputs are latched

Inputs are not latched

Mode 1 — Strobed Input/Output

One or two strobed ports

Each Mode 1 port contains:

8-bit data port

3 control lines

Interrupt support logic

Any port may be input or output

If one Mode 1 port is used, the remaining 13 lines

may be configured in Mode 0.

If two Mode 1 ports are used, the remaining 2 bits

may be input or output with bit set/reset capability.

Mode 2 — Strobed Bidirectional Bus

One bidirectional bus which contains:

8-bit bidirectional bus supported by Port A

5 control lines

Interrupt support logic

Inputs and outputs are latched

Tho remaining 11 lines may be configured in either

Mode or Mode 1.

The mode definition control word shown in Figure 3

is used to specify the configuration of the peripheral inter-

face lines on the 8255 device. When the opcode field (bit 7)

of the control word is equal to one, the control word is in-

terpreted by the 8255 as a mode definition control word. The

system softwear may specify the modes of port A and B inde-

pendently as input or output when in mode 0. Port C may be

treated as input only, output only, or divided into two por-

tions of input and output, as required by the port A and port

B mode definitions.

In group 2 the 8255 chip, with the control register

address of EBH, was configured through the use of the mode

control word interface as:

PORT A - MODE OUTPUT

PORT B - MODE INPUT

PORT C - MODE INPUT (STATUS)

PORT C - MODE OUTPUT (CONTROL)

The following mode control word was used:

1000 0011 (Binary)

8 3 (Hex)

The assembly language program is:

CONTROL EQU OEBH; 8255 #2 ADDRESS

MVI A,83H ; move control word into ACCM

OUT CONTROL ; output to address OEBH

(control word)

-- port C lower, input

- port B, input

select mode for port B,port C lower

-- port C upper, output

— port A output

- select mode 00 for port A,port C upper

- enable system

Figure 3. 8255 #2 Mode Control Word.

Now, let's take a closer look at port C since its

functions are split between control and status monitoring.

The address of port C is 0EAH, as shown in Table II. For

example, 11110000, or 0F0H, will put the recorder in the Write

mode and start writing characters. The assembly language

program follows:

PORT C EQU 0EAH; PORT C

MVI A,0F0H ; PORT C

OUT PORT C ;

ADDRESS

CONTROL WORD

TABLE II

Port Assignment 8255

SBC-80/10 Cable (Tape)ADDR J2 DB2 5 Memodyne Name/Function

Port A 43 2 M 2°

45 3 N 21

47 4 U 22 DATA TO

49 5 V 23

51 6 w 2* RECORDER39 7 X 2

EB 37 8 Y 26

35 9 19 27

Port B 05 14 2 2°

7 15 C 21

9 16 F 22 DATA FROM

3 17 H 23

11 18 J 21

* RECORDER13 19 K 2

E9 15 20 10 26

17 21 11 27

STATUS

Port C 25 25 20 STATUS23 10 8 TAPE SYNC

EA21 11 S CIP19 12 17 BEOT

CONTROL

Port C 27 13 A LWD FWD

12RWDSTART/STOP

33 24 22 WR/RD

1 14 GND

SBC-732 Combination Analog Input/Output Board

The SBC-732 is an analog input/output subsystem which,

under microprocessor control, performs the basic functions of

data acquisition of analog inputs and controlled analog output

signals [Fig. 4] . There are three programmable modes of oper-

ation for the acquisition of analog inputs: repetitive single

input, sequential channel scan input, and random channel input

The 732 multiplexer can accommodate 8 differential or

16 single-ended analog input channels. All input channels

are pretested to +_28V by clamping diodes and fusible current-

limit resistors.

The selected differential or single-ended input is

applied to the analog- to-digital connection (ADC) via a pro-

grammable gain amplifier, which under program control was

selected to provide a gain of 1. The ADC is a 12-bit, 35.7

microsecond, successive approximation device with an internal

sample-and-hold (S/H) amplifier. The ADC was jumper selected

for +_10V full scale inputs. The A/D conversion process was

initiated by program command.

Each of the two 12-bit non-isolated digital - to- analog

converters (DAC's) were configured for +10 volts full-scale

voltage output. Table III contains SBC-732 board specifica-

tions .

Memodyne Model 173 Cassette Recorder

The recorder is a memodyne model 173 magnetic tape

recorder. The model 173 is a parallel input/output, read/

write unit designed to be compatible with ASCII requirements.

d<eo•H+->

TABLE III

SBC-732 Specifications

Power Requirements Vcc

- + 5V 5S

I„„ = 2 . 5A maximumcc

Physical Characteristics:

Width:

Depth:

Thickness

Weight:

34.48 cm (12.00 inches)

17.15 cm (6.75 inches)

1 . 27 cm ( . 50 inches)

567 gm (20 ounces)

Addressing Reserves a block of 16 contiguous memory locationsrelating to a jumper-selectable memory baseaddress

Analog Input:

Number of Channels

Resolution

S/H Aperture Time

S/H Uncertainty

Overall Accuracy (25°C)

A/D Conversion Speed

8 differential or 16 singleended; expandable to 16 dif-ferential or 52 single-ended

12 bits (.025%), bipolar orunipolar

< 20 nanoseconds

5 nanoseconds

0.05% FSR + 1/2 LSB (Gain 2)

28 KHZ

Throughput

Sample Rate (single channel) 17 KHZ

Channel-to-Channel Rate 16 KHZ

Analog Output:

Number of Channels

Resolution

Two, non-isolated

12 bits, bipolar or unipolar(jumper selectable)

Voltage Output Characteristics:

Output Ranges

Output Current

Output Impedance

+5V, + 10V, +5V, +10V(jumper selectable)

5 MA @ +10V

. 2 ohm

When writing, this mode accepts 7-bit parallel input data

and formats the data word into serial format suitable for

recording on the tape. When reading, a start command will

cause one 8-bit character to be read and will present this

data in parallel format at the output. Figure 5 shows the

cassette tape recorder front panel and controls.

B. SOFTWARE PACKAGE

1 . Tape File Format

The purpose of the file format is to control input

and output data in a manner that will permit the determination

of the quantity and the accuracy encountered in the Read/Write

operations

All data stored on the tape will be arranged in the

file format illustrated in Figure 6. The three leading

zeroes in each record of the file provide the means for a

simple test to determine that the file type character is

approaching. The next character after the leading zeroes is

the file type character. This type of designation enables

the specific identification of each file. Record type 1

refers to source data that was obtained from actual flights;

on the other hand, record type 2 refers to source data derived

from computer generated flight loads. The next character in

a record is the record length, which indicates the quantity

of bytes which comprise the remainder of the record (excluding

the terminal checksum character) . The record length character

permits the writing of specific length Write/Read routines

«#^#*^

LeadingZeroes

RecordType

RecordLength Data Checksum

000 01 81H Julian Date

Aircraft Type

Configuration

Gross Weight

r Miss ion

000 02 94H MTS Scale Factor CS

Limit Load

• Cross SectionalArea

Random Number Seed

Strain Data Follows

000 03 (OO-FF)Hex (Strain Gage Data) CS

000 04 ODH End of File CS

Figure 6. Tape File Format

and ensures that the proper quantity of data is transferred

to/from the tape. The final character in a record is the

checksum, which is a Modulo 257 sum of the data in the record

between the file length character and the checksum itself.

As the data are written on the tape, the checksum is calculated

and then written at the end of each record to which they per-

tain. As the data are read from the tape, a new checksum is

calculated, computed with the previously calculated checksum

and, if an error exists, a CHECKSUM ERROR message is printed.

This error would indicate that a difference exists between the

data that were written on the tape and those which were read

from the tape. A rewind and rerecord operation is then at the

discretion of the operator.

2 . The Write Program

The modularity of the design of the program permits a

very simple conceptual construction of the Write main program.

Subroutines are called to perform the "work" of the program,

while the main program itself acts as the "manager." The

operation of the main Write program is as follows:

The type of source load data, actual or simulated,

determines whether record type 1 or 2 is accepted into RAM.

The recorder head is moved onto the tape oxide in preparation

to write. For each file, only three records are written

the tape. The tape is stopped after the fourth record is

written. The system 80/10 returns to monitor for future

control of the operation.

a. Write a Record Subroutine

The "write a record" subroutine (WRREC) writes

the individual records on the tape. Operation of the sub-

routine is as follows: 1) The address in RAM that starts

the record data chain is loaded into the H,L register pair.

2) The record type character is loaded into the D register.

3) The record length is loaded into the C register. 4) The

subroutine is called. 5) A gap is put on tape for the phys-

ical separation of records. 6) The checksum is initiated.

7) The three leading zeroes, file type and file length are

written on the tape. 8) One data byte is written on the

tape. 9) The checksum is updated. 10) The record length

counter is decremented. 11) If the record counter has not

reached zero, indicating that all data have been transferred,

the program continues looping through step 8. If the record

counter has reached zero, all data have been transferred; and

12) the checksum is written on the tape. 13) Finally, another

gap is put on the tape for further physical separation of files

b. Write a Character Subroutine

This subroutine (WRCHAR) takes a byte of data from

the accumulator and writes it on the tape. The operation of

the "write a character" subroutine is as follows: 1) the tape

recorder head is positioned near the tape oxide; 2) a write/

start signal is sent to the tape recorder control port (the

signal must be present for approximately one millisecond for

the recorder to recognize it); 5) the status bit is sampled:

if it is high, the recorder is still writing and the sampling

continues; when the status bit goes low, the recorder has

completed the Write operation; and 4) a five millisecond delay

is activated to ensure that the tape recorder is prepared to

accept another write/start signal initiating the writing of

the next data bit.

5 . The Read Program

The Read main program also "manages" the Read sub-

routines. The operation of the Read main program is as

follows: 1) the tape recorder head is positioned near the

tape oxide; 2) the RAM address at which the tape data will be

stored is loaded into H,L register pair; 5) all records on

the tape are read with each record type character being checked

for the "end of file" record character (in this program, record

type 4 indicates the end of the file) . If the file type 4 is

sensed, 4) the "end of file" message is printed and the 80/10

is returned to the calling program,

a. Read a Record Subroutine

This subroutine reads a record from the tape,

stores the data in RAM, and outputs the data to the output

device (CRT or TTY) . The operation of the READ A RECORD sub-

routine is as follows: 1) the RAM storage address is loaded

into the H,L register pair; 2) incoming data is checked and

rejected until the input of the record leading zeroes; 3) the

leading zeroes are noted, but rejected as data; 4) the record

type character is accepted as the first bytes of significant

data. If the record type is 4, the END OF FILE message is

printed and 80/10 is returned to monitor. If the record type

is not 4, then 5) the record length character is accepted,

indicating the length of data to be read from this record.

6) As each data byte is read, stored and output to CRT or

TTY, a new checksum is calculated. After all data have been

read, 7) the new checksum is compared with the previous check-

sum stored on tape, and if in error the CHECKSUM ERROR message

is printed. If no error, 8) control is returned to the calling

program.

b. Read a Character Subroutine

This subroutine takes a byte of data from the tape

and moves it into the accumulator. The operation of the READ

A CHARACTER subroutine is as follows: 1) the read/start sig-

nal is sent to the tape recorder control port for at least

one millisecond; 2) the tape SYNC bit is sampled until it is

high, indicating that the tape recorder has commenced reading;

3) the tape SYNC bit is sampled until it is low, indicating

that the tape recorder has completed the Read operation; 4) a

5-millisecond delay is provided to ensure that the tape re-

corder is ready to accept the next read/start signal for the

next character; 5) the byte of data is sent from the tape

recorder output port to the accumulator; 6) control is returned

to the calling program.

4 . ADC and DAC Programming

a. General Description

This section illustrates and describes the com-

mand, status, and data formats for programming the ADC and

DAC channels. A more complete description can be found in

Ref. [2]. Also see Table IIIA for pin assignments.

TABLE IIIA

SBC 732 ANALOG OUTPUT/ INPUTPIN ASSIGNMENT

Edge Connector/Pin Number Function EIA Comments

Jl/36 DAC 1: V «.out19

Jl/39 DAC 1: Analog Rtn Analog

Jl/42 DAC )3: V +H out18 Output

Jl/45 DAC 0: Analog Rtn

J2/4 Channel 1

J2/6 8 9

J2/8 1 2

J2/10 9 10

J2/12 2 3

J2/14 10 11

J2/16 3 4 Analog

J2/18 11 12 Input

J2/20 4 5

J2/22 12 14

J2/24 5 6

J2/26 13 13

J2/28 6 7

J2/30 14 16

J2/32 7 8

J2/34 15 17

J2/3-33 Analog Rtn 21-25

J2/39-45 Digital Common 1

J2/40 Clock Out 2

J2/42 Ext. Trigger In 3

J2/44 EOC Trigger Out 4

J2/46 EOS Status Out 5

J2/48 Analog Return 6

The system 80/10 communicates with SBC-732

through a sequence of Read and Write commands. Table IV lists

the individual commands associated with the SBC-732 ADC and

DAC ' s . These commands are addressed as specific memory loca-

tions relative to the memory base address F700H. If, for

example, the memory base address is F700, the address M + A

implies the specific memory address F70A.

b. Read/Write Formats

The multiplier (MUX) address and gain format is

shown in Figure 7. Bits 0-4 select the desired channel.

Starting channel for a random ohms, bit 5 is ignored, and

bits 6-7 select the programmable gain amplifier (PGA) input

voltage gain. Table V lists programmable gain versus ADC

full-scale range available to SBC-732 board.

The MUX address and gain are established by per-

forming a Write to M+ 1; the MUX address and gain may be

verified by performing a Read of M + l.

c. Command Register Format

The command register, which is associated entirely

(either directly or indirectly) with the A/D conversion pro-

cess, is loaded by a Write command to M+ 0. Bit must be

set before the A/D conversion can occur. The command register

format is shown in Figure 8.

d. Status Register Format

The contents of the status register, which con-

tains the status of the ADC and the function associated with

the A/D conversion process, are assessed by a Read command

TABLE IV

SBC -73 2

MEMORY ADDRESS ASSIGNMENTS

MEMORYADDRESS

COMMAND FUNCTION

M + Write Load Command Register

M+0 Read Read Status Register

M+l Write Load MUX Address Register and Gain Register

M+l Read Read MUX Address Register and Gain Register

M+2 Write Load. Last Channel Register

M + 3 Wnte Clear Interrupts

M + 4 Read Read Lower Byte of ADC Value

M + 5 Read Read Upper Byte of ADC Value

M + 8 Wnte Output Lower Byte for DACO to Hold Register (HR)

M + 9 Wnte Output Upper Byte to DACO (DACO-HR automatically)

M + A Write Output Lower Byte for DAC1 to Hold Register (HR)

M+B Write Output Upper Byte to DAC1 (DACl—HR automatically)j

TABLE V

Programmable Gain Vs. ADC Full-Scale Range

ADC FULL-SCALE RANGEGAIN

+ 5V + 10V + 5V + 10V

+ 5V + 10V + 5V + 10V XI

+ 2.5V + 5V + 2. 5 + 5V X2

+1. 25V + 2.5V +1.2 5 + 2.5 X4

+0. 625V +1.25V + 0.6 2 5V + 1.25 X8

487-10

21 2°

7 6 5 4 3 2 1

X8 1 1

GAINSELECT

X CHANNELSELECT(lof 32)

Figure 7. MUX Address and Gain Format.

ENABLE EOC INTERRUPT

ENABLE EOS INTERRUPT

CLEAR BUSY STATUS

*ttttA

ENABLE EXTERNAL TRIGGER

ENABLE AUTO- INCREMENT—ENABLE CONVERSION

Figure 8. Command Register Format

CONVERSION DONE

SCAN DONE

EOC INTERRUPT ENABLED-

EOS INTERRUPT ENABLED

BOARD BUSY

EXTERNAL TRIGGER ENABLED

AUTO- INCREMENT ENABLED —CONVERSION ENABLED

Figure 9. Status Register Format

to M + 0. As shown in Figure 9, bits through 5 essentially

verify the last command word written into M+ 0. Bit 3 (BOARD

BUS), however, has a special function. The first time a Read

command to M + is performed after the busy status bit is

cleared by a Write to M+ 0, the BOARD BUSY bit will be read

as a "0". Each time thereafter that the status register is

read, the BOARD BUSY bit will be returned true. This func-

tion is useful for multiprocessor systems in which two or

more processors are sharing the SBC-732. The BOARD BUSY bit

can be cleared only by Write command to M + with bit 3 clear

Bits 6 and 7 are used primarily in non- interrupt driven

programs to determine when valid ADC data are ready to be

read (CONVERSION DONE).

e. ADC Data

After the A/D conversion is complete, the data

word is obtained by a Read command to M + 4 and a Read command

to M+ 5, as shown in Figure 10. M+ 4 contains the ADC bits

through 3 and M+ 5 contains ADC bits 4 through 11.

ASSEMBLY LANGUAGE:

ADDATA EQU BASE + 4

LHLD ADDATA ; LOAD HL REG WITH

ADC DATA WORD

f. DAC Data

No program control other than the output data

word is required by the two DAC channels. For DACJ3, a Write

command must be given first to M + 8 to load the low byte into

M + 5 HIGH BYTE M + 4 LOW BYTE

76543210

ADCBIT 11

1ADCBIT 4

ADCBIT 3

5 4 3 2 1

A ' ^—ZEROS

ADCBIT

Figure 10. ADC Data Format

M + 9 DAC - HIGH BYTE

M + B DAC 1 - HIGH BYTE

M + 8 DAC - LOW BYTE

M + A DAC 1 - LOW BYTE

76543210A A

DACHT 11

7 6 5 4 3 2 1 Q

A -— ^

DAC DAC DACBIT 4 BIT 3 BIT

Figure 11. DAC Data Format

the Hold Register, and the Hold Register maintains the four

least significant bits valid at the DAC0 input; then a Write

command to M+ 9 presents the high byte to the DAC0 input.

DACJ9 automatically makes the conversion of the input data

when the Write command to M + 9 occurs.

The operation of DAC1 is identical to that of

DACJ0 except M + A is used for the low byte and M + B is used

for the high byte. Figure 11 illustrates the DAC data format.

ASSEMBLY LANGUAGE:

DACPFS EQU OFFF0H

LXI H, DACPFS

CALL WRDAC0

DAC POSITIVE FUL1 SCALE

LOAD HL FFF0H

WRDAC0: SHLD DACJ0 ; OUTPUTS POSITIVE FULL

RET (FFF0)

III. RANDOM LOAD TESTING

This section deals with the load sequence randomization

technique developed by Lt. John Scott Atkinson, Jr.,[Re£. 3].

Fortran arithmetic declarations and manipulations required for

8080 CPU compatibility; the communications interface program

called "HEXLINK" which links the MDS-800 to the IBM-360 via

telephone line; and the preparation of paper tape of random

load data using modification of DUMP program written by

Digital Research for CP/M.

A. LOAD SEQUENCE RANDOMIZATION TECHNIQUE

The load sequence randomization technique uses the computer

library subroutine RANDU to place 10 percent of the MIL-SPEC

8866, spectrum A positive loads [Table VI] in a random order.

Each of the positive loads is paired with a minimum load of

11 percent limit load, representing 1-g flight. During the

randomization, each load has an equal probability of selection.

A counter restricts the number of times a value is selected

to the number of occurrences of the particular load level in

MIL spectrum A.

B. RANDOM LOAD ACCURACY AND FORMAT

The accuracy and format of the random loads were dictated

by the 16-bit double precision accuracy of the 8080A CPU and

the ADC and DAC 12-bit data word format.

TABLE VI

FREQUENCY OF MANEUVER LOADS

Number of Times per Thousand Hoursthat Load Factor is Experienced

Percent of MaximmrSymmetrical Limit

l (Positive)Load Factor

Fl ight Maneuver LoadSpectrum A

17,000

45 9,500

55 6,500

65 4,500

75 2,500

85 1,360

95 440

105 150

115 40

125 16

Total .42,006

1. 8080A CPU Double Precision Accuracy

Since the 8080A CPU can handle 16-bit binary data,

the loads generated in Fortran algorithm were limited to

16-bit accuracy by simply declaring them INTEGER *2.

ADC and DAC Data Word Format

The ADC and DAC data word is formed using double

precision (2 bytes), referred to as the high byte and the low

byte. The 12 most significant bits are used in the conversion

process, thus leaving the least significant 4 bits of the

low byte with zeroes. This nibble was used to indicate the

designated channel (0-15). The ADC and DAC word is shown in

figure 12.

HIGH BYTE LOW BYTE

B r : 11 Bit 4 Bit C

Channel No.

Figure 12. ADC and DAC Data Word.

3 . Conversion of Loads to Voltages

The next step in the analysis was to correlate a

load generated with a corresponding voltage. The MTS requires

+10 volts to operate its four selectable load ranges. The

load ranges are: +10,000, +20,000, +50,000, and +100,000 lbs.

The range is selected by estimating the maximum stress expected

to occur. For example, if the 20,000 lb. range is selected

and +10 volts is applied, then the MTS will produce a 20,000

lb. load. Using 12 bits, the largest number that can be rep-

resented is 16 x 16 x 16 = 4096 parts. This means that if the

voltage range is +_10 volts, then there would be 4096 incre-

mental steps between the voltage limits. Since our investi-

gation will deal with positive loads only (0 to +10 volts),

the incremental range is now 2048 steps. In other words,

there are 204.8 steps per volt in the - 10 volt range.

Now, to determine the number of steps required for

a specific voltage supply, multiply the voltage by 204.8

steps/volt: for example, 9.375 volts is equivalent to 1920

Next, the number of steps is represented in a 16-bit

pattern. Continuing with our example, the 1920 steps have

the following 16-bit pattern.

BYTE 1 BYTE 2

111 10 = 1920

Since the analog converter data word used the three

most significant nibbles of the combination of Byte 1 and

Byte 2, the above 16-bit pattern is shifted 4 bits to the

left. This is accomplished by multiplying the above 16-bit

pattern by 16. The 16-bit pattern now is as follows:

111 10 '

The representation of volts by the ADC or DAC is

8000H or (1000 0000 0000 0000) in 16-bit binary pattern.

This means that the least value of the most significant nibble

is eight (1000) . This means that 1 is added to the most sig-

nificant bit, giving the following 16-bit pattern:

I1111 110 0000, 0000

The same results can be achieved by adding 32,678 to

the 16-bit pattern.

The Hexdecimal representation of the above 16-bit

binary number is F800. In summary, if F800 is outputted via

DAC channel, it will produce a voltage of 9.375 volts, which

corresponds to a load of 18,750 lbs. on the 20,000 lb. MTS

load range.

4 . Example

Suppose the critical stress analysis of a specimen

2with 0.9 in. cross -sect ional area had a limit load of 14,000

PSI . The largest load in the spectrum will be

1.25 x 14,000 x .9 = 15,750.

Selecting the 20,000 lb. load range and multiplying by 10

ll'7nn°n lu

S' x 10 volts = 7.875 volts.

20, 000 lbs

In other words, 7.875 volts is equivalent to 15,750 lb. load,

when the 20,000 lb. range is selected on the MTS.

To determine the number of steps from zero, multiply

by 204.8 steps/volt, and add 2048 (difference between 8000H

and 0000H. The result is 3660.8 steps with respect to 0000H.h

Converting to hexidecimal gives EaDX, where X designates

channel number.

Now that the random load data have been created and

stored in a vector, a technique for transmitting the data to

the microcomputer development system needs to be considered.

C. COMMUNICATIONS LINK BETWEEN IBM- 3 60AND MDS-8 00 VIA TELEPHONE LINE

1. CP/CMS Control Program- 67/Cambridge Monitor System

The CP-67/CMS time-sharing system consists of two

independent components: the control program (CP67, or CP

for short) and the Cambridge monitor system (CMS) . The control

program creates the time-sharing part of the system to allow

many users to access the computer simultaneously. The Cam-

bridge Monitor System provides the conversational part of the

system to allow a user to monitor his work from a remote

terminal

CMS gives the user a full range of capabilities - -

creating and managing files, compiling and executing problem

programs, and debugging, using only a remote terminal. For a

complete description of CP/CMS capabilities, see references

[4] and [5]

MDS-800 Microcomputer Development System

In its basic configuration, the INTEL MDS-800 Micro-

computer Development System consists of a CPU, 16K RAM, per-

ipheral interface controller, front panel controller, power

supply and enclosure. The MDS was directly connected to the

following peripheral devices: CRT and keyboard console, high

speed line printer, standard teletype with paper tape reader

and punch [Ref . 6]

Disk Operating System

The INTEL Disk Operating System (DOS) consists of

three major components, a dual floppy disk drive unit, a disk

controller, and the DOS support software.

Each 7.5 inch diameter floppy disk (diskette) had a

capacity of 256K bytes of semi-random access storage. With

the dual drive, over 0.5 million bytes of data, programs, or

other information could be assessed with relative ease and

moderate speed.

The software support package offered by Digital

Research was chosen as the operating system. CP/M consists

of several utility routines in addition to the Basic Disk

Operating System (BDOS) . These routines allow the user to

form and edit disk files, programs, or data files, and to

assemble and load assembly language programs, and provide a

powerful debug routine. A more complete description of the

CP/M BDOS is contained in Ref . [7] .

4 . Hexlink Program

Assembly language was used in the construction of the

communications interface program "LINK." "LINK" was developed

by Lt. Mack T. Elliott, USN [Ref. 8] to interface the MDS-800

(and Model 40 printer) with CP/CMS through a 1200-band tele-

phone line. Both the line and the printer are driven by an

8251 USARTS incorporated in a SBC-534 I/O board. LINK oper-

ates in one of three modes:

a. Direct link up mode

b. Transmit file mode

c. Receive file mode.

Our discussions will be limited to the Receive File

Mode. The Receive File Mode issues all CP/CMS commands to

effect the transfer of an entire P-Disk File to the floppy disk

It was necessary to modify "LINK" in its original form to in-

clude special filtering techniques of characters so that load

data would be in hexidecimal format. This means that all

characters other than (0-9, A-F) were excluded. It was still

necessary to employ additional filtering because of the

CP/CMS DumpF command output format.

5. CP/CMS DumpF Command

CP/CMS DumpF command types the contents of all or part

of a specified file in hexidecimal format. The output format

is as follows:

RECORD 1 LENGTH =512(Hexidecimal Data)

The additional filtering is required because the E, C , and D

in the word "Record" would slip through the filter, since

these letters are between A and F. These letters would pair

up and pass as valid data, i.e., E and C would form together

the hexidecimal byte value of "EC." Now, taking the entire

first line, the following characters would be accepted as

valid data: EC Dl, E5 12, followed by normal data. It can

be readily seen that when the record count becomes double

digit, i.e., 10 or greater, the number of characters to pass

through the existing filter system will be odd, thus allowing

an invalid character to form with valid data. This has the

effect of shifting valid data to the right one character,

completely changing the meaning of the data. The solution to

this problem was to check for character R, then filter out

all characters until carriage return line feed was sensed,

which comes after the 512 in the above example. This ensures

that all characters that pass through are valid data. With

the above filtering techniques, the system is ready to pass

data from CP/CMS to the Microcomputer Development System via

telephone line. The procedures are outlined below:

HEXLINK

CONTROL R

CMS FILENAME FILETYPE

FILE FT09F001

DISK: FILENAME FILETYPE

A : DATUM1 HEX

RECEIVING

HEXLINK > TRANSMISSION COMPLETE

02 00 RECORDS TRANSMITTED

D. PUNCHING LOAD DATA. ON PAPER TAPE

1. CP/M

CP/M is a monitor control program for microcomputer

system development which uses IBM compatible flexible disks

for back-up storage. Using a computer mainframe based upon

Intel's 8080 microprocessor, CP/M provides a general environ-

ment for program construction, storage, and editing, along

with assembly and program check-out functions [Ref. 9].

CP/M Dump Command Modification (Dumpl)

The Dump program was developed by Digital Research

Corp. and is compatible with the CP/M system. Dump types the

contents of the disk file at the console in hexadecimal form.

The file contents are listed 16 bytes at a time with the

absolute byte address listed to the left of each line in

hexadecimal

Dumpl is a modification to DUMP program that types

into memory, beginning at address 4400H, the contents of the

disk file. This modification was necessary in order to punch

a paper tape of data.

Punching Paper Tape Command

The MDS-800 monitor commands, specifically W4400,

F700, will punch a paper tape beginning at address 4400H and

terminating at F700H. The tape will be punched in standard

INTEL HEX FORMAT. The data generated on the IBM-360/67 is

now on paper tape in proper INTEL format, ready to be read

into the system 80/10 via TTY.

IV. SYSTEM OPERATION

A. SUBROUTINES

Appendix C contains a complete source listing of all

subroutines, including a branch table with PROM and memory

address locations. Selected subroutines will be discussed

in detail because of complexity and function. The less com-

plex subroutines are self-explanatory. Other subroutines,

such as WRCHAR, WRREC, RDCHAR, and RDREC, are covered in a

separate section.

The following subroutines will be discussed in detail:

VALDT, SGLCHN, HEADING, DSFILE, and RAMP.

1. VALDT Subroutine

The VALDT subroutine is designed to determine whether

an event is strain significant or not. VALDT was intended to

be used in conjunction with SGLCHN and STORE subroutines.

The change in magnitude of a signal is the first

indication that an event may be strain significant.

The sign of the slope of the change is determined and

compared with the sign of the slope of the previous change.

Any change in sign will identify a peak or a valley in the

analog signal and is further indication that a strain-

significant event may have occurred. Furthermore, to be sig-

nificant, the value of the strain reading must be above a

predetermined positive threshold or below a predetermined

negative threshold.

2. SGLCHN Subroutine

The SGLCHN subroutine uses the variables FSTCHN and

GAIN to define the channel and gain to be used in the conver-

sion of the analog input. The logic is similar to the sub-

routine, RANCHN, supplied by the manufacturer; however,

SGLCHN uses VALDT subroutine to determine strain significant

data. This routine converts a single channel at a time,

although the algorithm could very easily be expanded to

include a series of channels.

The mechanics of the software that accomplished this

task are based on a four-element vector. They are as follows

X : the current value of the signal on the designatedchannel

XLST: the previous value of the signal on the channeldes ignated

SIGN: the sign of the last change of the signal on thechannel designated (00H means positive slope;01H means negative slope)

FLAG: an indicator showing the status of the laststrain-significant event. 00H means within thethreshold, non-zero means outside the threshold.

Once a signal has been determined to be a strain-

significant event, it is identified by channel number and

stored in RAM. If an event fills the last storage location

in RAM, the recording procedure is initiated. The block of

256 bytes containing the data words is transferred, byte-by-

byte, to the recorder and written on the magnetic tape. Upon

completion of the transfer, the RAM is free to be refilled.

3. HEADING Subroutine

The HEADING subroutine is designed to format the

heading information that is to be written on cassette tape.

The particular heading information depends on whether the load

data were computer generated or obtained from actual aircraft

flights. The HEADING subroutine is used in ADCCHN, ADCMXM

and MASTER Executive routines. The operator is guided through

the subroutine by system prompt output on the (TTY) . The

first prompt the operator sees is as follows:

"LOAD DATA - ACTUAL OR SIMULATED A/S"

The operator now selects actual (A) or simulated (S) load data,

If the operator selects "S", then the system will respond with

the following prompts:

"MTS SCALE FACTOR (ENTER 5-DIGITS + SB)*'

The MTS SCALE FACTOR refers to the four load ranges

(+10,000; +20,000; + 50,000; +100,000) on the MTS. The

operator enters the appropriate five digits. If 100,000

scale is used, the operator would enter 99999.

"LIMIT LOAD (ENTER 5-DIGITS)"

The LIMIT LOAD refers to the design load derived from

stress analysis. The operator enters five digits plus a

space bar.

"CROSS SECT AREA (ENTER 3-DIGITS + DP)"

The CROSS SECT AREA refers to the cross-sectional

area of the test specimen at the point of investigation.

The operator can enter any combination of three digits and a

decimal point, plus a space bar.

"RANDOM NUMBER SEED (ENTER 6 DIGITS)"

The RANDOM NUMBER SEED refers to the seed used in the

load sequence randomization technique. The operator enters

six digits plus a space bar.

Had the operator declared the load data as actual,

then the system would display the following messages:

"JULIAN DATE (ENTER 4 DIGITS + SB)"

The operator enters three digits representing the

number of days that have expired since the beginning of the

year plus the last digit of the year; example, 1358 (135th

day, 1978). The operator types space bar for next prompt.

"AIRCRAFT TYPE (ENTER 4 CHARS + SB)"

The AIRCRAFT TYPE refers to the type of aircraft the

data were recorded from; for example, A-7E, F-4J, EA-6B, etc.

The operator enters aircraft type plus space bar.

"BUNO (ENTER 6 DIGITS + SB)"

The BUNO refers to the Bureau number of the aircraft.

The operator enters the six-digit Bureau number plus a space

"CONFIGURATION [ENTER 1-LETTER A, B, C OR D)

The CONFIGURATION refers to the external stores load-

ing. The letters A through D are defined by the user. For

example, the following definitions might be used:

"AM BASIC AIRCRAFT NO STORES

"B" CONF. "A" PLUS CENTERLINE STORE

"C" CONF. "B" PLUS INBOARD WING STORES

M D" CONF. "C" PLUS OUTBOARD WING STORES.

The operator enters the appropriate letter plus a space bar.

"GROSS WEIGHT (ENTER 5 DIGITS + SB)"

The GROSS WEIGHT refers to the aircraft's appropriate

gross weight. The operator enters five digits plus space bar.

"MISSION (ENTER 1-DIGIT 1, 2, 3, 4 or 5)"

The MISSION is user defined. For example, the user

may wish to define "1" as Air Combat or "2" as Close Air

Support or "3" as Point Intercept, etc. The operator enters

the appropriate digits plus a space bar.

The system will not write the above heading information

on the cassette tape. Once all the heading information is re-

corded, the tape is stopped and the system returns to the

calling routine.

4. Display File Subroutine (DSFILE)

The DSFILE subroutine is designed to output each

record to the teletype in a specified format. It is designed

to read each record of a file from a cassette tape and output

the record on the TTY in a specified format. The output

varies slightly, depending on whether the load data were

actual, or computer generated. The operator is guided through

the routine by prompts at the console.

We now consider the two different output formats. If

the load data were computer generated, then the following out-

put will be displayed:

SIMULATED LOAD DATA

MTS SCALE FACTOR : 2 000

LIMIT LOAD : 30000

CROSS SECT AREA : .500

RANDOM NUMBER SEED : 00 58 3

STRAIN DATA FOLLOWS:

The system will now prompt the operator with the

following

HARD COPY STRAIN DATA (Y/N)

The operator now has the choice of typing out the con

verted data or not. If "Y" is depressed, then the converted

data will be displayed in blocks of 256 bytes. Each block

of data will have eight columns with 16 rows. Sample output

follows

HARD COPY STRAIl*i DAT;I (Y/N)YE4F8 03o8 7018 0238 7018 0338 7018 0048

701S 0138 7018 0A38 7018 0238 7018 0A38

701S 0338 7018 03BS 7018 138 7018 0238

7018 0338 7018 0238 7018 0338 7018 0338

7188 0338 7018 0238 7018 03B8 7018 0338

7018 0338 7018 0238 7018 0338 7018 0138

7018 0338 7018 0C38 7018 0238 7018 02B8

7018 0338 7018 0338 7018 0138 7018 0338

7018 0238 7018 0338 7018 1 138 7018 0338

7018 0238 701S 0338 7018 0838 7018 0338

7018 0238 7018 0238 7018 0238 70 18 0338

7018 0238 7018 0338 7018 0038 7018 0338

7018 0338 70 18 0E38 7018 138 7018 0338

7018 0C38 7018 0238 7018 0338 7018 0238

7018 0238 7018 0238 7018 0238 7018 0A38

7018 3138 7018 0E38 7018 0238 7018 02

If the operator did not want a hard copy of the data,

depressing any other key will dump the next 256 byte block a

record type 5 data. This process will continue until control

senses a record type 4, at which time the system will type

"END OF FILE" on the TTY and return the user to the MAIN

Executive routine.

Had the load data been from actual aircraft flights,

then the operator would display the following information:

ACTUAL LOAD DATA

JULIAN DATE

AIRCRAFT TYPE

CONFIGURATION

GROSS WEIGHT

MISSION

132628

The remainder of the routine would be exactly as described

above. The display subroutine is used in the READ Executive

routine.

5. RAMP Subroutine

The RAMP subroutine is designed to output a voltage

via one of the DAC ' s corresponding to a particular load.

The driver loads are stored in the random load buffer, which

begins at memory location 4400H and extends to memory location

7F00H. The routine compares two successive loads, and incre-

ments or decrements the DAC output in steps of 0.00488 volts

until the load values are equal. In between each incremental

step the system delays a total of 6 millisec and checks the

assigned channel for significant strain data. The 6 millisec

delay provides the DAC output with a constant slope at an

average rate of one cycle per second.

When the two loads are equal, the system will relieve

the next load and repeat the above process until a "1AH" byte,

located at the end of the random data, is sensed. This byte

signals the end of the data, and the system checks to see if

it is to be repeated. The random load data can be repeated

up to 16 times, providing approximately ten hours of contin-

uous testing. At the completion of the specified number of

runs, the routine prompts the operator "M>" by automatically

returning to the MAIN Executive routine.>6

B. EXECUTIVE ROUTINES

The Executive routines integrate the entire software pack

age by using various combinations cf subroutines to perform

specific tasks. There are seven Executive routines: MAIN,

SORCLD, ADCCHN, ADCMXM, READ, LOAD, and MASTER. The follow-

ing paragraphs will discuss in detail the function of each

Executive routine.

1 . MAIN Executive

The MAIN Executive routine is designed to function

as an access routine to the other Executive routines and the

system 80/10 monitor. It is assumed that the system has been

powered up and the punch paper tape containing all the prompt

messages has been read in via paper tape reader. To gain

access, the operator types in at the console "G3C40." The

system will respond with "M>" followed by "CONTROL G FOR

INSTRUCTIONS." Each time the MAIN Executive is accessed, the

stack pointer is initialized and the DAC ' s are set to volts.

This last point is very important because, if it becomes

necessary to "RESET" the system, both DAC ' s are driven to

minus full scale. This could be disastrous if a test speci-

men were hooked up. Continuing, should the operator choose

to enter CONTROL G at the console, the following prompt would

be displayed:

CONTROL A - ENTER ADC CKN EXECUTIVE

CONTROL B - ENTER ADCMXM EXECUTIVE

CONTROL C - ENTER SBC 80/10 MONITOR

CONTROL D - EXIT EXECUTIVE ROUTINE

CONTROL E - ENTER MASTER EXECUTIVE

CONTROL G - INSTRUCTIONS

CONTROL L - ENTER LOAD EXECUTIVE

CONTROL R - ENTER READ EXECUTIVE

CONTROL S - ENTER SURCLD EXECUTIVE

Decimal Point = DP

Space Bar = SB.

The operator now has access to the entire system via the

above instructions. At this point the operator may wish to

access the system 80/10 monitor to read in a random load paper

tape. The operator accesses the monitor system by a "CONTROL

C." The system will respond with "." At this time, the

operator would load the punch paper tape containing the random

load data into tape reader, switch mode switch to "KT" and

depress the "R" key, followed by carriage return (CR) . The

system will begin to read in the punched paper tape of random

load data beginning at memory location 4400. This process of

reading in load data need be done only once, since the SORCLD

Executive will permanently record load data on a master load

tape. After reading the punched paper tape, the tape movement

will cease and the system will display "." at the console.

The operator should next depress the "RESET" button, located

on the front panel of the system 80/10 microcomputer (Fig. 13)

(Note: The machine should have hydraulic drive off prior to

depressing reset button, since DAC ' s are driven to minus full

scale.

It is necessary to insert a special byte value (1AH)

at F700H at this time to signal the end of load data and pre-

vent the system from possibly interfering with the stack area.

To gain access back to the MAIN Executive, the opera-

tor types in at the console "G3C40." The system will respond

with "M>" followed by "CONTROL G FOR INSTRUCTIONS."

If the operator has just used a paper tape containing

random loads, the next Executive routine selected would be

"SORCLD."

2. SORCLD Executive

The SORCLD Executive is designed to make a copy on

magnetic tape of the data between memory locations 4400-F700

HEX. Before entering SORCLD, ensure that the tape is rewound,

«CJ<a

GO•Htin

the "Write" head is engaged, and the Write/Read switch is in

the "Write" mode. The routine is accessed from the MAIN

Executive by holding down the "CONTROL" key and depressing

the "S" key.

The cassette tape will begin to record load data

located between 4400-7F00H. Upon completion, the system will

display the following prompt and automatically return to the

MAIN Executive:

LOAD DATA TRANSFER - COMPLETED

RELEASE WRITE HEAD

DEPRESS REWIND BUTTON

REMOVE LOAD DATA CASSETTE

ENGAGE WRITE HEAD

CHECK FOR M>.

CONTROL G FOR INSTRUCTIONS

Had the random load data been recorded previously on

magnetic tape, the operator could have elected to enter the

LOAD Executive.

3 . LOAD Executive

The LOAD Executive is designed to read random load

data contained on cassette magnetic tape into memory, begin-

ning at location 4400H.

Before entering the LOAD Executive, the operator

should insure that the tape is rewound, the "Read head" is

engaged, and the Write/Read switch is in the "Read" position.

The LOAD Executive is accessed from the MAIN Executive by

CONTROL L command. The tape recorder will begin to read the

random load data into memory. At the completion of this cycle,

the system will indicate that the load data transfer is com-

pleted and will automatically return to the MAIN Executive.

The prompt message is that given in the SORCLD Executive.

4. ADCCHN Executive

The ADCCHN Executive is designed to perform ADC on a

selected channel at a 28 KHZ rate. The converted data is

stored in a 256 byte buffer. When the buffer fills up, the

data are dumped onto the cassette tape; thus freeing the buffer

for more data. This process continues until the operator

elects to terminate by entering a CONTROL D at the console,

at which time the partially filled buffer is dumped onto

cassette tape, the tape is stopped and the system is returned

to the MAIN Executive routine.

The ADCCHN Executive is accessed from the MAIN Execu-

tive by entering a CONTROL A at the console. The system will

respond with "A>" followed by LOAD DATA - ACTUAL OR SIMULATED

(A/S)." Upon selecting "A" or "S" the operator will proceed

through bookkeeping prompts as discussed under "Heading" sub-

routine. After heading information has been entered, the

operator will be prompted with the following message, "SELECT

CHANNEL NUMBER (0-F HEX)." The operator depresses the appro-

priate key, and the conversion process will begin. This

routine is especially useful when testing and calibrating

individual channels.

5. ADCMXM Executive

The ADCMXM Executive is designed to perform ADC on a

selected channel. However, the only data that get stored in

the data buffer, and eventually on cassette tape, are the

maximum or minimum values of the converted data. The sub-

routine VALDT provides the logic for obtaining maximums and

minimums . The significant data bytes are stored in a memory

data buffer until the buffer is filled, at which time the

buffer is emptied onto cassette tape. This process continues

until the operator enters CONTROL D at the console, at which

time the partially filled buffer is emptied onto tape, and

the tape is stopped. The routine will automatically return

the user to the MAIN Executive routine.

6. MASTER Executive

The MASTER Executive is designed to drive the materials

testing system (MTS) with a random load, and simultaneously

monitor a selected channel for strain- s ignificant events. The

random load data used to drive the MTS are located beginning

at memory location 4400H. [See Appendix B]

The MASTER Executive is accessed from the MAIN Execu-

tive by entering a CONTROL E at the console. The system will

respond "E>" prompt, followed by "LOAD DATA - ACTUAL OR SIMU-

LATED (A/S)." Following the heading prompts, the system will

prompt the operator with "NUMBER OF RUNS ENTER - 1 DIGIT (0-H

HEX)." The operator enters the number of times that the load

data sequence is to be repeated, i.e., if the operator wishes

to repeat the load sequence four (4) times, then enter a "4."

This capability enables the operator to run the load sequence

16 times, which, with the given number of loads (7552) will

provide approximately 10 hours of continuous testing. The

next system prompt is "SELECT CHANNEL NUMBER (O-F HEX)." The

operator types in the channel number and the system will begin

to convert data and writing peaks and valleys on the cassette

tape. The system automatically returns to the MAIN Executive

following the last cycle through the random load data.

7. READ Executive

The READ Executive is designed to read (or play back)

a file created by the Write program. The information is dis-

played at the console. The operator has the choice of display-

ing record type 3 data or continuing. To gain access to the

READ Executive from the MAIN Executive, the operator types a

CONTROL R at the console. Prior to the CONTROL R command,

the cassette tape should be rewound, the Read head engaged,

and the Write/Read switch set to the Read position. The

system will respond with "R," then immediately begin reading

tape records. The record 1 or 2 type data are displayed

directly. The record 3 data are dumped in 256 byte blocks

into RAM, the tape is stopped, and the operator is prompted,

"HARD COPY STRAIN DATA (Y/N)." If the operator should elect

"Y," then the specific data loaded in the 256 byte RAM buffer

are typed out at the console. If the operator enters "N,"

the next block of data is read from the tape into RAM. This

process is continued until the END-OF-FILE is typed at the

console and the system automatically returns to the MAIN

Executive

C. PRELIMINARY SYSTEM QUALIFICATION

This section discusses the preliminary qualification tests

conducted on the data acquisition system, intended to exercise

the device throughout its expected range of operation so that

actual performance limitations, if any, may be determined.

1. DC Calibration

Accompanying the SBC-732 analog input/output model was

a voltage calibration and scan test software package [Ref . ]

This program consists of a three-step sequence which must be

performed in the following order: (1) P$A offset adjustment,

(2) ADC offset adjustment, and (3) ADC range adjustment.

Following the calibration test, the ADC system was verified

by applying standard precision DC voltage. The +10 volt range

was chosen to coincide with the MTS machine operating range.

The test also verified the subroutine associated with the

ADCCHN Executive routine. For instance, 2 volts from a stand-

ard precision supply were read into the system and an interro-

gation of the memory showed that the system stored 99ADH,

which corresponds to 2 volts.

Incremental DC Volt Step Test

This test was designed to verify the theoretical incre

mental voltage of each bit used in the conversion process.

Using 12 bits for conversion, there are (16 x 16 x 16 = 4096)

incremental steps possible. This means, using the + 10 volt

range, that each incremental step is equivalent to 0.00488

volts. A standard precision voltage source was applied in

steps of 5 millivolts. Changes in the bit pattern verified

the theoretical predictions.

3 . Sinusoidal Signal Reconstruction

This test was designed to evaluate the system's abil-

ity to accurately acquire, store,, and reconstruct a sinusoidal

signal with a known amplitude. The analog input signal was

converted and recorded on cassette tape using the ADCCHN Exec-

utive routine. Recorded data were read into memory location

beginning at 4400H and outputted via system DAC ' s to a strip

chart recorder. The reconstruction signal was compared to

the original signal and produced deviations of less than II.

4. Peak and Troughs Test

This test was designed to check the accuracy of the

system to record only the peaks and valleys of a known sinus-

oidal signal. The amplitude of the sign wave was calibrated

and measured. The peaks and valleys were reached on magnetic

cassette tape using the ADCMXM Executive routine. The con-

verted value from the tape was broken down into its voltage

representation and compared with actual input voltage. For

example, the converted value of FEE0H is equivalent to (256

x 15 + 16 x 14 + 14 = 4078) steps, which is the same as

9.9121 volts. This voltage was then compared with strip

chart value of 9.94 volts, which was well within the accur-

acies of the instrumentation.

Driver Test

This test was designed to exercise the entire system

using the random loads generated on the IBM-360 and to drive

the MTS machine using the RAMP subroutine. Some initial con-

cern was experienced with the speed of the drive signal and

the response of the MTS machine when the output signals were

attenuated by 10%. The RAMP rate was set to an average of

.7 cycles per second; the first list results indicated that

the driver voltage was being attenuated at both the peaks and

troughs by about 0.5 volts on a to 10 volt signal.

Further investigation revealed that because of the

incremental step technique used to create the driver signal,

it was necessary to hold the RAMP signal longer at the DAC

output port before proceeding to the next incremental step.

Test results indicated that it was necessary to hold the signal

at the DAC output about 8 millisec before proceeding to the

next step. The resulting acceptable driver rate was approx-

imately .6 cycles per sec. This test verified the subroutines

used in the MASTER Executive routine.

V. CONCLUSIONS AND RECOMMENDATIONS

Based upon the performance tests discussed in the preced-

ing section, it is concluded that the system is executing its

several modes of operation accurately and reliably. Further-

more, during the course of the software interface development,

modifications were constantly made with the intent of improving

the performance and operator interface. The modularity of the

software package makes it versatile and easily adapted to

future changing needs.

APPENDIX A

GLOSSARY

1. ASCII: American Standard Code for Information Interchange.

This is a seven-bit-plus-parity code established by the

American National Standards Institute to achieve compat-

ibility between data services. Also called USASCII.

2. Assembly: A listing which contains both source code and

machine code.

3. BIT: Binary digiT. A single unit of information in a

binary word.

4. Buffer: A group of memory locations used to store specific

data (input data, constants, output data, etc.).

5. Byte: An eight-BIT word which is processed as a single

quantity.

6. CPU: Central Processing Unit. The area of the micro-

processor which computes and sequences all logic and

arithmetic functions.

7. CRT: Cathode Ray Tube - A televis ion- like picture tube

used in visual display terminals.

8. D/A: The inverse of the A/D process.

9. EPROM: Erasable/programmable read only memory.

10. I/O: Input/output.

11. K: A suffix which indicates a group of 1024 (2 ) items

as in "4K of memory" meaning 4096 memory locations.

12. MUX: A multiplexing device.

13. Nibble: The upper or lower four BITs in one byte.

14. RAM: Random access memory. Volatile memory used for

variable storage and data manipulation.

15. Register: A storage location located in the CPU.

16. ROM: Read only memory, non-volatile.

17. Sample and Hold: A device for sampling the amplitude

of a signal at a given time and holding that amplitude.

18. Software: The program which resides in the U-P's memory

19. Source code: The program written by the user.

BeginningAddress

APPENDIX B

MEMORY MAP

DescriptionEndingAddress

EPROM #1 SBC-80/10 Monitor

EPROM #2 SBC-80/10 Monitor Subroutine

EPROM #3 Subroutines

EPROM #4 Subroutines + ExecutiveRoutines

UK Uncommitted Memory

RAM Reserved for Monitor

Start Software Program

Buffer #3

Mess ages /Variables

256 Byte Data Buffer

15,104 Byte Random Load Buffer

Stack Buffer

Memory Based Address for SBC-732Board

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LIST OF REFERENCES

1. Intel Corporation, System 80/10 Hardware Reference Manual,

2. Intel Corporation, SBC 732 Combination Analog Input/OutputBoard Hardware Reference Manual , 1977.

3. Atkinson, J.S., Jr., A Study of Spectrum Loading andRange-Pair Counting Method Effects on Cumulative FatigueDamage , Master's Thesis, Naval Postgraduate School,Monterey, CA, March 1977.

I BM , Control Program- 67/Cambridge Monitor System (CP-67/CMS)Version 3.2 Program Number 360 D-05.2.005 User's Guide ,

5. W. R. Church Computer Center, User's Manual , 1974.

6. Intel Corporation, MDS-800 Intellec MPS MicrocomputerDevelopment System Hardware Reference Manual , 1975.

7. Intel Corporation, Diskette Operating System MicrocomputerDevelopment System MDS-DOS Operator's Manual , 1975.

8. Elliott, M.T., Master's Thesis to be published September1978, Naval Postgraduate School, Monterey, CA.

9. Digital Research Corp., An Introduction to CP/M Featuresand Facilities , 1976.

10. Butler, C.L., Software Design for a Fatigue MonitoringData Acquisition System , Master's Thesis, Naval Post-graduate School, Monterey, CA, September 1976.

INITIAL DISTRIBUTION LIST

Defense Documentation CenterCameron StationAlexandria, Virginia 22314

Library, Code 0142Naval Postgraduate SchoolMonterey, California 93940

Department Chairman, Code 67Department of AeronauticsNaval Postgraduate SchoolMonterey, California 93940

Assoc. Professor G. H. Lindsey, Code 67LiDepartment of AeronauticsNaval Postgraduate SchoolMonterey, California 93940

LCDR Frederick Martin Blakely, USN14334 North Ashdale AvenueWoodbridge, VA 22193

No. Copies

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Blake] yDesign of software

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