digital integrated circuits lecture 7: combinational circuits
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Microsoft PowerPoint - Lec7Chih-Wei Liu
assign y = s ? d1 : d0; endmodule
1) Sketch a design using AND, OR, and NOT gates.
0
1
S
D0
assign y = s ? d1 : d0; endmodule
1) Sketch a design using AND, OR, and NOT gates.
D0 S
D1 S
Example 2
2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.
Y
Bubble Pushing
Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic
Remember DeMorgan’s Law
Example 3
3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.
Y
A B C D
Complex AOI
Y A B C= + Y A B C D= + ( )Y A B C D E= + +Y A= DCBAY ⋅+⋅=CBAY +⋅= DCCBAY ⋅++⋅= )(
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 9
A B C D
p = 16/3
gE = 8/3
Complex AOI
Y A B C= + Y A B C D= + ( )Y A B C D E= + +Y A= DCBAY ⋅+⋅=CBAY +⋅= DCCBAY ⋅++⋅= )(
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 10
Example 4
Given that the multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
Y
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 11
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 12
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 14
Annotate your designs with transistor sizes that achieve this delay.
Y
Annotate your designs with transistor sizes that achieve this delay.
6
ˆ
ˆ
out
in
i
i
Input Order
Our parasitic delay model was too simple Calculate parasitic delay for Y falling
If A arrives latest? Best case falling If B arrives latest? Worse case falling
R
Input Order
Our parasitic delay model was too simple Calculate parasitic delay for Y falling
If A arrives latest? 6RC = 2τ If B arrives latest? 7RC = 2.33τ
6C
2C2
2
22
B
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 19
Inner & Outer Inputs
Outer input is closest to rail (B) Inner input is closest to output (A)
If input arrival time is known Connect latest input to inner terminal
2
2
22
B
A
Y
Asymmetric Gates
Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same
gA = gB = gtotal = gA + gB = Asymmetric gate approaches g = 1 on critical input But total logical effort goes up
A reset
Asymmetric Gates
Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same
gA = 10/9 (better than 4/3) gB = 2 gtotal = gA + gB = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up in this case
A reset
A
B
The least delay NF1/N + p
H and B are ultimately determined by microarchitecture
G is determined by logic and circuit design Choose low G gates
Change circuit topology to reduce G for a given gate, how?
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 24
Skewed Gates
Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
gu = gd =
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 25
Skewed Gates
Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6 gd = 2.5 / 1.5 = 5/3
1/2
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 26
HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 27
gu = 2/1.5=4/3 gd = 2/3 gavg = 1
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
Y
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
Y
gu = 2/1.5=4/3 gd = 2/3 gavg = 1
gu = 3/3=1 gd = 3/1.5=2 gavg = 3/2
gu = 3/1.5=2 gd = 3/3=1 gavg = 3/2
gu = 3/2 gd = 3 gavg = 9/4
gu = 2 gd = 1 gavg = 3/2
Y
Y
1
Y
Reduces parasitic delay for critical input
A reset
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 31
Best P/N Ratio
We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter
Delay driving identical inverter tpdf = tpdr = tpd = dtpd / dP = Least delay for P =
1
The original model
μ=2 may not the best P/N ratio. The new model
kg s
d g
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 33
Best P/N Ratio
The P/N ratio that gives least average delay in a logic gate is the square root of the ratio that gives equal rise and fall delays Ex: inverter
Delay driving identical inverter tpdf = (P+1) tpdr = (P+1)(μ/P) tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2 dtpd / dP = (1- μ/P2)/2 = 0 Least delay for P =
1
P/N Ratios
In general, fastest P/N ratio is sqrt of equal delay ratio. We only shows average delay slightly for inverters But significantly decreases area and power
Inverter NAND2 NOR2
P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters But significantly decreases area and power
Inverter NAND2 NOR2
gd = 0.81 gavg = 0.98
Y
Observations
For speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input
assign y = s ? d1 : d0; endmodule
1) Sketch a design using AND, OR, and NOT gates.
0
1
S
D0
assign y = s ? d1 : d0; endmodule
1) Sketch a design using AND, OR, and NOT gates.
D0 S
D1 S
Example 2
2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.
Y
Bubble Pushing
Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic
Remember DeMorgan’s Law
Example 3
3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.
Y
A B C D
Complex AOI
Y A B C= + Y A B C D= + ( )Y A B C D E= + +Y A= DCBAY ⋅+⋅=CBAY +⋅= DCCBAY ⋅++⋅= )(
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 9
A B C D
p = 16/3
gE = 8/3
Complex AOI
Y A B C= + Y A B C D= + ( )Y A B C D E= + +Y A= DCBAY ⋅+⋅=CBAY +⋅= DCCBAY ⋅++⋅= )(
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 10
Example 4
Given that the multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.
Y
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 11
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 12
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 14
Annotate your designs with transistor sizes that achieve this delay.
Y
Annotate your designs with transistor sizes that achieve this delay.
6
ˆ
ˆ
out
in
i
i
Input Order
Our parasitic delay model was too simple Calculate parasitic delay for Y falling
If A arrives latest? Best case falling If B arrives latest? Worse case falling
R
Input Order
Our parasitic delay model was too simple Calculate parasitic delay for Y falling
If A arrives latest? 6RC = 2τ If B arrives latest? 7RC = 2.33τ
6C
2C2
2
22
B
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 19
Inner & Outer Inputs
Outer input is closest to rail (B) Inner input is closest to output (A)
If input arrival time is known Connect latest input to inner terminal
2
2
22
B
A
Y
Asymmetric Gates
Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same
gA = gB = gtotal = gA + gB = Asymmetric gate approaches g = 1 on critical input But total logical effort goes up
A reset
Asymmetric Gates
Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same
gA = 10/9 (better than 4/3) gB = 2 gtotal = gA + gB = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up in this case
A reset
A
B
The least delay NF1/N + p
H and B are ultimately determined by microarchitecture
G is determined by logic and circuit design Choose low G gates
Change circuit topology to reduce G for a given gate, how?
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 24
Skewed Gates
Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
gu = gd =
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 25
Skewed Gates
Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6 gd = 2.5 / 1.5 = 5/3
1/2
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 26
HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction
But larger for the other direction
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 27
gu = 2/1.5=4/3 gd = 2/3 gavg = 1
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
Y
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
gu = gd = gavg =
Y
gu = 2/1.5=4/3 gd = 2/3 gavg = 1
gu = 3/3=1 gd = 3/1.5=2 gavg = 3/2
gu = 3/1.5=2 gd = 3/3=1 gavg = 3/2
gu = 3/2 gd = 3 gavg = 9/4
gu = 2 gd = 1 gavg = 3/2
Y
Y
1
Y
Reduces parasitic delay for critical input
A reset
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 31
Best P/N Ratio
We have selected P/N ratio for unit rise and fall resistance (μ = 2-3 for an inverter). Alternative: choose ratio for least average delay Ex: inverter
Delay driving identical inverter tpdf = tpdr = tpd = dtpd / dP = Least delay for P =
1
The original model
μ=2 may not the best P/N ratio. The new model
kg s
d g
DIC-Lec7 cwliu@twins.ee.nctu.edu.tw 33
Best P/N Ratio
The P/N ratio that gives least average delay in a logic gate is the square root of the ratio that gives equal rise and fall delays Ex: inverter
Delay driving identical inverter tpdf = (P+1) tpdr = (P+1)(μ/P) tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2 dtpd / dP = (1- μ/P2)/2 = 0 Least delay for P =
1
P/N Ratios
In general, fastest P/N ratio is sqrt of equal delay ratio. We only shows average delay slightly for inverters But significantly decreases area and power
Inverter NAND2 NOR2
P/N Ratios
In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters But significantly decreases area and power
Inverter NAND2 NOR2
gd = 0.81 gavg = 0.98
Y
Observations
For speed: NAND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input
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