digital integrated circuitsa design perspectivedesigning sequentiallogic circuits.pdf

Digital Integrated

CircuitsA Design Perspective

Designing Sequential

Logic Circuits

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic

November 2002

Note this this

presentation

Is from psu university

This is for self use only do not use for commercial

purpose .

I know you enjoy my

work

Say thanks

© Digital Integrated Circuits2nd

Sequential Circuits

Sequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs

© Digital Integrated Circuits2nd

Sequential Circuits

Naming Conventions

• In our text:

• a latch is level sensitive

• a register is edge-triggered

• There are many different naming conventions

• For instance, many books call edge-triggered elements flip-flops

• This leads to confusion however

© Digital Integrated Circuits2nd

Sequential Circuits

Latch versus Register

Latch

stores data when

clock is low

D

Clk

Q D

Clk

Q

Register

stores data when

clock rises

Clk Clk

D D

Q Q

© Digital Integrated Circuits2nd

Sequential Circuits

Latches

© Digital Integrated Circuits2nd

Sequential Circuits

Latch-Based Design• N latch is transparent

when f = 0• P latch is transparent

when f = 1

N

LatchLogic

Logic

P

Latch

f

© Digital Integrated Circuits2nd

Sequential Circuits

Timing Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATA

STABLE

DATA

STABLE

Register

CLK

D Q

© Digital Integrated Circuits2nd

Sequential Circuits

Characterizing Timing

Clk

D Q

tC 2 Q

Clk

D Q

tC 2 Q

tD 2 Q

Register Latch

© Digital Integrated Circuits2nd

Sequential Circuits

Maximum Clock Frequency

FF’s

LOGIC

tp,comb

f

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

tclk-Q + tp,comb + tsetup = T

© Digital Integrated Circuits2nd

Sequential Circuits

Positive Feedback: Bi-Stability

Vo1

Vi25Vo1

Vi25Vo1

V i1

A

C

B

Vo2

V i1 = Vo2

Vo1 Vi2

V i2 = Vo1

© Digital Integrated Circuits2nd

Sequential Circuits

Meta-Stability

Gain should be larger than 1 in the transition region

© Digital Integrated Circuits2nd

Sequential Circuits

Writing into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

© Digital Integrated Circuits2nd

Sequential Circuits

Mux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ

© Digital Integrated Circuits2nd

Sequential Circuits

Mux-Based Latch

CLK

CLK

CLK

D

Q

© Digital Integrated Circuits2nd

Sequential Circuits

Mux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Non-overlapping clocks

© Digital Integrated Circuits2nd

Sequential Circuits

Master-Slave (Edge-Triggered) Register

Two opposite latches trigger on edgeAlso called master-slave latch pair

© Digital Integrated Circuits2nd

Sequential Circuits

Master-Slave Register

QM

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexer-based latch pair

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

D

Q

CLK

2 0.5

0.5

1.5

2.5

tc 2 q(lh)

0.5 1 1.5 2 2.50

time, nsec

Volts

tc 2 q(hl)

© Digital Integrated Circuits2nd

Sequential Circuits

Setup Time

© Digital Integrated Circuits2nd

Sequential Circuits

Reduced Clock Load

Master-Slave Register

DQT1 I 1

CLK

CLK

T2

CLK

CLKI2

I3

I4

© Digital Integrated Circuits2nd

Sequential Circuits

Avoiding Clock OverlapCLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK

© Digital Integrated Circuits2nd

Sequential Circuits

Overpowering the Feedback Loop ─

Cross-Coupled Pairs

Forbidden State

S

S

R

Q

Q

Q

QRS Q

Q00 Q

101 0

010 1

011 0RQ

NOR-based set-reset

© Digital Integrated Circuits2nd

Sequential Circuits

Cross-Coupled NAND

S

QR

Q

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Cross-coupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell

© Digital Integrated Circuits2nd

Sequential Circuits

Sizing Issues

Output voltage dependenceon transistor width

Transient response

4.03.53.0

W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q (

Vo

lts)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 mm

3

Vo

lts

Q S

W = 0.9 mm

W = 0.8 mm

W = 0.7 mm

W = 0.6 mm

W = 0.5 mm

© Digital Integrated Circuits2nd

Sequential Circuits

Storage Mechanisms

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static

© Digital Integrated Circuits2nd

Sequential Circuits

Making a Dynamic Latch Pseudo-Static

D

CLK

CLK

D

© Digital Integrated Circuits2nd

Sequential Circuits

More Precise Setup Time

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup/Hold Time Illustrations

Circuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1

Setup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataT

Setup-1

Setup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

ClockDataT

Setup-1

Setup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

© Digital Integrated Circuits2nd

Sequential Circuits

Timet=0

ClockDataT

Setup-1

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Setup/Hold Time IllustrationsCircuit before clock arrival (Setup-1 case)

Clk-Q Delay

TSetup-1

TClk-Q

Time

© Digital Integrated Circuits2nd

Sequential Circuits

Setup/Hold Time IllustrationsHold-1 case

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

DataClockT

Hold-1

0

Clk-Q Delay

THold-1

TClk-Q

Time

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

Timet=0

DataClockT

Hold-1

Setup/Hold Time IllustrationsHold-1 case

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

0

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

DataClockT

Hold-1

Setup/Hold Time IllustrationsHold-1 case

0

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data

Setup/Hold Time IllustrationsHold-1 case

0

© Digital Integrated Circuits2nd

Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1

SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data

Setup/Hold Time IllustrationsHold-1 case

0

© Digital Integrated Circuits2nd

Sequential Circuits

Other Latches/Registers: C2MOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

Slave Stage

“Keepers” can be added to make circuit pseudo-static

© Digital Integrated Circuits2nd

Sequential Circuits

Insensitive to Clock-Overlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap

© Digital Integrated Circuits2nd

Sequential Circuits

PipeliningR

EG

RE

G

RE

G

log

a

CLK

CLK

CLK

Out

b

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

RE

G

CLK

RE

G

CLK

Out

b

Reference Pipelined

© Digital Integrated Circuits2nd

Sequential Circuits

Other Latches/Registers: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Out

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

© Digital Integrated Circuits2nd

Sequential Circuits

Including Logic in TSPC

CLKIn CLK

VDDVDD

Q

PUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

In2

AND latchExample: logic inside the latch

© Digital Integrated Circuits2nd

Sequential Circuits

TSPC Register

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4

© Digital Integrated Circuits2nd

Sequential Circuits

Pulse-Triggered Latches

An Alternative Approach

Master-Slave

Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered

Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:

© Digital Integrated Circuits2nd

Sequential Circuits

Pulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

X

MP

MN

(a) register (b) glitch generation

CLK

CLKG

(c) glitch clock

© Digital Integrated Circuits2nd

Sequential Circuits

Pulsed LatchesHybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2

CLKD

© Digital Integrated Circuits2nd

Sequential Circuits

Hybrid Latch-FF Timing

© Digital Integrated Circuits2nd

Sequential Circuits

Latch-Based Pipeline

© Digital Integrated Circuits2nd

Sequential Circuits

Non-Bistable Sequential Circuits─

Schmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

•VTC with hysteresis

•Restores signal slopes

© Digital Integrated Circuits2nd

Sequential Circuits

Noise Suppression using Schmitt Trigger

© Digital Integrated Circuits2nd

Sequential Circuits

CMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3

© Digital Integrated Circuits2nd

Sequential Circuits

Schmitt Trigger Simulated VTC

2.5

VX(V) VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

Vx(V)

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

© Digital Integrated Circuits2nd

Sequential Circuits

CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6

© Digital Integrated Circuits2nd

Sequential Circuits

Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

© Digital Integrated Circuits2nd

Sequential Circuits

Transition-Triggered Monostable

DELAY

td

In

Outtd

© Digital Integrated Circuits2nd

Sequential Circuits

Monostable Trigger (RC-based)

VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.

© Digital Integrated Circuits2nd

Sequential Circuits

Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

© Digital Integrated Circuits2nd

Sequential Circuits

Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

© Digital Integrated Circuits2nd

Sequential Circuits

Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Trigger

restores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (

ns

ec)

propagation delay as a functionof control voltage

© Digital Integrated Circuits2nd

Sequential Circuits

Differential Delay Element and VCO

in2

two stage VCO

v1

v2

v3

v4

V ctrl

Vo2 V o1

in 1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2 0.51.5

V1 V2 V 3 V4

time (ns)

2.5 3.5