easy steps towards virtual prototyping using the systemverilog dpi by dave rich verification...
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Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI
byDave Rich
Verification ArchitectMentor Graphics
Sponsored By:
2 of 120 Dave Rich - Mentor Graphics
Overview
• The world loves two kingdoms– Hardware you can touch– Software is what most people see
• Not very many people understand bothconcepts well enough for verification
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Objectives
• Provide a verification environment for hardware and software as a system– Early hardware access from software– Preserve debugging environments for both sides– Provide most optimal abstraction levels for
performance– Do not duplicate hardware/software component
verification
Sponsored By:
4 of 120 Dave Rich - Mentor Graphics
Typical SOC Design
ARMcore/CPU
DMA controller
on-chip RAM or ROM
UART
timer
parallel i/f
bridge
test i/f ctrl
external bus interfaceAHB
APBother
master/slave devices
Embedded Core
External Devices
Software in Memory
Bus Fabric
Internal Devices
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Virtual Prototype Backplane
UART
timer
parallel i/f
External bus interface
other master/slave devices
Virtual Backplane
Virtual CPU
or native code
RAM
Direct Memory References
Memory Mapped References
MemoryMap
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Block-Level Verification Environment
UART
timer
parallel i/f
APB
APB VIP
USB VIP
Processor is
irrelevant
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Mixed Software/Hardware Simulation
Virtual CPU
or native code
RAM
Direct Memory References
Memory Mapped References
UART
timer
parallel i/f
external bus interface
APB
Virtual Bus handler
Bus agent
Virtual backplane
routes traffic
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LEVELS OF ABSTRACTION
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Abstraction Levels of Accuracy• Untimed (UT) – limited or unspecified timing
accuracy. At this level, only ordering of operations matters and there may be no bookkeeping of elapsed simulated time.
• Loosely-timed (LT) – time is broken into slices or some quantum unit. An SoC virtual platform is likely to choose the execution of an instruction as its quantum time unit.
• Approximately-timed (AT) – Quantum units are broken down into phases and the tracking of elapsed simulated time is enough to gather relative performance statistics.
• Cycle-accurate/cycle-callable (CC) Timing is accurate enough to run in lock-step to match the hardware models at a pin-level, clock or bus-cycle boundaries.
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Partitioning Choices
• Wide range of abstraction choices for software models
• Hardware tends to limit to what is synthesizable• What components can be black-box verified?
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Software to Hardware DPI linkvoid C_routine() { if (address==0xFFA) { APB_read(address,&data); } else { data = MemRead[address]; } APB_write(address,data+1);
function call
transactions
task APB_read(input int address, output int data); @(posedge clock) bus <= address; cmd <= read; @(posedge clock) cmd <= ack; data = bus;endtask export “DPI-C” task APB_read;export “DPI-C” task APB_write;
Pin-level transaction
s
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Compressed Hardware Simulation Timing
APB_readop1op2APB_writeMemReadop3APB_readAPB_readop4…op1001APB_writeMemWriteAPB_writeop1002op1003APB_read
Read
Write
ReadRead
Write
Write
Read
Simulation time
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Approximated Hardware Simulation Timingtask APB_idle(input int cycles);repeat (cycles) @(posedge clock);endtask
Read
Write
idleRead
Write
idle
Read
APB_readop1op2APB_writeMemReadop3APB_idle(3);APB_readAPB_writeop4…op1004APB_idle(50)APB_read;
Do I really need 1000
cycles?
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Interrupt Monitor
task APB_idle( input int requestedCycles, output int iRequested, output int actualCycles); int i; fork for(i=0;i<requestedCycles;i++) @(posedge clock); @(IRQ!=0); join_any disable fork; actualCycles = i; iRequested = IRQ;endtask
One of many ways
to represent
an interrupt
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Transaction Specification
Field Type DescriptionOperation Enum Read, write,idle,burstAddress 32-bit Physical starting
addressReqStart Time Time of RequestReqDuration Time Time allocated for
operationTrStart Time Actual start timeTrEnd Time Actual end timeInterruptMode Enum Ignore, Complete,
AbortInterruptReq Enum None,RequestedInterruptTime Time Time of InterruptLength Int Size of dataPayload nBytes Transaction data
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MASTER TO MASTER COMMUNICATION
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Starting A C Thread
int c_code() { /* C task */ while(1) { /* C thread */ v_code(args); ... }}
module top; import “DPI-C” task c_code(); initial c_code; // start C thread bit clk; always #10 clk++; export “DPI-C” task v_code; task v_code(args); addr <= args; @(posedge clk); args = result; endtaskendmodule
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Inter-process Communication
C Thread
Software Master
Initiate Socket
Wait for message
Hardware Client
Connect to Socket
SystemVerilog Threads
Send transaction
Wait for response
Send message
Virtual PrototypeThreads
Single bus transaction
Software Bus Model
Send message
Wait for message
IPC
Com
munic
ati
on
DPI C
om
munic
ati
on
Sponsored By:
19 of 120 Dave Rich - Mentor Graphics
UVM Testbench Re-Use
DUTBus AgentRegister Model
UVM Test
regA.read()regA.write()
Virtual PrototypeBus Model
IPCchannel
IPCchannel
DPI C Thread
Sequence
Sponsored By:
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Summary
• This methodology has been deployed with a number commercially and internally developed virtual prototypes
• It turns out this technique can be used for a wide range of applications where non-SystemVerilog stimulus is needed– Any C code needs to be the master– Python/Perl Testbench (For legacy, of course)
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