ee115c – spring 2010 digital electronic circuits

EE115C – Spring 2010Digital Electronic Circuits

Final Project Presentation

Area-Delay Optimization for a 10-bit Carry-Select Adder

3

Design Summary

A) Adder block topology, B) Circuit StyleA) Used mirror adder, B) Static

C) WHY: about Area, about Delay, otherC) Static is easier to size, can optimize for delay easier, low power consumption because it’s staticNote: tp = max {tp_ci→co, tp_ci→s9}

Area = max {X2, Y2}

EE115C – Spring 2010

Schematic Layout size Metric Verfication

tp_ci→co = 1.067ns

X= 66.5µm, Y= 35.1µm

tp × Area = 4873 ns*µm2

Func: Y / N

tp_ci→s9 = 1.102ns

Area = 4422µm2

DRC: Y / N

tp = 1.102ns LVS: Y / N

4

Critical Path Analysis

Highlight critical path– block diagram of design / crit-path delay equation

tcritical tsetup 2tcarry 4tmux

EE115C – Spring 2010

Image source: http://en.wikipedia.org/wiki/Carry_select_adder

5

Design Optimization

Swept inverter based on width

Found that 3.5:1 ratio better for circuit, based on load given

EE115C – Spring 2010

w=1.26u

w=1.26u

w=1.26u

w=360n

w=360n

w=360n

w=420n

w=120n

w=840n

w=240n

w=840n

w=240n

w=120n w=420n

6

Functionality Check

Screenshot of relevant waveforms

S0

S1

S2

S3

S4

S5

S6

S7

Cout

EE115C – Spring 2010

7

Adder Layout

EE115C – Spring 2010

X=66.5µm, Y=35.1µm, Area = 4422µm2

8

Discussion

Three most important features of your design– Used static for low-power consumption– Used symmetry with mirror adder grouping to reproduce wiring

easily– Used mirror adder to reduce area

Given another chance, 3 things you would do different– Could have made layout more compact by using more metals 4

and 5– If delay is more important than power consumption, would have

used transmission gate rather static– Put in some buffers to optimize design

EE115C – Spring 2010