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EEM16/CSM51A:

Logic Design of Digital Systems

Lecture #5Combinational Building Blocks

Prof. Danijela Cabric

Fall 2013

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Recap of class thus far

Introduction of digital design

Digital representation

Boolean Algebra

Combinational logic design

Truth table, minterms, maxterms

Universal gates: AND, OR, NOT, NAND, NOR, XOR

K-maps: prime implicants, essential implicants,

Minimal SoP and PoS

2

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Todays Lecture

Combinational building blocks the idioms of digital

design Decoder

Encoder

Primary Encoder Muliplexer

Comparators

Read-only memories

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Decoder

A decoder converts symbols from one code to another.

A binary to one-hot decoder converts a symbol from binary code

to a one-hot code.

One-hot code: exactly one bit is high at any given time and

each bit represents a symbol.

Binary input a to one-hot output b

b[i] = 1 if a = ib = 1

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Example of a Decoder

2 4 Decoder

a1 a0 b3 b2 b1 b0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

a1

a0

b3

b2

b1

b0

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Can build a large decoder from several small decoders

Example build a 6 64 decoder from 3 2 4 decoders

Each 24 decodes 2 bits a[1:0]x[3:0], a[3:2]y[3:0], a[5:4]z[3:0]

AND one bit each of x, y, and z to generate an output

b[i] = x[i[1:0]] & y[i[3:2]] & z[i[5:4]]

Think of each bit of b as a position in a 3-D cube

a5 a4 z3 z2 z1 z0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

a3 a2 y3 y2 y1 y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

a1 a0 x3 x2 x1 x0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

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2-Stage decoders

2:4

a[5:0]6 a[5:4]

2

4

x[3:0

]

2:4

a[3:2]

2

4

y[3:0

]

2:4

a[1:0]

2

4

z[3:0

]

b63x[3]

y[3]z[3]

b62x[3]

y[3]z[2]

b0x[0]

y[0]z[0]

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Advantage Of Dividing Large Decoder

6->64 decoder requires:

64 6-input AND gates (384 inputs) 6->64 decoder using 2->4 decoders requires:

12 2-input AND gates (24 inputs)

64 3-input AND gates (192 inputs)

Faster, smaller, lower power

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Coincident Decoder

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Tree Decoder

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Encoders

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8 bit Encoder

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Priority Encoder:

n-bit input signal a

m-bit output signal b

b indicates the position of the first 1 bit in a

n n m

Priority Encoder

mn

r g

Arbiter

a b

Encoder

m = log2n

a b

Priority

Encoder

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Priority Encoder

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Arbiter

n n

Finds first 1bit in r

g[i]=1 if r[i]=1 and r[j]=0 for j>i

Arbiter handles requests from multiple devices to use a single resource

A

rbiter

r g

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Arbiter

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Two implementations of Arbiter

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a0

s0

a1

s1

a2

s2

a3

s3

b

a0

s0

a1

s1

a2

s2

a3

s3

b

Multiplexer Implementation

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k-bit Binary-Select Multiplexer

a0

k

s

n

b

an-1

k

k

Selects one of n k-bit inputss must be one-hot

b=a[i] if s [i] = 1

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k-bit Binary-Select Multiplexer (Cont)

s1

s0

a3

a2

a1

a0

b

a0

k ban-1

k

k

s

m na b

Decoder

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sb

3

isprime

0

1

1

10

1

0

1

0

1sb [2 ]

1

sb

2

isprime

Logic with Muxes

Muxb

Muxb

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Multiplexer tree

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16:1 MUX using 4:1 MUXs

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Magnitude Comparator

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Magnitude Comparator

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Magnitude Comparator

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Going from Most to Least Significant Bit

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ROMa da

n

d

m

Read-only memory (ROM)

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Tri-State Buffer

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Decoder

w0

d0

w1

d1

12 nw12 nd

a

n

m

m

Conceptual block diagram

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Decoder

a

w0

8

6

256 word x16 bit/word ROM

64 rows x 64 columns

w63

w1

d0

d4

d1

d5

d2

d6

d3

d7

16

a7:2

16 16 16

d252

d253

d254

d255

Multiplexer

16

a1:0

2-D array implementation

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Summary

Assemble combinational circuits from pre-defined building blocks

Decoder converts codes (e.g., binary to one-hot)

Encoder encodes one-hot to binary

Multiplexer select an input (one-hot select)

Arbiter pick first true bit

Comparators equality and magnitude

ROMs

Divide and conquer to build large units from small units

Decoder, encoder, multiplexer

Logic with multiplexers or decoders