finite state machine w/ data pathee 3921 15 © tj fsmd •fibonacci –fsmd - fsm-----...
Post on 20-Jul-2020
4 Views
Preview:
TRANSCRIPT
Finite State Machinew/ Data Path
Last updated 5/19/20
2 © tjEE 3921
FSMD
These slides review FSM’s with Datapath
Upon completion: You should be able to design and simulate FSM’s with Datapath
3 © tjEE 3921
FSMD
• FSMD
• FSM with Data Path
• FSM• Control the Data Path
• Data Path• Sequential circuitry to accomplish a task
• Typically register transfer operations
Reg A Reg BTask
(combinational)
clk
Task(combinational)
Reg C
4 © tjEE 3921
FSMD
• FSMD
• FSM with Data Path
• Data Path• Sequential circuitry to accomplish a task
• Typically register transfer operations
Task(Combinational)
Reg A
clk
5 © tjEE 3921
FSMD
• FSMD
clk
Next StateLogic
Register(D-FFs)inputs outputs
OutputLogic
clk
Data Path
Control Path
outputs
inputs Task(Combinational)
Reg A
6 © tjEE 3921
FSMD
• Fibonacci – FSMD
fib(i) = 1 i = 1fib(i-1) + fib(i-2) i > 1
0 i = 0
for i= 60-1-1-2-3-5-8
7 © tjEE 3921
FSMD
• Fibonacci – FSMD
• Input Signals• clk, rstb• num_cycles – how many numbers to generate - vector• startb – start generating (bar)
• Output Signals• complete – generation complete• result_latched – Final Fibonacci value
• States• Idle• Run• Complete
8 © tjEE 3921
FSMD
• Fibonacci – FSMD
Data Path
fib(0) = 0fib(1) = 1
fib(i) = fib(i-1) + fib(i-2)
State Machine
(idle, run, complete)
num_cycles
startb
complete
result(i) OutputRegister
result_latched
9 © tjEE 3921
FSMD
• Fibonacci – FSMD
Data Path
fib(0) = 0fib(1) = 1
fib(i) = fib(i-1) + fib(i-2)
State Machine
(idle, run, complete)
num_cycles
startb
complete
result(i) OutputRegister
result_latched
calc
10 © tjEE 3921
FSMD
• Fibonacci – FSMD
• Control Path
calc 0complete 1
startb = 0F
idle
T
run
calc 1complete 0
cnt = 1F
T
cnt cnt - 1
cntnum_cycles
calc 0complete 1
complete
11 © tjEE 3921
FSMD
• Fibonacci – FSMD
• Data Path
fib(i-2) 0fib(i-1) 1
calc = 0T F
fib(i-1) fib(i-1) + fib(i-2)
fib(i-2) fib(i-1)
12 © tjEE 3921
FSMD
• Fibonacci – FSMD
calc
13 © tjEE 3921
FSMD
• Fibonacci – FSMD - FSM
14 © tjEE 3921
• Fibonacci – FSMD - FSM
FSMD
15 © tjEE 3921
FSMD
• Fibonacci – FSMD - data path
16 © tjEE 3921
FSMD
• Fibonacci – FSMD - data path
17 © tjEE 3921
FSMD
• Fibonacci – FSMD
18 © tjEE 3921
FSMD
• Fibonacci – FSMD
19 © tjEE 3921
FSMD
• Fibonacci – FSMD
20 © tjEE 3921
FSMD
• FibonacciFSMD
FSM
Data Path
21 © tjEE 3921
FSMD
• Fibonacci
N = 6
Results and intermediate values
Indicates the correct vector size was calculated
22 © tjEE 3921
FSMD
• Multiplication• Want a process that is repetitive• Repetitive addition multiplication
5 x 4 = 5 + 5 + 5 + 5 i.e. the multiplicand added the multiplier times
• Requires integers – or non-fractional binary numbers for the multiplier
23 © tjEE 3921
FSMD
• Multiplication
1110x 0011
11111110x 00000011
11111110x 00000011
1111111011111110
00000000 00000000
00000000 00000000
00000000 00000000
11111010
24 © tjEE 3921
FSMD
• Multiplier
Next StateLogic
Register(D-FFs)inputs outputs
OutputLogic
clk Control Path
clk
Data Path
outputs
inputs Task(Combinational)
Reg A
25 © tjEE 3921
FSMD
• Multiplier – FSMD
• Control Path
calc 0complete 1
startb = 0F
idle
T
run
calc 1complete 0
done = 1F
T
calc 0complete 1
finish
26 © tjEE 3921
FSMD
• Multiplier – FSMD
• Data Path
T F
calc = 0T F
Load multiplicandLoad multiplier
Result <- 0
multiplier = 0
done 1 Result = result + multiplicand
Multiplier - -
27 © tjEE 3921
FSMD
• Multiplier – FSMD
T F
calc = 0T F
Load multiplicandLoad multiplier
Result <- 0
multiplier = 0
done 1 result = result + multiplicand
Multiplier - -
calc 0complete 1
startb = 0F
idle
T
run
calc 1complete 0
done = 1F
T
calc 0complete 1
finish
done
calc
28 © tjEE 3921
FSMD
• Multiplier – FSMD - FSM
29 © tjEE 3921
FSMD
• Multiplier – FSMD - FSM
30 © tjEE 3921
FSMD
• Multiplier – FSMD – Data path
31 © tjEE 3921
FSMD
• Multiplier – FSMD – Data path
32 © tjEE 3921
FSMD
• Multiplier – FSMD
33 © tjEE 3921
FSMD
• Multiplier – FSMD
34 © tjEE 3921
FSMD
• Multiplier FSMD
FSM
Data Path
35 © tjEE 3921
FSMD
• Multiplier - FSMD
Note: Takes “multiplier” number of clock cyclesTakes a variable number of clock cycles
Results and intermediate values
top related