flash memory cell compact modeling using psp model

Flash Memory Cell Compact Modeling Using PSP Model

Anthony MaureIM2NP Institute UMR CNRS 6137

(Marseille-France)STMicroelectronics(Rousset-France)

Outline

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

Motivation 1/4

Semiconductor Memories

Volatile Memories Non-Volatile Memories

DRAM SRAM

Programmable Permanent Storage

EPROM EEPROM Flash ROM

Semiconductor memories classification

Motivation 2/4Semiconductor memories market

1996 2000 2006

Total : $36 billion Total : $49 billion Total : $61 billion

DRAMDRAM

DRAM

SRAM SRAM

SRAM

Flash Flash Flash

EEPROMROM

EPROM

EEPROMROM

EPROMEEPROM ROM

EPROM

Flash 7% Flash 21% Flash 36%

Motivation 3/4Flash memory cell applications

Memory cards

USB flash drives

Handheld computers

Digital audio players

Digital still cameras

Digital video cameras

Cellular phones

Game consoles

Motivation 4/4Flash memory cell for designers

To integrate circuit simulators and to perform multi-cell simulations : > compact modeling approach > adapted and flexible language (Verilog-A)

To include physical effects appropriate for small component : > based on an advanced description (PSP MOS model)

Accurate electrical behavior for modern technologies: > complete characterization procedure

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

Background 1/4Flash Memory Cell :

Capacitive structure and injection currents

Bulk PSource N+ Drain N+

Floating Gate polySi

Control Gate polySi

Oxide

Oxide

Background 1/4Flash Memory Cell :

Capacitive structure and injection currents

Bulk PSource N+ Drain N+

Floating Gate polySi

Control Gate polySi

CPP

COX

Background 1/4Flash Memory Cell :

Capacitive structure and injection currents

Bulk PSource N+ Drain N+

Floating Gate polySi

Control Gate polySi

CPP

COXIFN

ICHE

IFN IFN

Erased and Programmed modes :

PP

FGTT

C

QVV UV −=

Background 2/4

Id

Vgs

∆Vt

Id(«1»)

Id(«0»)VREAD

«1» «0»UV

Id

Vgs

∆Vt

Id(«1»)

Id(«0»)VREAD

«1» «0»UVB

S D

GId

Background 3/4Injection Currents : Fowler-Nordheim tunneling

BS D

G

EF

poly Si SiO2 Si

EF

Floating gate n+ Bulk p

q*VGB

e-

EC

EB

Negative charge evacuation from floating gate

TUNETUNFN eESI

β

α−

= 2..

Background 4/4Injection Currents : Channel Hot Electron current

Drain

Oxide

Floating gate

Channel

Depleted zone

e-

EFIELD

EFIELD

h+

e-

BS D

G

Negative charge injection into floating gate

TUND

D

E

A

AVLDCHE eIAIexp

..−

=

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

PSP-based Flash cell model 1/4The PSP MOS model

Developed by Philips Research and Penn State University. (first version 2006)

Compact surface-potential based model.

Relevant physical effects (mobility reduction, velocity saturation, DIBL, GIDL…)

Source/Drain junctions are described using the JUNCAP2 diode model.

Possibility of including temperature and geometrical scaling rules.

PSP-based Flash cell model 1/4The PSP MOS model

Developed by Philips Research and Penn State University. (first version 2006)

Compact surface-potential based model.

Relevant physical effects (mobility reduction, velocity saturation, DIBL, GIDL…)

Source/Drain junctions are described using the JUNCAP2 diode model.

Possibility of including temperature and geometrical scaling rules.

Pao-Sah

Charge Sheet Model

MM9(Philips)

SP(Penn State University)

MM11(Philips)

PSP

Advanced compact MOS

models

Addition of the CPP capacitor using a charge neutrality equation

PSP-based Flash cell model 2/4

( )CGFGPPGDGSGIFG VVCQQQQ −+++=

Floating Gate

BulkSource Drain

QGS QGDQGI

Control Gate

CPP

QGI, QGS and QGD values are calculated by PSP model.

They depend on VFG, VB, VS and VD (Equivalent MOS electrodes).

Implicit computation of VFG

PSP-based Flash cell model 3/4Addition of the injection currents

TUNETUNFN eESI

β

α−

= 2..

From surface potentials, vertical electric fields through tunnel oxide can be computed

B

S D

G

Fowler-Nordheim current

PSP-based Flash cell model 3/4Addition of the injection currents

From surface potentials, vertical electric fields through tunnel oxide can be computed

B

S D

G

TUND

D

E

A

AVLDCHE eIAIexp

..−

=Channel Hot Electron current

PSP-based Flash cell model 4/4Computation scheme

∫ ++= dtIIQQ CHEFNFGFG )(0

Static relation ( )CGFGPPGDGSGIFG VVCQQQQ −+++=

Dynamic relation

PSP-based Flash cell model 4/4Computation scheme

∫ ++= dtIIQQ CHEFNFGFG )(0

Static relation ( )CGFGPPGDGSGIFG VVCQQQQ −+++=

Dynamic relation

VFG

QGI, QGS, QGD

VB, VS, VD

QFG

VCG

PSP-based Flash cell model 4/4Computation scheme

∫ ++= dtIIQQ CHEFNFGFG )(0

Static relation ( )CGFGPPGDGSGIFG VVCQQQQ −+++=

Dynamic relation

VFG

QGI, QGS, QGD

VB, VS, VD

ETUN, IFN, ICHE

QFG

VCG

QFG0

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

Characterization procedure 1/4Characterization procedure diagram

PSP model card extraction on dummy cell(optionally including thermal and geometrical scaling effects)

Hot carriers injection calibration on dummy cellUsing Ig@Vg and Ib@Vg characteristics

Fowler-Nordheim tunneling on a tunnel capacitor

Inter-polysilicium capacitor characterization

Checking of the programming window and fine tuning

PSP model card extraction on dummy cell(optionally including thermal and geometrical scaling effects)

Hot carriers injection calibration on dummy cellUsing Ig@Vg and Ib@Vg characteristics

Fowler-Nordheim tunneling on a tunnel capacitor

Inter-polysilicium capacitor characterization

Checking of the programming window and fine tuning

}

}}

s d

cg = fg

s d

cg

b

b

Dummy cell

Capacitors

Flash cell

Characterization procedure 2/4PSP model card extraction using a dummy cell

Characterization procedure 3/4Injection current calibration

Characterization procedure 4/4Fine tuning on real cell characteristics

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

Simulations 1/2Dynamic reliability (example)

VT evolutions are compared with a standard programming polarization.

VT error after programming < 0.5 V

Simulations 2/2Overall performances

Simulation slower than the single PSP model

+5 % for DC simulation+70 % for transient simulation

Internal data can be observed (as VFG)

General behavior concords with theory.

Motivation Background PSP-Based Flash cell model Characterization procedure Simulations Conclusions

ConclusionsThe proposed Flash memory cell model :

- is compact to integrate common circuit simulators.

- takes advantage of a MOS channel advanced description (using PSP).

- is written with a flexible code (Verilog-A).- can perform both DC and transient simulations.- is adapted for analysis about consumption or

injection rates.

Thanks for your attention