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CHAPTER 1
INTRODUCTION
1.1 Evolution of computer aided designs:-
VHDL is a hardware description language intended for documenting and
modeling digital System ranging from a small chip to a large system. It can be
used to model a digital system at Any level of abstraction ranging from the
architectural level down to the gate level.
The language was initially developed specially for department of defense
VHSIC (very high speed integrated circuits) contractors. However, due to an
overwhelming need in the industry For a standard hardware description language,
the VHSIC hardware description language (VHDL) was selected and later
approved to become an IEEE standard called the IEEE std 1076-1987. The
language was updated again in 1993 to include a number of clarifications in
addition to a number of new features like report statement and pulse rejection
limit.
Digital circuit design has evolved rapidly over the last 25 years. The
earliest digital circuits were designed with vacuum tubes and transistors.
Integrated circuits were then invented where logic gates were placed on a single
chip. The first integrated circuit (IC) chips were SSI (small scale integration) chips
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where the gate count was very small. As technologies became sophisticate,
designers were able to lace circuits with hundreds of gates on a single chip. The
traditional design methods are convenient as long as the system is simple and
gates involved in final implementation are limited for larger systems, inputs and
outputs are more and obtaining the truth table or table can be difficult if not
impossible and the processes started getting very complicated and designers felt
the need to automate these processes. Computer aided design (cad) techniques
began to evolve. Chip designers began to use the circuit and logic simulation
techniques to verify the functionality of building blocks of the order of about 100
transistors. The circuits were still tested on the board, and the layout was done on
paper or by hand on graphic computer terminal.
With the advent of VLSI (very large scale integration) technology,
designers could design single chips with more than 1,00,000 transistors. Because
of complexity of these circuits, it was not possible to verify these circuits on a
breadboard. Computer aided techniques became critical for verification and design
of VLSI digital circuits.
Computer programs to do automatic placement and routing for circuit
layouts also became popular. The designers were now building gate level digital
circuits manually on graphic terminals. They would build small building blocks
and then derive higher- level blocks from them. This process would continue until
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they had built the top-level block. Logic simulators came into existence to verify
the functionality of these circuits before they were fabricated on chip.
As designs got larger and more complex, logic simulation assumed an
important role in the design process. Designers could iron out functional bugs in
the architecture using simulation, before chop was designed further.
1.2 Emergence of HDLs:-
For longtime, programming languages such as FORTRAN, PASCAL and
C were being used to describe computer programming that were sequential in
nature. Similar in the digital field, designers felt the need for a standard language
to describe digital circuits. Thus, hardware description languages (HDLs) came
into the existence. HDL allowed the designers to model concurrency of processes
found in hardware elements. Hardware description languages such as verilog HDL
and VHDL became popular. Verilog HDL originating in 1983 at gateway design
automation. Later, VHDL was developed under contract from DARPA. Both
verilog and VHDL Simulators to simulate large digital circuits quickly gained
acceptance from designers.
Even though DHLS were popular for large verification, designers had to
manually translate the HDL based design into a schematic circuit with
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interconnections between gates. The advent of logic synthesis in the late 1980s
changed the design methodology radically. Digital circuits could be described at a
register transfer level (RTL) by use of a HDL. Thus, the designers had to specify
how the data flows between registers and how the design processed the data.
Logic synthesis tools from the RTL description automatically extracted the details
of gates and their interconnections to implement the circuit. Thus, logic synthesis
pushed the HDLs into forefront of digital design. Designers no longer had to
manually place gates to build logic circuits. They could describe complex circuits
at an abstract level in terms of functionality and data flow by designing those
circuits in HDLs. Logic synthesis tools would implement the specified
functionality in terms of gate interconnections.
HDLs also began to be used for system-level design. HDLs were used
for simulation of system boards, inter connect buses, FPGAs (Field Programmable
Gate Arrays) and PALs (Programmable Array Logic). A common approach is to
design each IC chip using an HDL, and then verify system functionality via
simulation.
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DESIGN SPECIFICATIONS
PHYSICAL LAYOUT
FLOOR PLANNING
BEHAVIORAL DESCRIPTION
GATE LEVEL NETLIST
LOGICAL VERIFICATION & TESTING
RTL DESCRIPTION
FUNCTIONAL VERIFICATION & TESTING
LOGIC SYNTHESIS
LAYOUT VERIFICATION
IMPLIMENTATION
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1.3 TYPICAL DESIGN FLOW:-
Typical design flow for designing VLSI IC circuits is shown in figure
fig 1.1 Typical design flow for designing VLSI IC circuits
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1.4 IMPROTANCE OF HDLs:-
HDLs have many advantages compared to traditional schematic-based design:
Design can be described at a very abstract level be use of HDLs.
Designers can write their RTL description without choosing a specific
fabrication technology. Logic synthesis tools can automatically convert
the design to any fabrication technology. If a new technology emerges
Designers don’t need to redesign their circuit. They simply input the RTL
description to the logic synthesis tools and crate a new gate-level net list.
Using the new fabrication technology.
The logic synthesis tools will optimize the circuit in area and timing for
the new technology. By describing designs in HDLs, functional
verification of the design can be done early in the design cycle. Since
designers work at the RTL level, they can optimize and modify the RTL
description until it meets the desired functionality. Most design bugs are
eliminated at this point. This cuts down design cycle time significantly
because the probability of hitting a functional bug a later time in the gate-
level net list of physical layout is minimized.
Designing with HDLs is analogous to computer programming. A textual
description with comments is an easier way to develop a circuit.
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This also provides a concise representation of the design, compared to
gate-level schematics. Gate-level schematics are almost in comprehensible for
very complex design.
HDLs are almost certainly a trend of the future. With rapidly increasing
complexities of digital circuits and increasingly sophisticated CAD tools, HDLs
will probably be the only method for large digital designs. No digital circuit
designer can afford to ignore HDL-based design.
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CHAPTER 2
INTRODUCTION TO VHDL
2.1 Use of VHDL tools in VLSI design:-
IC designers are always looking for a ways to increase their productivity
without degrading the quality of their designs. Therefore, it is no wonder that they
have embraced logic synthesis tools. In the last few years, these tools have grown
to be capable for producing designs as good as a human designer. Now logic
synthesis is helping to bring about a switch to design using a hardware description
language (HDL) to describe the structure and behavior of circuits, as evidenced
by the recent availability of logic synthesis tools using the very high speed
integrated circuit hardware description language(VHDL).
Now logic synthesis tools can automatically produce a gate level net list,
allowing designers to formulate their design in a high level description such as
VHDL.Logic synthesis provided two fundamental capabilities. Automatic
translation of high-level descriptions into logic designs, and optimization to
decrease the circuit’s area and increase its speed. Many designs created manually,
in terms of chip area occupied and ic signal speed, but are much faster to do.
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The ability to translate a high level description into a net list automatically
can improve design efficiency markedly. It quickly gives designers an accurate
estimate of their logic potential speed and chip real estate needs. In addition,
designers can quickly implement a verify of architectural choices and compare
area and speed characteristics. In a design methodology based on synthesis, the
designer begins by describing a design’s behavior in high level code, capturing its
intended functionality rather than its implementation. Once the functionality has
been thoroughly verified through simulation, the designer reformulates the design
in terms of large structural blocks such as registers, arithmetic units, storage
registers, and combinational logic typically constitutes only about 20% of a chip’s
area, creating it can easily absorb 80% of the gate level design time. The resulting
description is called register transfer level(RTL) since the equation describes how
data is transferred from one register to another.
In logic synthesis process, the tool’s first step is to minimize the logical
equations complexity and hence size by finding common terms that can be used
repeatedly. In a translation step called technology mapping, the minimized
equations are mapped into a set of gates the non-synthesized portions of the logic
are also mapped into a technology specific integrated circuit (ASIC) vendor
library in which to implement the chi, so that the logic synthesis tool may
efficiently apply the gates available in that library.
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The primary consideration in the entire synthesis process is the quality of
the resulting circuit. Quality in logic synthesis is measured by how close the
circuit comes to meeting the designer speed, chip area and power goals. These
goals can apply to the entire IC or the portions of the logic. Logic synthesis has
achieved its greatest success of synchronous designs that have significant amounts
of combinational logic. Asynchronous designs require that designers formulate
timing constraints explicitly. Unlike the behavior of synchronous designs is not
affected by events such as the arrival of signals.
By devising a set of constraints that the synthesis tools have to meet, the
designer directs the process towards the most desirable solution. Although it
might be desirable to build a give circuit that is both small and fast, area typically
trades off with speed. Thus, designers must choose the trade off point that is best
for a specific.
The ability to steer the synthesis process towards various solutions allows
designers to implement rapidly many versions of a circuit and choose the solution
best suited for their specific situation. Designers can therefore explore their
options in a way that has not been practical before. The ability of synthesis tools
to synthesize sequential logic and optimize it in any chosen technology makes
designs quickly as improved technologies become available and to try out a
circuit in several technologies and then choose the best one. Furthermore,
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modifying logic manually is tedious and takes a great deal of time, so those
human designers do as little of it as possible. Syntheses tools, on others hand
make many process overall the possible logic combinations of a circuit. Tight
integration of timing analysis with in the optimization algorithms enables some
synthesis system to quickly find circuit critical paths – the path determines the
overall clock rate and re-optimize when necessary. Thus in a fraction of time it
would take a designer to do one manual version, the tools iterate through many
solutions to determine the best one. When a designer starts a synthesis process
by translating an RTL description into a netlist, the synthesis tools must first be
able to understand the RTL description. A number of languages known as the
hardware description languages (HDLs) have been developed for this purpose.
HDL Statements can be describing circuits in terms of the structure of he
structures or behavior or both. One reason HDLs are so powerful, in fact is that
they support both a variety of design description. A HDL simulator handles all
those descriptions, applying the same simulation and test vectors from the design
behavioral level all the way down to the gate level. This integrated approach
reduces the problems that can result from different descriptions of the same
design. As logic synthesis matures, it will allow designers to concentrate less on
the details of the circuit and more on its actual function and behavior. Logic
synthesis tools are becoming capable of more behavioral- level tasks, such as
synthesizing sequential logic and deciding if and where the storage elements are
needed in a design. Existing logic synthesis tools are moving up the designer
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ladder, while behavioral research is extending down to the RTL level. Eventually
they will merge, given designers a complete set of tools to automate designs from
concept to layout.
2.2 Scope of VHDL:-
VHDL satisfies all the requirements for the hierarchical description of
electronic circuits from system level down to switch level. It can support all levels
of timing specification and constraints and is capable of detecting and signaling
timing violations. The language models the reality of concurrency present in
digital system and supports the recursively of finite state machines. The concept
of packages and configurations allow the creation of design libraries for the reuse
of previously designed parts.
2.3 WHY VHDL?
A design engineer in electronic industry used hardware description
language to keep pace with the productivity of the competitors. With VHDL we
can quickly describe the capability described as follows:
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2.3.1 Power and flexibility:-
VHDL has powerful language constructs with which to write succinct
code descriptions of complex control logic. It also has multiple levels of design
description for controlling design implementation. It supports design libraries and
creation of reusable language for design and simulation.
2.3.2 Devices- independent design:-
VHDL permits to create a design with out to first choose a device
implementation. With one design description, we can target many device
architectures. Without being familiar with it, we can optimize our design for
resource utilization performance. It permits multiple style of design description.
2.3.3 Portability:-
VHDL portability permits to simulate the same design description that we
have synthesized. Simulating a large description before synthesizing can save
considerable time. As VHDL is a standard, design description can be taken from
one simulator to another, one synthesis tool to another, and one platform to
another means design description can be used in multiple projects.
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2.3.4 Benchmarking capabilities:-
Device independent design and portability allows benchmarking a design
using different device architectures and different synthesis tools. We can take a
completed design description and synthesize it, create logic for it, evaluate the
results and finally choose the device-a CLD or an FPGA that best fits our design
requirements.
2.3.5 ASIC Migration:-
The efficiency that VHDL generated, allows our product to hit the market
quickly if it has been synthesized on a CPLD or FPGA. When production volume
reaches appropriate levels, VHDL facilitates the development of application
specific integrated circuit (ASIC). Sometimes, the exact code used with the PLD
can be used with the ASIC and because VHDL is a well –defined language, we
can be assured that out ASIC vendor will deliver a device with expected
functionality.
2.3.6 Quick Time-to-Market and low cost:-
VHDL and programmable logic pair will together facilitate a speedy
design process. VHDL permits to be described quickly. Programmable logic
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eliminates NRE expenses and facilitates quick design iterations. Synthesis makes
it all possible. VHDL and programmable logic as powerful vehicle to bring the
products in market record time.
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CHAPTER 3
DESIGN SYNTHESIS
The design process can be explained in six steps:
1. Define the design requirements.
2. Describe the design in VHDL (formulate and code the design).
3. Simulate the source code.
4. Synthesis, optimize and fit the design on to a suitable device.
5. Simulate the post-layout design model.
6. Progress the device.
3.1 Define the design requirements
Before launching into writing code for our design, we must have a clear
idea of design objective and requirements. That is, the function of the design
required setup and clock-to-output times, maximum frequency of operation and
critical paths.
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3.2 Describe the design in VHDL
Formulate the design: having and idea of design requirements, we have to
write an efficient code that is realized, through synthesis, to the logic
implementation we intended. Code the design: after deciding upon a design
methodology, we should code the design referring to the block, dataflow, and
state diagrams such that the code is syntactically and semantically correct.
3.3 Stimulate the source code
With source code simulation, flaws can be detected early in the design
cycle, allowing us to make corrections with the least possible impact o the
schedule. This is more efficient for larger designs, for which synthesis and lace
and route can take a couple of hours.
3.4 Synthesis, Optimize, and Fit the design
3.4.1 Synthesis:
It is a process by which net lists or equations are created from design
descriptions, which many be abstracted. VHDL synthesis software tools convert
VHDL descriptions to technology specific net lists or set of equations.
3.4.2 Optimization:
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The optimization process depends on three things: the form of the Boolean
expression, the type of resources available and automatic or used applied
synthesis directives (sometimes called constraints). Optimization for CPLDs
involves reducing the logic to minimal sum-of- products, which is then further
optimized for a minimal literal count. This reduces the product-term utilization
and number of logic block inputs required for any given expression.
3.4.3 Fitting:
Fitting is process of taking the logic produced by the synthesis and
optimization process, and placing it into a logic device, transforming the logic (if
necessary) to obtain the best fit. It is a term typically used to describe the process
of allocating resources for CPLD-type architectures.
3.5 Simulate the Post-layout design model
A post layout simulation will enable us to verify, not only the functionality
of our design, but also timing, such as setup, clock-to-output, and register-to-
register times. If we are unable to meet our design objectives, then we need to
either resynthesize, and/or fit our design to a new logic device.
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CHAPTER 4
PROGRAMMABLE LOGIC PRIMERS
In this chapter, we introduce the defining features of programmable logic
design architectures and of many popular devices, as well as the decisions that go
into selecting on appropriate device for an application.
4.1 Complex Programmable Logic devices (CPLD)
CPLDs extend the concept of the PLD to higher level of integration to
improve system performance; they also use less board space, improve reliability
and reduce cost. Instead of making the PLD larger with more inputs, product
terms and macro cells. A CPLDs contains multiple logic blocks, each similar to a
small PLD like the 22V10. The logic blocks communicate with one another using
signals routed via a programmable interconnects. This architectural arrangement
makes more efficient use of the available silicon die area, leading to better
performance and reduced cost.
4.1.1 Programmable interconnects
The programmable interconnect (PI) routes signals from i/os to logic block
inputs, or from block outputs(macro cell outputs) to the inputs of he it or other
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logic blocks. Some logic blocks have local feedback so that macro cell outputs
used in the same logic block do not route through the global programmable
interconnect.
Most CPLDs use one of the two implementations for the programmable
interconnect: Array based interconnects or multiplexer based interconnect. Array
based interconnect allows any signal in the PI to route to any logic block. Each
term in the pi is represented by a vertical wire and is assigned as an input (through
a sense amplifier) to a given logic block, so there is one PI term for each input to
a logic block. An output from a logic block can connect to PI terms through a
memory element (such as an EPROM cell). Device inputs can connect to PI terms
as well. This interconnect scheme implement a full cross-point switch, that is, it is
fully routable. Any input to the programmable interconnect can be routed into any
logic block, provide that not all of the inputs to a logic block are already being
used. With multiplexer based interconnect; there is one multiplexer for each input
to a logic block. Signals in the PI are connected to the inputs of a number of
multiplexer are programmed to allow one input for each multiplexer to propagate
into a logic block. Using wider multiplexer, allowing each signal the PI to connect
to the input, increases routability in the PI to connect to the input of several
multiplexer for each logic block.
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4.1.2 Logic blocks
Each logic block has product term array, a product term distribution scheme and
macro cells. The size of a block is a measure of its capacity; it is typically
expressed in the terms of macro cells. Also important are the number of inputs to
the logic block the number of terms and the product terms and the product term
distribution scheme. A logic block usually ranges in size from 4 to 20 macro cells.
Sixteen or more macro cells logic block enough inputs from PI to the logic block
exists.
4.1.3 Produt-term arrays
The size of the array identifies the average number of the product terms per
macro cell and maximum number of product terms per logic block. Each CPLD
will have a specific product term array.
4.1.4 Product-term distribution.
Cypress and MAX family allocated four product terms per macro cell
while allowing expander product-terms, to allocate individually t any micro cell
or macro cell. With expander product-terms, the additional products-terms are
allocated only to those macro cells that can make use of them. Concept that a
particular macro cell can use a product-term is term and product-term steering and
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the concept that the multiple macro cells may use same product- term is termed
product-term sharing.
4.1.5 Macro cells
CPLDs include macro cells that provide flip-flops and polarity control.
Polarity control enables the implementation of either the true or the complement
of an expression. CPLDs have i/o macro cells, input macro cells and buried macro
cells. An input macro cell is associated with pin. Buried macro cell is similar to
i/o macro cell expect that its output can propagate directly to an i/o, rather its
output its output is fed back to PI.
4.1.6 I/O Cells
I/O cells are used to drive a signal off the device, depending on the state of
output enable and to provide a data for incoming signals. I/o cells contains switch
matrix or output routing pools in which a one-to-one connection is made between
an i/o macro cell output and an i/o, advantage of this scheme is flexibility in
determining where logic can be placed in a logic block in relation to where the i/o
cell is located.
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CHAPTER 5
FIELD PROGRAMMABLE GATE ARRAY
5.1 Field programmable gate arrays (FPGA)
A field-programmable gate array (FPGA) is an integrated circuit designed
to be configured by the customer or designer after manufacturing—hence "field-
programmable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific
integrated circuit (ASIC) (circuit diagrams were previously used to specify the
configuration, as they were for ASICs, but this is increasingly rare). FPGAs can
be used to implement any logical function that an ASIC could perform. The
ability to update the functionality after shipping, partial re-configuration of a
portion of the design and the low non-recurring engineering costs relative to an
ASIC design (notwithstanding the generally higher unit cost), offer advantages for
many applications.
FPGAs contain programmable logic components called "logic blocks",
and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"—somewhat like many (changeable) logic gates that can be inter-wired
in (many) different configurations. Logic blocks can be configured to perform
complex combinational functions, or merely simple logic
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gates like AND and XOR. In most FPGAs, the logic blocks also include memory
elements, which may be simple flip-flops or more complete blocks of memory.
In addition to digital functions, some FPGAs have analog features. The most
common analog feature is programmable slew rate and drive strength on each
output pin, allowing the engineer to set slow rates on lightly loaded pins that
would otherwise ring unacceptably, and to set stronger, faster rates on heavily
loaded pins on high-speed channels that would otherwise run too slow. Another
relatively common analog feature is differential comparators on input pins
designed to be connected to differential signaling channels.
A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital
Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal
conditioning blocks allowing them to operate as a system-on-a-chip. Such devices
blur the line between an FPGA, which carries digital ones and zeros on its internal
programmable interconnect fabric, and field-programmable analog array (FPAA),
which carries analog values on its internal programmable interconnect fabric.
FPGA architecture is an array of logic cells that communicate with i/o via
wires routing channels. In a FPGA, existing wire resources that run in horizontal
and vertical columns (routing channels) are connected via programmable
elements. These routing wires also connect logic to i/0s. Logic cells have less
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functionality than the combined product terms and macro cells of CPLDs, but
large functions can be created cascading logic cells.
1. Performance- the ability for real system design to operate at
increasingly higher frequencies.
2. Density and capacity- the ability to increase integration, to place more
and more in a chip (system in a chip), and use all available gates with
in the FPGA, they’re by providing a cost effective solution.
3. Ease of use – the ability for system designers to bring their products
to market quickly, leveraging the availability of easy-to-use software
tools for logic synthesis as well as lace and route, in addition to
architectures that enables late design that effect logic, routing, and i/o
resources without a significantly adverse effect on timing.
4. In- system programmability and in circuit re-programmability the
ability to program or reprogram a device while it is in-system,
mainstreaming, and inverters as well as allowing for field upgrades
and user configurability.
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5.1 History
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). PROMs and PLDs both had the option of
being programmed in batches in a factory or in the field (field programmable),
however programmable logic was hard-wired between logic gates.In the late
1980s the Naval Surface Warfare Department funded an experiment proposed by
Steve Casselman to develop a computer that would implement 600,000
reprogrammable gates. Casselman was successful and a patent related to the
system was issued in 1992.
Some of the industry’s foundational concepts and technologies for
programmable logic arrays, gates, and logic blocks are founded in patents
awarded to David W. Page and LuVerne R. Peterson in 1985.
Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented
the first commercially viable field programmable gate array in 1985 – the
XC2064. The XC2064 had programmable gates and programmable interconnects
between gates, the beginnings of a new technology and market. The XC2064
boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup
tables (LUTs). More than 20 years later, Freeman was entered into the National
Inventors Hall of Fame for his invention.
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Xilinx continued unchallenged and quickly growing from 1985 to the mid-
1990s, when competitors sprouted up, eroding significant market-share. By 1993,
Actel was serving about 18 percent of the market.
The 1990s were an explosive period of time for FPGAs, both in
sophistication and the volume of production. In the early 1990s, FPGAs were
primarily used in telecommunications and networking. By the end of the decade,
FPGAs found their way into consumer, automotive, and industrial applications.
FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a
researcher working at the University of Sussex, merged genetic algorithm
technology and FPGAs to create a sound recognition device.
Thomson’s algorithm configured an array of 10 x 10 cells in a Xilinx FPGA chip
to discriminate between two tones, utilising analogue features of the digital chip.
The application of genetic algorithms to the configuration of devices like FPGAs
is now referred to as Evolvable hardware.
5.2 FPGA design and programming
To define the behavior of the FPGA, the user provides a hardware
description language (HDL) or a schematic design. The HDL form is more suited
to work with large structures because it's possible to just specify them numerically
rather than having to draw every piece by hand. However, schematic entry can
allow for easier visualisation of a design.
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Then, using an electronic design automation tool, a technology-mapped
netlist is generated. The netlist can then be fitted to the actual FPGA architecture
using a process called place-and-route, usually performed by the FPGA
company's proprietary place-and-route software. The user will validate the map,
place and route results via timing analysis, simulation, and other verification
methodologies. Once the design and validation process is complete, the binary file
generated (also using the FPGA company's proprietary software) is used to
(re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial
interface (JTAG) or to an external memory device like an EEPROM.
The most common HDLs are VHDL and Verilog, although in an attempt
to reduce the complexity of designing in HDLs, which have been compared to the
equivalent of assembly languages, there are moves to raise the abstraction level
through the introduction of alternative languages. National
Instrument's LabVIEW graphical programming language (sometimes referred to
as "G") has an FPGA add-in module available to target and program FPGA
hardware.
To simplify the design of complex systems in FPGAs, there exist libraries
of predefined complex functions and circuits that have been tested and optimized
to speed up the design process. These predefined circuits are commonly called ip
cores and are available from FPGA vendors and third-party IP suppliers (rarely
free, and typically released under proprietary licenses). Other predefined circuits
are available from developer communities such as OpenCores (typically released
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under free and open source licenses such as the GPL, BSD or similar license), and
other sources.
In a typical design flow, an FPGA application developer will simulate the
design at multiple stages throughout the design process. Initially the
RTL description in VHDL or Verilog is simulated by creating test benches to
simulate the system and observe results. Then, after the synthesis engine has
mapped the design to a netlist, the netlist is translated to a gate level description
where simulation is repeated to confirm the synthesis proceeded without errors.
Finally the design is laid out in the FPGA at which point propagation delays can
be added and the simulation run again with these values back-annotated onto the
netlist.
5.3 Spartan-3E FPGA:
5.31Features
• Low-cost, high-performance logic solution for high-volume, consumer-
oriented applications.
• SelectIO™ interface signaling.
- 622+ Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 8 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.465V
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- Double Data Rate (DDR) support
- DDR, DDR2 SDRAM support up to 333 Mbps
• Logic resources
- Abundant logic cells with shift register capability
- Wide, fast multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE®
• MicroBlaze™ and PicoBlaze™ process
• Pb-free packaging options
• Automotive Spartan-3 XA Family variant.
5.4 Spartan-3E FPGA Compatibility
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Within the Spartan-3 family, all devices are pin-compatible by package.
When the need for future logic resources outgrows the capacity of the Spartan-3
device in current use, a larger device in the same package can serve as a direct
replacement. Larger devices may add extra VREF and VCCO lines to support a
greater number o I/Os. In the larger device, more pins can convert from user I/Os
to VREF lines.
Also, additional VCCO lines are bonded out to pins that were “not
connected” in the smaller device. Thus, it is important to plan for future upgrades
at the time of the board’s initial design by laying out connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previous Xilinx
FPGA family or with other platforms among the Spartan-3 Generation FPGAs.
Rules Concerning Banks When assigning I/Os to banks, it is important to follow
the following VCCO rules:
Leave no VCCO pins unconnected on the FPGA. Set all VCCO lines
associated with the (interconnected) bank to the same voltage level. The VCCO
levels used by all standards assigned to the I/Os of the (interconnected) bank(s)
must agree. TheXilinx development software checks for this. Only one of the
following standards is allowed onoutputs per bank: LVDS, LDT, LVDS_EXT, or
RSDS. This restriction is for the eight banks in each device, even if the VCCO
levels are shared across banks, as in the CP132 and TQ144 packages. If none of
the standards assigned to the I/Os of the (interconnected) bank(s) uses VCCO, tie
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all associatedVCCO lines to 2.5V.In general, apply 2.5V to VCCO Bank 4 from
power-on to the end of configuration. Apply the same voltage to VCCO Bank 5
during parallel configuration or a Readback operation. For information on how to
program the FPGA using 3.3V signals and power, see the 3.3V-Tolerant
Configuration Interface section.
CHAPTER 6
INTRODUCTION TO TRAFFIC LIGHT
CONTROLLER
6.1 INTRODUCTION
Traffic lights are integral part of modern life. Their proper
operation can spell the difference between smooth flowing traffic and
four-lane gridlock. Proper operation entails precise timing, cycling
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through the states correctly, and responding to outside inputs. The traffic
light controller is designed to meet a complex specification. That
specification documents the requirements that a successful traffic light
controller must meet. It consists of an operation specification that
describes the different functions the controller must perform, a user
interface description specifying what kind of interface the system must
present to users, and a detailed protocol for running the traffic lights. Each
of these requirements sets imposed new constraints on the design and
introduced new problems to solve. The controller to be designed controls
the traffic lights of a busy highway (HWY) intersecting a side road (SRD)
that has relatively lighter traffic load. Figure 1.1 shows the location of the
traffic lights. Sensors at the intersection detect the presence of cars on the
highway and side road.
Fig 6.1. Crossover between side road and highway
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The heart of the system is a finite state machine (FSM) that directs
the unit to light the main and side street lights at appropriate times for the
specified time intervals. This unit depends on several inputs which are
generated outside the system. In order to safely process these external
inputs, we can design an input handler that synchronizes asynchronous
inputs to the system clock. The input handler also latches some input
signals and guarantees that other input signals will be single pulses,
regardless of their duration. This pulsification greatly simplifies the design
by ensuring that most external inputs are high for one and only one clock
cycle. In addition to the FSM and input handler, the design also includes a
slow clock generator. Because the specification requires that timing
parameters are specified in seconds, the controller needs to be informed
every second that a second of real time has elapsed. The slow clock solves
this problem by generating a slow clock pulse that is high for one cycle on
the system clock during every second of real time. In addition to
generating a once per second pulse, we need to be able to count down
from a specified number of seconds. The timer subsystem does that job.
When given a particular number of seconds to count down from, it informs
the FSM controller after exactly that number of seconds has elapsed.
Finally, we have storage and output components. In order to store the
users timing parameters, we use a static RAM whose address and control
lines are supplied by the FSM. The RAM data lines are on a tristate bus
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which is shared by the timer unit and a tristate enabled version of the data
value signals. This same bus can drive the HEX-LED display, which
comprises the output subsystem along with the actual traffic light LEDs.
The heart of the controller is the FSM. This FSM controls the loading of
static RAM locations with timing parameters, displaying these parameters
by reading the RAM locations, and the control of the actual traffic lights.
The timer and the divider control various timing issues in the system. The
timer is a counter unit that counts for a number of one second intervals that
are specified by data stored in the static RAM. The divider provides a one-
second clock that is used by the timer as a count interval. Lastly, the
synchronizers ensure that all inputs to the FSM are synchronized to the
system clock.
6.2 LITERATURE REVIEW
Intelligent Transportation Systems (ITS) applications for traffic
signals – including communications systems, adaptive control systems,
traffic responsive, real-time data collection and analysis, and maintenance
management systems – enable signal control systems to operate with
greater efficiency. Sharing traffic signal and operations data with other
systems will improve overall transportation system performance in
freeway management, incident and special event management, and
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maintenance/failure response times. Some examples of the benefits of
using ITS applications for traffic signal control include: Updated traffic
signal control equipment used in conjunction with signal timing
optimization can reduce congestion. The Texas Traffic Light
Synchronization program reduced delays by 23 percent by updating traffic
signal control equipment and optimizing signal timing. Coordinated signal
systems improve operational efficiency. Adaptive signal systems improve
the responsiveness of signal timing in rapidly changing traffic conditions.
Various adaptive signal systems have demonstrated network performance
enhancement from 5 percent to over 30 percent. Traffic light controller
communication and sensor networks are the enabling technologies that
allow adaptive signal control to be deployed. Incorporating Traffic light
controller into the planning, design, and operation of traffic signal control
systems will provide motorists with recognizable improvements in travel
time, lower vehicle operating costs, and reduced vehicle emissions. There
are more than 330,000 traffic signals in the United States, and, according
to U.S. Department of Transportation estimates, as many as 75 percent
could be made to operate more efficiently by adjusting their timing plans,
coordinating adjacent signals, or updating equipment. In fact, optimizing
signal timing is considered a low-cost approach to reducing congestion,
costing from $2,500 to $3,100 per signal per update. ITS technology
enables the process of traffic signal timing to be performed more
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efficiently by enhancing data collection and system monitoring capabilities
and, in some applications, automating the process entirely. ITS tools such
as automated traffic data collection, centrally controlled or monitored
traffic signal systems, closed loop signal systems, interconnected traffic
signals, and traffic adaptive signal control help make the traffic signal
timing process efficient and cost effective. Several municipalities have
worked to synchronize, optimize, or otherwise upgrade their traffic signal
systems in recent years. Below is an example of the benefits some have
realized:
The Traffic Light Synchronization program in Texas shows a
benefit-cost ratio of 62:1, with reductions of 24.6 percent in delay, 9.1
percent in fuel consumption, and 14.2 percent in stops. The Fuel Efficient
Traffic Signal Management program in California showed a benefit-cost
ratio of 17:1, with reductions of 14 percent in delay, 8 percent in fuel
consumption, 13 percent in stops, and 8 percent in travel time.
Improvements to an 11-intersection arterial in St. Augustine, Florida,
showed reductions of 36 percent in arterial delay, 49 percent in arterial
stops, and 10 percent in travel time, resulting in an annual fuel savings of
26,000 gallons and a cost savings of $1.1 million. Although
communications networks allow almost instantaneous notification of
equipment failure, without which some failures may go unnoticed for
months, there must be staff available to respond
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6.3 PROTOCOL
The protocol or the design rules we incorporated in designing a
traffic light controller are laid down:-
We too have the same three standard signals of a traffic light
controller that is RED, GREEN, and YELLOW which carry their usual
meanings that of stop go and wait respectively.
We have two roads – the highway road and the side road or
country road with the highway road having the higher priority of the two
that is it is given more time for motion which implies that the green signal
remains for a longer time along the highway side rather than on the
country side. We have decided on having a green signal or motion signal
on the highway side for a period of 80 seconds and that on the country
road of 40 seconds and the yellow signal for a time length of 20 seconds.
We can have provisions for two exceptions along the roads one
along the highway and the other along the country side which interrupt the
general cycle whenever a exceptions like an emergency vehicle or any
such kind of exceptions which have to be addressed quickly. When these
interrupts occur the normal sequence is disturbed and the cycle goes into
different states depending on its present state and the interrupt occurrs.
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We have taken into consideration a two way traffic that is the
opposite directions along the highway side will be having the same signals
that is the movements along the both direction on a single road will be
same at any instant of time. This ensures no jamming of traffic and any
accidents at the turnings.
6.4 THE OBJECTIVES
The following line up as the main objectives of the project.
1. Transform the word description of the protocol into a finite state
machine transition diagram.
2. Implement a simple finite state machine using VHDL.
3. Simulate the operation of the finite state machine.
4. Implement the design onto a FPGA.
CHAPTER 7
THE STATE MACHINE
7.1 THE FINITE STATE MACHINE
The FSM-FINITE STATE MACHINE is the heart of traffic light
controller. It responds to the input signals processed by the input handling
module and provides the output and control signals needed to make the
system function. This design uses a standard two process finite state
machine where one process is used to change states on every clock cycle
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while the other process is used to combinatorically calculate what the next
state should be based on the current inputs and the current state. That
combinatorial process also sets the outputs for the next clock cycle.
The FSM has four main groups of states corresponding to the
four modes in which the traffic light controller can operate. The read
function causes the controller to enter the memory read state. Once in that
state, the system remains there until reset, using whatever value is on the
timing parameter selection switches for the RAM address. The memory
read state also ensures that write enable for the RAM is disabled since the
system is only trying to read previously stored values in RAM. The second
major state group corresponds to the memory write function. In this mode,
the FSM transitions to the memory write state and then returns to the start
state. When in the memory write state, the system uses the value of the
timing parameter selection switches for the RAM address lines as in the
memory read state, but asserts the memory write enable control signal.
This ensures that the new value is actually written to RAM. One crucial
feature of this design is that the system is only in the memory write state
for one cycle; thus the RAM write enable is never high for more than a
single clock cycle. That ensures that we never write to the RAM while
either data or address values are changing.
7.1.1 DEFINITION OF THE FSM
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A finite-state machine (FSM) or finite-state automation , or simply
a state machine, is a mathematical abstraction sometimes used to
design digital logic or computer programs. It is a behavior model
composed of a finite number of states, transitions between those states,
and actions, similar to a flow graph in which one can inspect the
way logic runs when certain conditions are met. It has finite internal
memory, an input feature that reads symbols in a sequence, one at a time
without going backward; and an output feature, which may be in the form
of a user interface, once the model is implemented. The operation of an
FSM begins from one of the states (called a start state), goes through
transitions depending on input to different states and can end in any of
those available, however only a certain set of states mark a successful flow
of operation (called accept states).
7.1.2 Notion of States in Sequential Machines
A state machine is a type of sequential circuit structure which can
allow you to create more elaborate types of digital systems. A state
machine consists of:
1) memory elements (e.g. D flip-flops) to store the current state
2) combinational logic to compute the next state
3) combinational logic to compute the output
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7.1.2 WORKING PRINCIPLE OF AN FSM
Finite state machines consist of 4 main elements-
- states which define behavior and may produce actions.
- state transitions which are movement from one state to another.
- rules or conditions which must be met to allow a state transition.
- input events which are either externally or internally generated, which
may possibly
trigger rules and lead to state transitions.
A current state is determined by past states of the system. As such,
it can be said to record information about the past, i.e., it reflects the input
changes from the system start to the present moment. The number and
names of the states typically depend on the different possible states of the
memory, e.g. if the memory is three bits long, there are 8 possible states.
A transition indicates a state change and is described by a condition that
would need to be fulfilled to enable the transition. An action is a
description of an activity that is to be performed at a given moment. There
are several action types:
Entry action
which is performed when entering the state
Exit action
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which is performed when exiting the state
Input action
which is performed depending on present state and input conditions
Transition action
which is performed when performing a certain transition.
7.1.3 IMPLEMENTATION OF A FSM
State Variable: The variable held in the SM (FF) that determines its present state.
A basic FSM has a memory section that holds the present state of
the machine (stored in FF) and a control section that controls the next state
of the machine (by clocks, inputs, and present state).The outputs and
internal flip flops (FF) progress through a predictable sequence of states in
response to a clock and other control inputs.
A finite state machine must have an initial state which provides a
starting point, and a current state which remembers the product of the last
state transition. Received input events act as triggers, which cause an
evaluation of some kind of the rules that govern the transitions from the
current state to other states. The best way to visualize a FSM is to think of
it as a flow chart or a directed graph of states, though as will be shown;
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there are more accurate abstract modeling techniques that can be used.
Fig 7.1 A POSSIBLE FINITE STATE MACHINE
7.1.4 ADVANTAGES OF FSM
- Their simplicity make it easy for inexperienced developers to implement
with little to no extra knowledge (low entry level)
- Predictability (in deterministic FSM), given a set of inputs and a known
current state, the state transition can be predicted, allowing for easy testing
- Due to their simplicity, FSMs are quick to design, quick to implement
and quick in execution
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- FSM is an old knowledge representation and system modeling
technique, and its been around for a long time, as such it is well proven
even as an artificial intelligence technique, with lots of examples to learn
from
- FSMs are relatively flexible. There are a number of ways to implement a
FSM based system in terms of topology, and it is easy to incorporate many
other techniques
- Easy to transfer from a meaningful abstract representation to a coded
implementation
- Low processor overhead; well suited to domains where execution time is
shared between modules or subsystems. Only the code for the current state
need be executed, and perhaps a small amount of logic to determine the
current state.
- Easy determination of reachability of a state, when represented in an
abstract form, it is immediately obvious whether a state is achievable from
another state, and what is required to achieve the state.
7.2 TYPES OF STATE MACHINES
There are two basic ways to design clocked sequential circuits ,i.e.,
the state machines.
7.2.1 MEALY MACHINE
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In the theory of computation, a Mealy machine is a finite-
state machine whose output values are determined both by its
current state and by the values of its inputs. The state diagram for a Mealy
machine associates an output value with each transition edge (in contrast
to the state diagram for a Moore machine, which associates an output
value with each state). In a Mealy machine, the outputs are a function of
the present state and the value of the inputs. Accordingly, the outputs may
change asynchronously in response to any change in the inputs. A
combinational logic block maps the inputs and the current state into the
necessary flip-flop inputs to store the appropriate next state just like
Mealy machine. However, the outputs are computed by a combinational
logic block whose inputs
are only the flip-flops
state outputs.
fjig
7.2.2 MOORE MACHINE
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A Moore machine is a finite-state machine whose output
values are etermined solely by its current state. (This is in contrast to a
Mealy machine, whose output values are determined both by its current
state and by the values of its inputs.) The state diagram for a Moore
machine associates an output value with each state (in contrast to the state
diagram for a Mealy machine, which associates an output value with each
transition edge).
A combinational logic block maps the inputs and the current state
into the necessary flip-flop inputs to store the appropriate next state just
like Mealy machine. However, the outputs are computed by a
combinational logic block whose inputs are only the flip-flops state
outputs. The outputs change synchronously with the state transition
triggered by the active clock edge.
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fhdhhj
7.2.3 MECHANISM
Most digital electronic systems are designed as clocked
sequential systems. Clocked sequential systems are a restricted form of
Moore machine where the state changes only when the global clock signal
changes. Typically the current state is stored in flip-flops, and a global
clock signal is connected to the "clock" input of the flip-flops. A typical
electronic Moore machine includes a combinational logic chain to decode
the current state into the outputs (lambda). The instant the current state
changes, those changes ripple through that chain, and almost
instantaneously the outputs change (or don't change). There are design
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techniques to ensure that no glitches occur on the outputs during that brief
period while those changes are rippling through the chain, but most
systems are designed so that glitches during that brief transition time are
ignored or are irrelevant. The outputs then stay the same indefinitely
(LEDs stay bright, power stays connected to the motors, solenoids stay
energized, etc.), until the Moore machine changes state again.
7.2.4 FSM DESIGN TECHNIQUES
FSM’s can be designed in two appropriate ways.
Classical Design: Makes use of state tables, FF excitation tables, and
Karnaugh Mapping to find FF input control logic.
VHDL Design: Uses case statements or IF THEN ELSE statements to set
the design and the logic synthesis tools to define equation.
7.2.5 CLASSICAL DESIGN APPROACH
1. Define the actual problem.
2. Draw a state diagram (bubble) to implement the problem.
3. Make a state table. Define all present states and inputs in a binary
sequence.
4. Then define the next states and outputs from the state diagram.
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5. Use FF excitation tables to determine in what states the FF inputs must
be to cause a present state to next state transition.
6. Find the output values for each present state/input combination.
7. Simplify Boolean logic for each FF input and output equations and
design logic.
7.2.6 VHDL FSM DESIGN APPROACH
Uses an enumerated type to declare state variables.
Enumerated Type: A user-defined type in which all possible values of
a named identifier are listed in a type definition.
An FSM uses a CASE statement on the enumerated type state
variable.
Without any doubt, we proceed with the VHDL design approach
for implementation of our design .
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STATE DIAGRAM FOR TRAFFIC LIGHT CONTROLLER
Fig 7.1 State diagram for Traffic light controller
We consider 2 roads opposite to each other with 5 possible states from 1 to
5. We initially reset them, so that State S0 shows red on both signals.
After a certain time period, moving to state 1, signal on 1 side goes read
and other goes green. And again upto a certain time count, the changes to
red and yellow and then moves to state 3 where the lights change to red
both. A Similar process takes place for the remaining states
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CHAPTER 8
XILINX
8.1 INTRODUCTION
Xilinx leads one of the fastest growing segments of the semiconductor
industry – programmable logic devices.
8.1.1 Xilinx FPGAs
The Xilinx FPGA Spartan3e series has redefined programmable logic by
expanding the traditional capabilities of field programmable gate arrays
(FPGAs) with new levels of integration and features that address high
performance system design issues. In a single, off-the-shelf programmable
Xilinx device, systems architects can take advantage of microprocessors, the
highest density of on-chip memory, multi-gigabit serial transceivers, digital
clock managers, on-chip termination and more. The result is that Xilinx FPGAs
helps designers to simplify board layout, reduce bill of materials, and get
products to market faster than ever before.
Xilinx FPGA Spartan3e FPGAs are available with up to four immersed
IBM PowerPC 405 processors and up to 16 high-speed transceivers that operate
at 3.125 gigabits per second. Xilinx Rocket I/O transceivers offer a complete
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serial interface solution, supporting 10 Gigabit Ethernet with XAUI, PCI
Express and SerialATA. Each IBM PowerPC in Xilinx FPGA Spartan3e FPGAs
run at 300-plus MHz, delivering 450 Dhrystone MIPS, and is supported by IBM
CoreConnect bus technology. With Xilinx FPGA Spartan3e FPGAs, systems
designers can for the first time partition and repartition their systems between
hardware and software at any time during the development cycle, even after the
product has shipped, and debug hardware and software simultaneously at speed.
Xilinx FPGA Spartan3e devices range in density from 3,168 to 50,832 logic
cells.
8.2. Overview of ISE and Synthesis Tools
Overview of ISE
ISE controls all aspects of the design flow. Through the Project Navigator
interface, you can access all of the various design entry and design
implementation tools. You can also access the files and documents associated with
your project. Project Navigator maintains a flat directory structure; therefore, you
can maintain revision control through the use of snapshots.
Project Navigator Interface
The Project Navigator Interface is divided into four main sub windows, as seen in
Figure 1-1. On the top left is the Sources in Project window which hierarchically
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displays the elements included in the project. Beneath the Sources in Project
window is the Processes for Current Source window which displays available
processes. The third window at the bottom of the Project Navigator is the Console
window which displays status messages, errors, and warnings, and which is
updated during all project actions. The fourth window to the right is a multi-
document Interface (MDI) window for viewing ASCII text files and HDL
Bencher™ Waveforms. Each window may be resized, undocked from Project
Navigator or moved to a new location within the main Project Navigator window.
Selecting View Restore. Default Layout can always restore the default layout.
These windows are discussed in more detail in the following sections.
Figure 1-1: Project Navigator
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Sources in Project Window
This window consists of three tabs, which provide information for the
user. Each tab is discussed in further detail below.
Module View
The Module View tab displays the project name, any user documents, the
specified part type and design flow/synthesis tool, and design source files. Each
file in the Module View has an associated icon. The icon indicates the file type
(HDL file, schematic, core, or text file, for example). For a complete list of
possible source types and their associated icons, seethe Project Navigator online
help. Select Help_ISE Help Contents, select the Index tab and click Source / file
types. If a file contains lower levels of hierarchy, the icon has a + to the left of the
name. HDL files have this + to show the entities (VHDL) or modules (Verilog)
within the file. You can expand the hierarchy by clicking the +. You can open a
file for editing by double-clicking on the filename.
Snapshot View
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The Snapshot View tab displays all snapshots associated with the project
currently open in Project Navigator. A snapshot is a copy of the project including
all files in the working directory, and synthesis and simulation subdirectories. A
snapshot is stored with the project for which is taken, and can be viewed in the
Snapshot View. You can view the reports, user documents, and source files for all
snapshots. All information displayed in the Snapshot View is read-only. Using
snapshots provides an excellent version control system, enabling sub teams to do
simultaneous development on the same design.
Library View
The Library View tab displays all libraries associated with the project open
in Project Navigator.
Processes for Current Source Window
This window contains the Process View tab.
Process View
The Process View tab is context sensitive and changes based upon the source
type selected in the Sources for Project window. From the Process View tab, you
can run the functions necessary to define, run and view your design. The Process
Window provides access to the following functions
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Design Entry Utilities
Provides access to symbol generation, instantiation templates, HDL Converter,
View Command Line Log File, Launch MTI, and simulation library compilation.
User Constraints
Provides access to editing location and timing constraints.
Synthesis
Provides access to Check Syntax, synthesis, View RTL Schematic, and
synthesis reports. This varies depending on the synthesis tools you use.
Implement Design
Provides access to implementation tools, design flow reports, and point
tools.
Generate Programming File
Provides access to the configuration tools and bit stream generation. The
Processes for Current Source window incorporates auto make technology. This
enables the user to select any process in the flow and the software automatically
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runs the processes necessary to get to the desired step. For example, when you run
the Implementation process, Project Navigator also runs the synthesis process
because implementation is dependent on up-to-date synthesis results.
Note: To view a running log of command line arguments in the Console window,
expand Design Entry Utilities and select View Command Line Log File.
Console Window
The Console window displays errors, warnings, and informational
messages. Errors are signified by a red box next to the message, while warnings
have a yellow box. Warning and Error messages may also be viewed separately
from other console text messages by selecting either the Warnings or Errors tab at
the bottom of the console window.
Error Navigation to Source
You can navigate from a synthesis error or warning message in the Console
window to the location of the error in a source HDL file. To do so, select the error
or warning message, right-click the mouse, and from the menu select Go to
Source. The HDL source file opens and the cursor moves to the line with the error.
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Error Navigation to Solution Record
You can navigate from an error or warning message in the Console
window to the relevant solution records on the support.xilinx.com website. These
type of errors or warnings can be identified by the web icon to the left of the error.
To navigate to the solution record, select the error or warning message, right-click
the mouse, and from the menu select go to Solution Record. The default web
browser opens and displays all solution records applicable to this message.
Synthesizing the Design
So far you have used XST for verifying syntax. Next, you will synthesize
the design. The synthesis tool uses the design’s HDL code and generates a
supported netlist type (EDIF or NGC for the Xilinx® implementation tools). The
synthesis tools perform three general steps (although all synthesis tools further
breakdown these general steps) to create the netlist:
Analyze / Check Syntax
Checks the syntax of the source code.
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Compile
Translates and optimizes the HDL code into a set of components that the
synthesis tool can recognize.
Map
Translates the components from the compile stage into the target technology’s
The RTL Viewer
XST can generate a schematic representation of the HDL code that you
have entered. A schematic view of the code is helpful for analyzing your design to
see a graphical connection between the various components that XST has inferred.
To view a schematic representation of your RTL code:
1. In Project Navigator, click + next to Synthesize to expand the process
hierarchy.
2. Double-click View RTL Schematic.
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FIGGGGGGGG
Entering Synthesis Options through ISE
Synthesis options enable you to modify the behavior of the synthesis tool
to optimize according to the needs of the design. One option is to control synthesis
by optimizing based on area or speed. Other options include controlling the
maximum fan out of a signal from a flip-flop or setting the desired frequency of
the design.
For this tutorial, set the global synthesis options:
1. Select stopwatch.vhd (or stopwatch.v).
2. Right-click the Synthesis process.
3. From the menu, select Properties.
4. Click the Synthesis Options tab, and set the Default Frequency to 50MHz.
5. Click the Netlist Options tab, and ensure that the Do Not Write NCF box is
unchecked.
6. Click the Constraint File Options tab, and select the stopwatch.ctr file
created in LeonardoSpectrum, in the “Modifying Constraints” section
above.
7. Click OK to accept these values.
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8. Select stopwatch.vhd (or stopwatch.v) and double-click the Synthesize
process in theProcesses for Source window
The RTL/Technology Viewer
LeonardoSpectrum can generate a schematic representation of the HDL
code that you have entered. A schematic view of the code is helpful for analyzing
your design to see a graphical connection between the various components that
LeonardoSpectrum has inferred.
To launch the design in LeonardoSpectrum’s RTL viewer, double-click the
View RTL Schematic process. The following figure displays the design in an RTL
view. LeonardoSpectrum Synthesis Processes
Overview of Behavioral Simulation Flow
Behavioral simulation is done before the design is synthesized to verify
that the logic you have created is correct. This allows a designer to find and fix
any bugs in the design before spending time with Synthesis or Implementation.
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Xilinx® ISE provides an integrated flow with the ModelTech ModelSim simulator
that allows simulations to be run from the Xilinx Project Navigator graphical user
interface (GUI). The examples in this tutorial show how to use this integrated
flow. For additional information about simulation and for a list of the other
supported simulators, refer to Chapter 6 of Synthesis and Verification Guide. This
Guide is available with the collection of software manual and is accessible from
ISE by selecting Help___Online Documentation,or from the web at
http://support.xilinx.com/support/sw_manuals/xilinx6/.
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CHAPTER 9
SOURCE CODE AND SIMULATION RESULTS
9.1 Source code:
library ieee;
use ieee.std_logic_1164.all;
entity tlc is
port(clk,sa,sb:in std_logic;
ra,rb,ga,gb,ya,yb:buffer std_logic);
end tlc;
architecture beh of tlc is
signal state, nextstate : integer range 0 to 12;
type light is(r,y,g);
signal lighta,lightb:light;
begin
process(state,sa,sb)
begin
ra<='0';rb<='0';ga<='0';gb<='0';
ya<='0';yb<='0';
case state is
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when 0 to 4 => ga<='1';rb<='1';
nextstate<=state+1;
when 5=>ga<='1';rb<='1';
if sb='1' then nextstate<=6;
end if;
when 6=>ya<='1';rb<='1';
nextstate<=7;
when 7 to 10=>ra<='1';gb<='1';
nextstate<=state+1;
when 11=>ra<='1';gb<='1';
if(sa='1' or sb='0')then nextstate<=12;
end if;
when 12=> ra<='1';yb<='1';
nextstate<=0;
end case;
end process;
process(clk)
begin
if clk='1' then
state<=nextstate;
end if;
end process;
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lighta<=r when ra='1' else y when ya='1'else g when ga='1';
lightb<=r when rb='1' else y when yb='1'else g when gb='1';
end beh;
9.2 Simulation Result:
simulation output waveform for traffic light controller
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CHAPTER 10
SYNTHESIS REPORT
Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to D:/New Folder (2)/traffic/traffic/xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.33 secs
--> Parameter xsthdpdir set to D:/New Folder (2)/traffic/traffic/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.33 secs
--> Reading design: tlc.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
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3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
==========================================================
===============
* Synthesis Options Summary *
==========================================================
===============
---- Source Parameters
Input File Name : "tlc.prj"
Input Format : mixed
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Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "tlc"
Output Format : NGC
Target Device : xc3s500e-4-fg320
---- Source Options
Top Module Name : tlc
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
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ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
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Optimization Effort : 1
Library Search Order : tlc.lso
Keep Hierarchy : NO
Netlist Hierarchy : as_optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
==========================================================
===============
* HDL Compilation *
==========================================================
===============
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WARNING:HDLParsers:3607 - Unit work/tlc is now defined in a different file.
It was defined in "D:/vhdl/traffic/aaaaaaa.vhd", and is now defined in "D:/New
Folder (2)/traffic/traffic/aaaaaaa.vhd".
WARNING:HDLParsers:3607 - Unit work/tlc/beh is now defined in a different
file. It was defined in "D:/vhdl/traffic/aaaaaaa.vhd", and is now defined in
"D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd".
Compiling vhdl file "D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd" in Library
work.
Architecture beh of Entity tlc is up to date.
==========================================================
===============
* Design Hierarchy Analysis *
==========================================================
===============
Analyzing hierarchy for entity <tlc> in library <work> (architecture <beh>).
==========================================================
* HDL Analysis *
==========================================================
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Analyzing Entity <tlc> in library <work> (Architecture <beh>).
INFO:Xst:1739 - HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
INFO:Xst:1739 - HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
INFO:Xst:1739 -HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
INFO:Xst:1739 - HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
INFO:Xst:1739 - HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
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INFO:Xst:1739 -HDL ADVISOR - "D:/New Folder
(2)/traffic/traffic/aaaaaaa.vhd" line 5: declaration of a buffer port will make it
difficult for you to validate this design by simulation. It is preferable to declare it
as output.
WARNING:Xst:819 - "D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd" line 33:
One or more signals are missing in the process sensitivity list. To enable synthesis
of FPGA/CPLD hardware, XST will assume that all necessary signals are present
in the sensitivity list. Please note that the result of the synthesis may differ from
the initial design specification. The missing signals are:
<nextstate>
Entity <tlc> analyzed. Unit <tlc> generated.
==========================================================
===============
* HDL Synthesis *
==========================================================
===============
Performing bidirectional port resolution...
Synthesizing Unit <tlc>.
Related source file is "D:/New Folder (2)/traffic/traffic/aaaaaaa.vhd".
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WARNING:Xst:646 - Signal <lightb> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <lighta> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 4-bit latch for signal <state>. Latches may be
generated from incomplete case or if statements. We do not recommend the use of
latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <nextstate>. Latches may be
generated from incomplete case or if statements. We do not recommend the use of
latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data
and gate enable inputs of this latch share common terms. This situation will
potentially lead to setup/hold violations and, as a result, to simulation problems.
This situation may come from an incomplete case statement (all selector values
are not covered). You should carefully review if it was in your intentions to
describe such a latch.
Found 4-bit adder for signal <nextstate$addsub0000>.
Found 4-bit 13-to-1 multiplexer for signal <nextstate$mux0000>.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 4 Multiplexer(s).
Unit <tlc> synthesized.
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INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some
arithmetic operations in this design can share the same physical resources for
reduced device utilization. For improved clock frequency you may try to disable
resource sharing.
==========================================================
===============
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
4-bit adder : 1
# Latches : 2
4-bit latch : 2
# Multiplexers : 1
4-bit 13-to-1 multiplexer : 1
==========================================================
===============
* Advanced HDL Synthesis *
==========================================================
===============
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Loading device for application Rf_Device from file '3s500e.nph' in environment
C:\Xilinx\10.1\ISE.
==========================================================
===============
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
4-bit adder : 1
# Latches : 2
4-bit latch : 2
# Multiplexers : 1
4-bit 13-to-1 multiplexer : 1
==========================================================
===============
* Low Level Synthesis *
==========================================================
===============
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Optimizing unit <tlc> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block tlc, actual ratio is 0.
Final Macro Processing ...
==========================================================
===============
Final Register Report
Found no macro
==========================================================
===============
==========================================================
===============
* Partition Report *
==========================================================
===============
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Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
==========================================================
===============
* Final Report *
==========================================================
===============
Final Results
RTL Top Level Output File Name : tlc.ngr
Top Level Output File Name : tlc
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 9
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Cell Usage :
# BELS : 12
# LUT3 : 2
# LUT4 : 10
# FlipFlops/Latches : 8
# LD : 8
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 8
# IBUF : 2
# OBUF : 6
==========================================================
===============
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-4
Number of Slices: 7 out of 4656 0%
Number of Slice Flip Flops: 8 out of 9312 0%
Number of 4 input LUTs: 12 out of 9312 0%
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Number of IOs: 9
Number of bonded IOBs: 9 out of 232 3%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
==========================================================
===============
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE
TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
------------------
--------------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
--------------------------------------+------------------------+-------+
nextstate_not0001(nextstate_not0001:O)| NONE(*)(nextstate_0) | 4 |
clk | BUFGP | 4 |
--------------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically
buffered by XST with BUFG/BUFR resources. Please use the buffer_type
constraint in order to insert these buffers to the clock signals to help prevent skew
problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
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Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 6.207ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
==========================================================
===============
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 23 / 6
-------------------------------------------------------------------------
Offset: 6.207ns (Levels of Logic = 2)
Source: state_2 (LATCH)
Destination: gb (PAD)
Source Clock: clk falling
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Data Path: state_2 to gb
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 11 0.676 1.108 state_2 (state_2)
LUT4:I0->O 2 0.704 0.447 gb1 (gb_OBUF)
OBUF:I->O 3.272 gb_OBUF (gb)
----------------------------------------
Total 6.207ns (4.652ns logic, 1.555ns route)
(74.9% logic, 25.1% route)
==========================================================
===============
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 4.41 secs
-->
Total memory usage is 158008 kilobytes
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Number of errors : 0 ( 0 filtered)
Number of warnings : 7 ( 0 filtered)
Number of infos : 9 ( 0 filtered)
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CHAPTER 11
RTL Schematics:
RTL Schematics:
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CHAPTER 12
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CONCLUSION
The Project mainly deals with the chip level modeling, taking
designing of AES . During the course of the project we have realized and
experienced the definite advantages that a hardware description language
offers over the conventional method of designing.
VHDL coupled with simulation tools provides the designers with
option of modeling in parts and the advantages of checking the
correctness of the design as it evolves. There is a great scope for
development in the project .we are successful in bringing the AES in
our design implementation using VHDL.In our project, we also learned
about the AES that are in market today. Thus there is scope for both
quantitative, qualitative and total security improvement of this pro
\
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BIBLOGRAPHY
BOOKS:
1.BHASKAR.J “ VHDL PRIMER “
2.DOUGLAS L.PERRY “ VHDL “
3.STEPHEN BROWN AND “FUNDEMENTAS OF DIGITAL LOGIC
ZVONKO VRANESIC WITH VHDL DESIGN”
4.DOUGLAS V.HALL “MICROPROCESSORS AND INTERFACING”
WEB SITES:
http://support.xilinx.com/support/sw_manuals/xilinx6/.
www.xilinx.com/itp/xilinx10/books/docs/qst/qst.pdf
www.xess.com/appnotes/ise-10.pdf
www.digilentinc.com/.../Tutorials/.
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