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AN147 – An Overview of the PowerQUICC® III MPC8572
July, 2009
Toby FosterProduct Marketing
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Agenda
• Positioning• Target markets and key advantages• Block diagram
Per block details• Usage Models
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AgendaMoore’s Law Breakdown
1.00
10.00
100.00
1000.00
10000.00
1996 1998 2000 2002 2004 2006 2008 2010 2012 2014
Rel
ativ
e Pe
rfor
man
ce
Historical+IPC+PipeliningTechnology
40x
6.6x
10x
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Core0 Core1
Core0 Core1Core0 Core1
Multiprocessing Use Case
network
SMP
network
Offloading
network
Partitioning
network
Standby
• Scaled control plane• SW transparent• OS manages entire chip
• Typically AMP• Control + data plane• Legacy OS + services on
Linux• Combining two processors
• CPU intensive activity on one core
• Security• Deep packet inspection
• Redundancy• Quick in-field SW upgrade• Future in-field performance
upgradeCore0 Core1
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Many Choices
Number of Cores
Perfo
rman
ce o
f Cor
es
H/E Data
H/E Mixed
Control/Data
H/E Control
L/E Mixed
Control/Data
►Multicore application differentiators• Frequency• IPC• Number of cores
Threading• Cache size and structure• HW Acceleration
►Other differentiators• Power• I/O• Price • Package size• ISA
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What Application for What Multicore?
Control Plane
Mixed
Data Plane
2 4 6 8 10 12 14 16
1 - 2
2 - 4
4+
Number of Cores
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What Application for What Multicore?
Control Plane
Mixed
Data Plane
2 4 6 8 10 12 14 16
1 - 2
2 - 4
4+
Number of Cores
Code Footprint
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What Application for What Multicore?
Control Plane
Mixed
Data Plane
2 4 6 8 10 12 14 16
1 - 2
2 - 4
4+
Number of Cores
Code Footprint
Potential for acceleration
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More Cores = More Better?
L2►Watch out for cache thrashing►Small L2 per core►High miss ratios
Bus Bandwidth►Can bus feed all cores?►Small L2 exacerbates problem►Increases latency
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Multicore
SingleCore
SingleCore
10
PowerQUICC® Migration to QorIQ™ PlatformsPe
rfor
man
ce
1st Parallel RapidIO1st DDR memory
1st Security engine1st 1GHz Core
1st Dual CoresRapidIO and PCI ExpressBackside Cache, e600
1st 1.5GHz core1st DDR1 / 21st sRapidIO,PCI Express
Lower Power, 3 PCI-e Ctlrs1st SGMII
Dual Core e500 1.5GHzPME, TLU, Security1st DDR 2/3
MPC8641D P2020
MPC8540MPC8541
MPC8544MPC8548
Platform
P30xx
P1011
P2010
P1020
45 nm Lower PowerDual and Single CorePin-compatible Family
e500mc, 1.5 GHzCoreNettm
Tri-level Cache10 GbE, PCI-e 2.0
P50xx
P30xx
P30xx
MPC8347MPC8377
MPC831x Low power Efficient performance
P4080
MPC8572
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Mapping Freescale Products to Applications
Number of Cores
Perfo
rman
ce o
f Cor
es
P4080MPC8641DMPC8572
P2020P1020
Dual core performance in single e300 power/price budgetsDual core performance in single e500 power/price budgetsWell-rounded high performance with security acceleration
Highest performance for compute-intensive apps
High performance multi-core simplified
Cores
Frequency
Cache
SerDes
GE BW
Mem BW
P1020 P2020 8572 8641D P4080
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Target Applications
• Networking (switches and routers) High-end line card control plane Mid-range line card combined control and data plane Services/options cards Per-chassis controller
• Telecom AdvancedMC™ card AdvancedTCA® carrier processor card Control and modem for LTE, WiMAX General-purpose compute blade
• Industrial Storage Robotics Test/measurement Multifunction printer Single board computers Industrial applications
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PowerQUICC® III MPC8572 Key Advantages
►High single-threaded performance • Efficient core: 2-instruction, 2.4 DMIPs/MHz• High frequency: up to 1.5 GHz
►Enables performance without complexity of partitioning across multiple cores or threads
►Highly suitable for control plane applications whose sequential nature means efficiency is lost with scaling to many cores
►Pattern matching and classification acceleration►In production, highly enabled
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MPC8572/E: Content to the Masses• Dual e500 cores, built on Power Architecture®
technology (to 1.5 GHz)• 36-bit addressing• 1 MB shared L2 cache/SRAM with ECC
• With stashing• Dual memory controller
• Dual DDR2/3 SDRAM up to 800 MHz• 32-/64-bit data bus with ECC• Support for up to 32 GB memory
• High-speed interconnect• One x8/x4/x2/x1 PCI Express® (PCIe)
Or Two x4/x2/x1 PCIeOr One x4/x2/x1 PCIe AND Two x2/x1 PCIe Or One x4/x2/x1 PCIe AND x4/x1 sRapidIO
• Ethernet• 4x 10/100/1000 Ethernet controllers with classification/policing, 8
Rx/Tx queues, checksum offload, QoS, lossless flow control, IEEE® 1588, 4 SGMII
• 1x 10/100 FEC with MII (muxed)• Security engine (SEC 3.0)
• ARC4, 3DES, AES, AES-GCM, SHA-384/512, RSA/ECC, RNG and XOR
• Single pass SSL• Pattern matching (Reg-Ex) and deflate
• 16k patterns up to 128, breaking across packets• Table lookup unit (TLU)
• Up to 7M lookups/sec• 90 nm SOI process, 1023 pin package• Frequency, voltage, power (typical)
VDD Core Freq Plat Freq Power 1.1V 1500 600 17.3W1.1V 1333 533 16.3W1.1V 1200 480 15.6W1.1V 1067 533 12.3W
Production
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e500v2 Core Architecture
Instruction UnitCompletion
UnitInstruction Queue (12)
Branch Processing
Unit
GPR Issue (2)
DispatchUnit
CFX SFX2 LSU
GPRs
RenameBuffers
Core Complex Bus36-bit Address Bus
128-bit Rd/Wr Data Bus
Sequencer Fetcher 32KB
InstructionCacheTa
gsTa
gs 32KBData
CacheL1 Data MMU
DTLBs
L1 Instruction MMUI-TLBs
Memory Unit
SFX1
L2 Unified MMUs
MAS
Book E APUs:Performance
Monitor,SPE, DPFPIsel, BTB,
Cache Line Locking,MachineCheck
• Up to 1.5 GHz• L1: 32KB, 8-way set
associative, Parity• L2: Front Side: 8-way
set associative, ECC• Cache line locking
supported• MESI cache
coherence• Peak IPC 2
Instructions plus 1 branch
• Out of Order Execution
• Multiple Book E APUs• 16 TLB SuperPages• 512-entry 4K Pages• 36-bit Physical
Address
Shared1 MB Unified
Frontside L2 Cache
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e500 Core 1
32KB D-cachew/Parity
32KB I-cachew/Parity
Core Complex Bus
e500v2 Core
RD1 RD2 WR
L2 Cache Controller
► Shared 1MB unified frontside L2 cache w/8-way associativity (Each way: 128KB)
► Assignment Granularity:• One, two, four, or all eight “ways” of the cache
can be assigned as the following:• SRAM• Stash-Only• CPU0 L2 Only• CPU1 L2 Only• Both CPU0 & CPU1 L2
► Stash-Only regions can now be defined• Prevents stash data from polluting processor
data and vice-versa• One, two or four “ways” of the cache can be
dedicated as stash-only► Stash Allocate Disable mode added
• Allows update of all resident cache lines without allocation of new lines
Core Complex Bus
CoherencyModule
e500v2 Core
64
128
128
RD1 RD2 WRRD_IN DOUT WR_IN
Stash Only
CPU0 & 1 L2CPU1 L2
Example
32 KB D-cachew/Parity
32 KB I-cachew/Parity
e500v2 Core
e500 Core 0
Core Complex Bus
1MB
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10/100/1000MAC
8-bit FIFOInterface
TCP/IPOffload
Quality ofServiceRx
FIFO2 KB
TxFIFO10 KB
64-bit DMAGig-E Controller 1
10/100/1000MAC
8-bit FIFOInterface
TCP/IPOffload
Quality ofServiceRx
FIFO2 KB
TxFIFO10 KB
64-bit DMAGig-E Controller 2
10/100/1000MAC
8-bit FIFOInterface
TCP/IPOffload
Quality ofServiceRx
FIFO2 KB
TxFIFO10 KB
64-bit DMAGig-E Controller 3
Enhanced Triple Speed Ethernet Controller
Optimizes CPU performance on TCP/IP• TCP/IP checksum offload Rx + Tx• IPv6 support in H/W
QoS support for 16 H/W queues (8 Rx + 8 Tx)• Customizable per-packet filing/filtering• 802.1p, IP TOS, Diffserv classification• Support for weighted fair queueing• TCP/UDP port-based flows• Assist firewall through IP/TCP/UDP reject• Ethernet preamble sorting and insertion
FIFO I/F to ASICs + (R)GMII/(R)MII/(R)TBI• 8-/16-bits @ OC-48 rates (155 MHz)
Layer 2 features• VLAN insertion and deletion per frame• 16 exact-match MAC addresses• Lossless Flow Control
Code compatible with PowerQUICC® III e/TSEC controllers
10/100/1000MAC
8-bit FIFOInterface
TCP/IPOffload
Quality ofServiceRx
FIFO2 KB
TxFIFO10 KB
64-bit DMAGig-E Controller 4
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IEEE® 1588 Summary► IEEE 1588 – Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems• The standard defines a Precision Time Protocol (PTP) designed to synchronize real-time clocks in a
distributed system• Intended for local area networks using multicast communications (including Ethernet)• IEEE 1588 was designed to work within a building or factory
Intended typically for industrial automation and test and measurement systems (e.g. synchronized printing presses)• Targeted accuracy of microsecond to sub-microsecond• Version 1 approved September 2002 and published November 2002• Version 2 approved March 2008 and published August 2008• Available from the IEEE 1588 web site (http://ieee1588.nist.gov)
Node A:Time = 9:04
Node B:Time = 9:29
Node C:Time = 9:28
Node A:Time = 9:04
Node B:Time = 9:04
Node C:Time = 9:04
NETWORK NETWORK
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Freescale Security Engine – SEC 3.0
CryptoChannel
CryptoChannel
CryptoChannel
CryptoChannel
On-ChipSystem
InterfaceControl
FIFO
PKEU DEUAESUXOR AFEUMDEU RNG
FIFO FIFO FIFO
CRC
FIFO
KEU
FIFO
FIFO FIFO FIFO FIFOFIFO
► Public Key Execution Unit supports:• RSA and Diffie-Hellman (to 4096b)• Elliptic curve cryptography (1023b)
► DES Execution Unit• DES, 3DES (2K, 3K)• ECB, CBC, OFB-64 modes
► AES Execution Unit• Key lengths of 128, 192, and 256-bits• ECB, CBC, CTR, CCM, GCM, CMAC, OFB-128,
CFB-128, and LRW► Message Digest Execution Unit
• SHA-1 160-bit digest• SHA-2 256-bit digest• SHA-384/512• MD5 128-bit digest• HMAC with all algorithms
► ARC Four Execution Unit• Compatible with RC4 algorithm
► Kasumi Execution Unit (KEU)• F8, F9 as required for 3GPP• A5/3 for GSM and EDGE• GEA-3 for GPRS
► CRC Execution Unit• CRC32, CRC32C
► XOR acceleration► Random Number Generator
Back
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Pattern Matching/Deflate Engines
► Regex support plus significant extensions:
• 16K patterns of up to 128B length• Patterns can be split into 256 sets each of
which can contain 16 subsets• 2.4 Gbps raw performance
► Combined hash/NFA technology• No “explosion” in number of patterns due
to wildcards• Low system memory utilization• Fast pattern database compiles and
incremental updates► Matching across “work units” finds
patterns in streamed data
Deflate Engine► Supports decompression of dominant
(DEFLATE) compression format including zlib and gzip
► Optimized decompression of Layer 7 PDUs (attachments, web objects) required for antivirus and anti-SPAM scanning
The Pattern Matching Engine and Deflate Engine dramatically
offloads the CPU cores Back
On-ChipSystem
Interface
DMAEngine
Memory HashTables
Key ElementScanning
Engine(KES)
DeflateEngine
Decompress
Data Examination
Engine(DXE)
StatefulRule
Engine(SRE)
Results
Access to Patterm Descriptors and StateTM
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Table Lookup Units (Two TLU’s on the MPC8572E)
► A special purpose hardware block designed to off-load table searches from the PowerQUICC® III e500 core
► A compatible superset of the Freescale C-5e TLU specification
► Incorporates some TLU improvements targeted for C-10
► Supports a similar variety of table numbers, types, and entry sizes
• Up to 32 tables • Up to 16M entries per table• Up to 64B per entry
► Longest prefix match, exact match, chained hash, and flat data table formats
► Supports 32, 48, 96, and 128-bit keys
DDR
64-bitrequest/result
bus
PipelineIndexGeneration
MemoryInterface
TLURegisters
AddressGeneration
CommandParser
InitialIndex
Generation
HashFunction
SystemInterface Local
Bus
Back
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PCI Express® Interface
► Three PCI Express (PCIe) controllers► PCI Express 1.0a compatible► Supports x1, x2, and x4 link widths @ 2.5 Gbaud, 2.0Gb/s
• Auto-detection of number of connected lanes► Selectable as root complex or endpoint at initialization► 32 and 64-bit addressing into PCI Express address space► Root complex inbound support for MSI and INTx► Endpoint support for outbound MSI ► Reads/writes carried across ports, but not a switch► 256 byte maximum payload size► One virtual channel► Strong and relaxed ordering rules► 8 non-posted, 6 posted transactions► 3 inbound + 1 configuration window
• Translates upper 52b of PCI addr to upper 24b of local addr• Window sizes of 4 KB to 64 GB• Settings: read/write type, prefetchable, and target• 1 MB Config window maps to CCSR region
► 4 outbound + 1 default window• Translates upper 24b of local addr to upper 52b of PCI addr• Select I/O or memory for reads and writes• Window sizes of 4kB to 64GB
Switch
Peripheral Endpoint
Peripheral Endpoint
Peripheral Endpoint
e500
Root Complex/ Endpoint
e500
ATMUs
Root Complex/ Endpoint
Root Complex/ Endpoint
Peripheral Endpoint
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Serial RapidIO® Interconnect for Fabric Connectivity
Compliant to Serial RapidIO Interconnect Spec, Rev 1.2► In-the-box interconnect
• Chip-to-chip, board-to-board, backplane• Greater efficiency than box-to-box protocols
• Physical layer defined for backplane interconnection• ~80–100 cm + 2 connectors (serial)
• Both memory-mapped and packet-based transactions► Point-to-point packetized architecture
• Low overhead• Variable packet size• Maximum 256 byte PDU• SAR support for 4K-byte messages• Hardware error recovery
► Implementation• 1x or 4x serial, 1.25, 2.5, and 3.125 GBaud• Read/write bridged between PCI Express port
► Message Unit• Two outbound and two inbound message controllers• One outbound and one inbound doorbell controllers
ATCA 3.5
SRIO Switch
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Memory Controller
• DDR2 and DDR3 to 800 MHz• 64-bit (72 bits with ECC)
32-bit (40 bit with ECC) also• 4 chip selects• Support for up to 4 Gb devices,
x8, x16, x32 configurations• Up to 4 GB DIMMs per bank• Up to 16 GB• Supports self-refresh mode• Battery backup• Initialization bypass• Chip-select interleaving• Automatic DRAM initialization• Error injection
ECM
e500 Core
System Bus
DDR2/DDR3, SDRAM
Controller
e500 Core
DDR2/DDR3, SDRAM
Controller
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Four Channel DMA Controller (x2)
• Each controller in separate 4k memory space to facilitate making it a private resource per core
• 4 channels and all accessible by local and remote masters
• Supports direct, simple chaining, advanced chaining and stride mode
• Support for unaligned transfers• Support for transfers to and from any local
memory or I/O port • Interrupt on completed segment, link, list and
error• Selectable hardware enforce coherence
(snoop/no-snoop)• Programmable bandwidth control between
channels• Support 256B sub-block transfer for RapidIO®
and PCI Express® interfaces• Ethernet descriptor mode to transfer data using
Ethernet descriptors
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Programmable Interrupt Controller► 12 external IRQ pins► 43 internal sources (PCIe, L2, eTSEC, etc)► Multicore capability
• Per core interrupt routing• Dedicated core interrupts• Intercore communication Messages Interrupts
• Register duplication• Multicast delivery for interprocessor and timer
interrupts► Prioritization
• 16 levels• Fully nested
► Modes• Pass through and Mixed
► Eight global timers• Cascade to create 127-bit timer• Can be clocked with divided internal clock or
external RTC ► OpenPIC compliant
MPIC
Timers
IRQ
_OU
T
e500 e500IR
Q[0
:11]
RTC
MC
P1, M
CP2
S/H
RES
ET
UD
E
Routing Configuration
ECML2 DDRDMA1-2PEX1-3SRIO1-2MsgUniteTSEC1-31588 1-3I2CPerfMonDUARTSPISECeLCBGPIOeSDHCUSB
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Runtime Power Management
►Dynamic power management• Withholds clocks to e500’s unused execution units, MMUs, caches and other
blocks without performance impact►Programmable power mode
• Programmable transition (per core) between e500 modes: full power, doze, nap and sleep
• Three external pins track power mode of cores• POWMGTCR puts device into sleep or doze
►Memory Controller• Dynamic power management
Doesn’t clock DRAM when no transactions• Sleep/doze mode
DRAM put into self-refresh mode, controller goes into sleep mode► I/O power management
• eTSEC’s Magic Packet support: specially defined Ethernet packet received on eTSEC wakes chip from sleep
• PCI Express® power states: D0 – D3, L0 – L3
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e500 Clock Control Architecture and Low Power States
Run
Processor Clocks
Snoops Responded To?
Interrupts Responded To?
Comments
On Yes Yes Dynamic Power Management (DPM) may be enabled
On Yes Yes Core stops dispatching new instructions
Off except time base
No Yes Flush data cache before entering
Off No Yes I/O clocks also turned off except interrupt controller
Doze
Nap
Sleep
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Configuration Power Management
►Multiplier flexibility to optimize core, internal bus, and DDR performance and power
►Disable unused blocks through DEVDISR register• e500 (each individually)• PCI Express® (all three individually)• Serial RapidIO® (both together)• Local bus• Security block• DMAs (both individually)• eTSECs (each individually)• DDR controller• I2C (both together)• DUART• Timers (both sets individually)
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Multiprocessing Configurations
► Symmetric Multiprocessing• Homogenous OS support• High-performance option• Software transparency• Cores share address space for OS and data• Resource sharing handled by OS• Dynamic load balancing by OS
► Asymmetric Multiprocessing• Heterogeneous OS support• Two separate OS or two copies of one non-
SMP OS• Collapse two processors into one• Task offload or division of labor• Operating systems, data reside in different
address spaces• Resource sharing handled by user• Static load balancing
► Cooperative AMP• Application-level awareness between cores
Core 0 Core 1OS,
shared user data
Private data
Private data
Core 0 Core 1
shar
ed
user
dat
a
OS, Private
data
OS, Private
data
Memory Map Overlap
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e500 core1
SMP Memory Organization
►The OS kernel resides at physical memory address 0, addressable by both cores
►The MMU relocates applications and shared memory appropriately
e500 core0Apps "A"
Apps "B"
OS
Apps "A"
Apps "B"
Sharedmemory
Physicalmemory
OS
Sharedmemory
OS
Sharedmemory
OS
MM
UM
MUApps "A"
Apps "B"
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Asymmetric MP Memory Organization
• Each OS kernel expects to control physical memory beginning at address 0
• Each wants its own interrupt vectors
• The MMU can relocate applications and shared memory appropriately
core1
core0Apps, OS "A"
Apps, OS "B"
Apps "A"
Apps "B"
Sharedmemory
Apps "A"Sharedmemory
Apps "B"Sharedmemory
OS "A"
OS "B"
OS "A"
OS "B"
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Resource Allocation►SMP
• Both Cores can see all peripherals. Imaginary separation can be made by OS/Software.
►AMP/CAMP• Each resources are dedicated to designated
core. Statically assigned.eTSEC DDRC DMA
SRIO
eTSEC
eTSECeTSEC PCIe
DDRC
eT1 eT2 eT3 eT4
MPIC
eT1-4
eT1 eT2 eT3 eT4
MPIC
eT1&2 eT3&4PCIePCIe
DMA
?
Core0 Core1Core0 Core1
Core0 Core1
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UART 1
DDR 2
Resources: Shared or Multiple Instances
core1core0 DDR 1MPICLocal Bus SRIO
Shared Resource
Multiple resource instances
PCI-Ex 3 DMA1UART 0
I2C 2
Partially shared or multiple instances in some circumstances
FEC PME
DMA0 I2C 1 TLU1TLU0eTSEC4PCI-Ex 2
PCI-Ex 1eTSEC3eTSEC2
eTSEC1
SEC
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Not Shared: PEX, eTSEC, DUART, I2C, TLU, DMA
• Multiple instances present• Interrupt can be targeted to core• Dataflow can be contained to
core’s memory space
PIC
core1core0
Memory
Interrupt Flow
Data Flow
eTSEC2eTSEC1
PCI-Ex 3
PCI-Ex 2eTSEC4
eTSEC3
I2C 2IC2 1
UART 1UART 0
PCI-Ex 1
TLU 1TLU 0
DMA 1DMA 0
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The Ideal Control Plane Processor► High single-threaded performance
Efficient core: 2-instruction, 2.4 DMIPs/MHz High frequency: up to 1.5 GHz
► Enables performance without complexity of partitioning across multiple cores or threads► Highly suitable for control plane applications whose sequential nature means efficiency is lost with scaling to many cores► Pattern matching and classification acceleration► In production, highly enabled
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TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 37
Freescale Introduces Product Longevity Program
►The embedded market needs long-term product support, which allows OEMs to provide assurance to their customers.
►Freescale has a longstanding track record of providing long-term production support for our products.
►Freescale is pleased to introduce a formal product longevity program for the market segments we serve.
• For the automotive and medical segments, Freescale will manufacture select devices for a minimum period of 15 years.
• For all other market segments in which Freescale participates, Freescale will manufacture select devices for a minimum period of 10 years.
►A list of applicable Freescale products is available at www.freescale.com.
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 38
Q&A
►Thank you for attending this presentation. We’ll now take a few moments for the audience’s questions and then we’ll begin the question and answer session.
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