fully parallel learning neural network chip for real-time control
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7/6/99 MITE 1
Fully Parallel Learning Neural Network Chip for Real-time Control
Students: (Dr. Jin Liu), Borte Terlemez
Advisor: Dr. Martin Brooke
7/6/99 MITE 2
Combustion Instability Control -Simulation Results Review
• Simulated Neural Net and Combustion
• One-frequency Results
• Multi-frequency Results
• Parameter Variation Results
• Added Noise Results
7/6/99 MITE 3
Simulation SetupD
elay
1.5
ms
Del
ay li
ne
error error
UnstableCombustion Model
xu
Software Simulation of Neural Network Chip
uxxb
bxx
2
2 )(2
7/6/99 MITE 5
One Frequency Result
Time (second)
Eng
ine
Pre
ssur
eN
N W
eigh
t
1 4 2 3 4 2 1 3 2 3 4 3 5 1 5 4
f = 400Hzb =
7/6/99 MITE 8
10 % Added Noise Results
Uncontrolled Engine
Neural Network Controlled Engine
f=400Hz=0.005b=1
7/6/99 MITE 9
Neural Network Chip Control of Combustion Instability
Del
ay 1
.5m
s
Del
ay li
ne
2.5
ms
8 ta
ps
error
400Hz
xx2/b -1)x+2x=u ...
xu
7/6/99 MITE 10
Experimental Setup
Chip ControlSignals
5
Digital Output
1
Analog Input
Chip Output
Chip Input
Analog Output
8
National InstrumentAT-MIO-16E
National InstrumentAT-AO-10
Current to Voltage Conversion
7/6/99 MITE 16
Details of the Continuously Adjusting Process
Error Increases
Error Decreases
f = 400Hz = 0.0b = 0.1
7/6/99 MITE 20
Summary of NN Chip Control of Simulated Combustion Instability
• The NN chip can successfully suppress the combustion instabilities within around 1 sec.
• The NN chip continuously adjusts on-line to limit the engine output to be within a small magnitude.– I/O card delay and engine simulation delay
• 30 times longer than real time
• Weight leakage
– Fixed learning step size
7/6/99 MITE 21
Improved Neural Network Chip in 0.35- m Process
• Seven Time More Neuron Cells• Two layers
• Each layer has 30 inputs instead of 10
• Totally 720 neurons instead of 100
• Adaptive Learning Step Size• Capacitor charge sharing scheme
• Current charging and discharging scheme
• Partitioned Error Feedback
• Synchronized Learning, without stopping the clocks
7/6/99 MITE 23
Chip Architecture - Block Diagram
AB
A I
nput
s (3
0)
A Outputs (20)
B I
nput
s (3
0)
B Outputs (4) Biases, Clocks and Control Signals (18)
7/6/99 MITE 25
Full Chip Spice Simulation after Parasitic Extraction
• Shift Register
• Weight Updating
• Current Outputs at Pads
• Clocking Scheme
7/6/99 MITE 26
Shift Register
X=1msFirst 0 to 1at sh_in
X=1.48msFirst 0 to 1at sh_out_1r24 cycles of delay
X=15.4msFirst 0 to 1at sh_out_end720 cycles of delay
7/6/99 MITE 29
Clocking Scheme for Learning
Sh_in data
1
2
_learn
_randomfor three sub-nets
One clocking cycle is 20 s
7/6/99 MITE 30
Conclusion
• Extensive software simulations to provide a solution for real-time control using the RWC algorithm, with direct feedback scheme
• Successful application of the analog neural network chip to control simulated dynamic, nonlinear system
• Improved chip resulted from the extensive hardware experiments
• Automated test method and system
7/6/99 MITE 31
Future Works
• Acoustic Oscillation Suppression
• Test of the New Chip
• Real Combustion System Control• Third Generation Chip (~10,000 Weights)
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