fundamentals of power integrity with current design ...ihsan erdin, ram achar, "pin-capacitor...
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Nov 2018 1
Fundamentals of Power
Integrity with Current
Design & Analysis Practices
Ihsan Erdin
Nov 2018 2
Power path
Signal path
Return path
TX RXVRM
Nov 2018 3
Power delivery network
Nov 2018 4
Power Noise on 3.3V Supply
Nov 2018 5
Logic Noise Margins
high
low
Nov 2018
Voltage (
mV
)
0.0 50.0 100.0 150.0 200.0 250.0
500.0
Time (ps)
-500.0
250.0
-250.0
0.0
Receiver Eye Diagram
Nov 2018 7
Analysis Parameters
)s(I)s(Z)s(V loadpowernoise
Nov 2018 8
Zpower
Pin
PDN Characterization
Z11
Z21
Z12
Z22
Zpower
Pin
Pin
Nov 2018 9
Planar Circuit Analysis
Nov 2018 10
Target Impedance Mask
Zpower
)s(I
)s(VZ
load
noiseetargt
Nov 2018 11
Vendor Provided Impedance Mask
Zpower
Nov 2018 12
Pin Groups and Representative Port
Nov 2018
Practical Example
Nov 2018
106
107
108
109
10-3
10-2
10-1
100
Frequency (Hz)
|Zin| (
)
16 Optimized 1F Capacitors for 60 Pins
Ihsan Erdin, Ram Achar, "Multipin Optimization of Decoupling Capacitors on Practical Printed Circuit Boards," 2018 IEEE
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), Dec. 2018, Chandigarh, India
Nov 2018 15
Self-resonance of decoupling
caps
sCsLRZc
1
Nov 2018 16
Power
Spread Inductance
Ground
IC Device
r
d
Nov 2018 17
ZC
Z11-Z12
Z12
Zin
Pin
)s(Z)s(Z
)s(Z)s(Z)s(Z
C
in
22
212
11
Ihsan Erdin, Ram Achar, "Pin-Capacitor Spacing As A Design Guide To Power Delivery Networks," 2017 IEEE MTT-S
International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and
Terahertz Applications (NEMO), pp. 70-72, May 2017.
Z22-Z12
Nov 2018 18
Impedance Increases with Spacing
Ihsan Erdin and Ram Achar, "Efficient Decoupling Capacitor Placement Based on
Driving Point Impedance," IEEE Trans. Microwave Theory and Tech., vol. 66, pp.
669-677, Feb. 2018.
Nov 2018 19
Ihsan Erdin and Ram Achar, “Analysis of Decoupling Capacitors on Power
Transmission Lines," 2018 IEEE APEMC, May 2018.
Nov 2018 20
Calculate Required Total Capacitance
)s(sV
)s(IC
noise
loadtotal
Nov 2018
20-pin BGA footprint
x (mm)
y (
mm
)
Nov 2018
)r,s(Z
)r,s(Z)s(Q
ii
iii
0
A New Figure of Merit for Capacitor Placement
Nov 2018
y (
mm
)
x (mm)
Nov 2018
Nov 2018
177 power pins
Nov 2018
20 40 60 80 100 120 140 160
2
2.5
3
3.5
4
4.5
5
Pin Number
Q
nc=1
nc=5
nc=10
nc=25
nc=50
nc=75
nc=100
nc=125
Nov 2018
0 20 40 60 80 100 120
2
2.5
3
3.5
4
4.5
Number of Capacitors
Q
Nov 2018
pn
ii
p
Q̂n
Q1
1
Objective Function for Optimization
Nov 2018
Optimized placement
10 10.5 11 11.5 12 12.5 13 13.5 14
10
10.5
11
11.5
12
12.5
13
x-coordinate (mm)
y-c
oord
inate
(m
m)
10 10.5 11 11.5 12 12.5 13 13.5 149.5
10
10.5
11
11.5
12
12.5
13
x-coordinate (mm)
y-c
oord
inate
(m
m)
0 5 10 15 201
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
Pin Number
Norm
aliz
ed |Z
in| (
)
Even placement
Optimized Even
Qave 1.99 2.31
Qmax 2.61 2.62
6 capacitors
Nov 2018
Optimized placement Even placement
Optimized Even
Qave 1.75 2.11
Qmax 2.31 2.35
8 capacitors
0 5 10 15 201
1.5
2
2.5
Pin Number
Norm
aliz
ed |Z
in| (
)
10 11 12 13 149.5
10
10.5
11
11.5
12
12.5
13
x-coordinate (mm)
y-c
oord
inate
(m
m)
9 10 11 12 13 14 159.5
10
10.5
11
11.5
12
12.5
13
13.5
x-coordinate (mm)
y-c
oord
inate
(m
m)
Nov 2018
Optimized placement Even placement
Optimized Even
Qave 1.48 1.97
Qmax 2.23 2.30
12 capacitors
0 5 10 15 201
1.5
2
2.5
Pin Number
Norm
aliz
ed |Z
in| (
)
10 11 12 13 14
10
10.5
11
11.5
12
12.5
13
13.5
x-coordinate (mm)
y-c
oord
inate
(m
m)
10 10.5 11 11.5 12 12.5 13 13.5 14
10
10.5
11
11.5
12
12.5
13
x-coordinate (mm)
y-c
oord
inate
(m
m)
Nov 2018
nc = 20
nc = 12
nc = 8
nc = 6
Input Impedance of all pins
Nov 2018
Pins with Lowest Input Impedance
Nov 2018
177 power pins
Nov 2018
395 400 405 410 415
56
58
60
62
64
66
68
70
72
74
76
x-coordinate (mm)
y-c
oord
inate
(m
m)
50 Capacitors Qave
=2.20 FF: Qmean
Nov 2018
0 20 40 60 80 100 120 140 160
1
1.5
2
2.5
3
Pin Number
Norm
alized |Z
in| (
)
50 Capacitors Qave
=2.20 FF: Qmean
Nov 2018 37
•PI is an extension of SI in shared medium.
•Noise implications increase with data rates.
•Current design practices need to be revised for
high data rate applications.
•A new definition is proposed for effectiveness of
decoupling capacitors.
•Proposed algorithm considers power pins
individually, aims to minimize spread inductance.
•A new objective function is proposed for
optimized placement.
•Tested on industrial applications.
Conclusions
Nov 2018 38
Appendix
)r(H
)r(J|)rr|(H
r
dsZ
i)(
jji)(
i
ij
2
1
020
2
Model of planar structure
Nov 2018 39
Distance at which the capacitor’s effectiveness reduces
by one qth of its maximum.
q)r,s(Z
)r,s(Z
in
in 0
Nov 2018 40
)r,s(f
)r,s(frr
n
nnn
1
)r,s(Z
)r,s(Zq)r,s(Z)r,s(f
*in
min
in
22
Nov 2018 41
Nov 2018 42
mpcmpmppin Z]ZZ[ZzZ 1
ccpc
cppp
xnnxnn
xnnxnn
ZZ
ZZZ
Relations for Multi-pin and capacitor configuration
Nov 2018
10 11 12 13 14
10
10.5
11
11.5
12
12.5
13
13.5
x-coordinate (mm)
y-c
oord
inate
(m
m)
1 cm
Nov 2018
Worst-case Input Impedance with Additional Capacitors Outside BGA Pinfield
Ihsan Erdin and Ram Achar, “Multi-Pin Optimization Method for Placement of Decoupling Capacitors Using Genetic Algorithm," to
appear in IEEE Trans. Electromagnetic Compatibility, in Dec. 2018.
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