gaas mos_skp
Post on 06-Apr-2018
233 Views
Preview:
TRANSCRIPT
-
8/2/2019 GaAs MOS_SKP
1/43
GaAs based Metal-Oxide-Semiconductor
(MOS) capacitors with high-k dielectrics:
interface engineering for better performance
International Workshop on the future of nanoelectronics: research &
challenges; SKP Engineering College, Tiruvannamalai
Prof. Pallab Banerji
Semiconductor Division
MATERIALS SCIENCE CENTRE
INDIAN INSTITUTE OF TECHNOLOGY
KHARAGPUR- 721 302
INDIA
-
8/2/2019 GaAs MOS_SKP
2/43
Outline
Brief introduction
Scope of the present investigation
Work plan
Experimental part (Device fabrication and characterizations)
Results and discussion
Future plan
2
-
8/2/2019 GaAs MOS_SKP
3/43
Metal
Oxide
Semiconductor
VG
Metal : metal or poly-silicon material
Oxide : SiO2 or high- dielectric material
Semiconductor : p-type or n-type
semiconductor material
Importance of MOS Capacitors
Essential for understanding MOSFET
Basic structural part of MOSFET
CCD consists of series of MOS diode
MOS (Metal-Oxide-Semiconductor)
-
8/2/2019 GaAs MOS_SKP
4/43
Four modes of MOS operation The four modes of operation of an MOS structure:
Accumulation, Depletion, Flatband, and Inversion.
Under negative gate bias, one attracts holes from thep-typesubstrate to the surface, yielding accumulation
Surface depletion occurs when the holes in the substrate arepushed away by a positive gate voltage.
Flatband conditions exist when no charge is present in thesemiconductor so that the energy band is flat.
A more positive voltage also attracts electrons (the minoritycarriers) to the surface, which form the so-called inversion layer.
4
-
8/2/2019 GaAs MOS_SKP
5/43
accumulation
depletionInversion
Band diagram of MOS
5
-
8/2/2019 GaAs MOS_SKP
6/43
Moores Law :A 30% decrease in
the size ofintegrated circuitsevery two years.
www.intel.com/technology/silicon/itroadmap.htm
(courtesy: Intel corporation, USA) 6
-
8/2/2019 GaAs MOS_SKP
7/43
Intel Transistor Scaling and Research Roadmap
7
(courtesy: Intel corporation, USA)
-
8/2/2019 GaAs MOS_SKP
8/43
Need for high-k: Silicon dioxide
limitations
OXt
KC
0
K: permittivity; O: free space permittivity; tOX: gate dielectric
thickness ; IDsat: saturation drain current
COX K/tOX ; IDsat COX;
SiO2 limitations:
Electron direct tunnel probability is high
High leakage current limits EOT power dissipation increases
High-k dielectric is an essential requirement for fabrication of
MOS capacitors
With greater physical
thickness and high-k values,
the leakage current is
reduced and oxide
capacitance is increased
8
-
8/2/2019 GaAs MOS_SKP
9/43
Material Dielectric
constant
Band gap
(eV)
CB offset
(eV)
Breakdown
(MV/cm)
SiO2 3.9 9 3.1 14
Si3N4 6.3 5.3 2.1 6.3
Al2O3 8.5 8.8 2.8 6.2
HfO2 21 6 4 4
Ta2O5 19 4.4 1.3 3.5
ZrO2 25 5.8 2.7 3.8
TiO2 30 3.9 1.7 3.4
SrTiO3 183 3.3 1.75 1.1
PZT 300 3.2 1.34 0.87
Dielectric constant (K)
Bre
akdownfield(M
V/cm)
SiO2
Si3N4 ,Al2O3
HfO2,ZrO2
TiO2
SrTiO3
Ta2O5
9
-
8/2/2019 GaAs MOS_SKP
10/43
GaAs as channel materials!!
Advantages of GaAs:
High electron mobility (~5 times higher compared to Si).
High breakdown field.
Low power consumption.
For high-speed and high-power applications.
Feature a large drain current, much lower gate leakage current, a
better noise margin, and much greater flexibility in digital
integrated circuit design.10
-
8/2/2019 GaAs MOS_SKP
11/43
Found no stable oxide like SiO2 on Si
Poor native oxides on it (Ga-O or As-O).
Fermi level pinning at the interface between high-k andsemiconductor.
High threshold voltage and back gating and side gating effect.
High interface trap density (Dit)
Limitations of GaAs
Interface Passivation Layer (IPL) is essential in
between GaAs and high-k
11
-
8/2/2019 GaAs MOS_SKP
12/43
Oxide/Semiconductor interface Charges
QM=Mobile charges
(Na+/K+).
Qf= Fixed oxide charge.
QIT=Interface trapped
charge.
12
-
8/2/2019 GaAs MOS_SKP
13/43
IPL Thickness (nm) Capacitance Hysteresis
(V)
Dit (cm-2eV-1) Leakage current
@-1V (A/cm2)
Sulfur 10.5 (Al2O3) 0.6 F/cm2 0.43 51011 310-8
Ge 6.5 (HfO2) +
1.5 Ge
2.6 F/cm2 0.27 51011 310-4
Si 7 HfO2 + 1.5 Si 1.2 F/cm2 0.8
_
10-6
AlON 10.8 (TiO2) +
3.3 (AlON)
1 F/cm2 _ 6.91012 2.810-5
TaN 3 (TaN) 4 fF/ cm2
_ _
10-6
Si/SiO2 3-5 nm 510-11 F
_
1010 10-5
13
-
8/2/2019 GaAs MOS_SKP
14/43
Fabrication steps1. GaAs wafer preparation
i. MOCVD grown of p-GaAs
TMGa and AsH3 were the precursors for Ga and As, respectively
Growth temperature: 600C
Carrier gas: H2
dopant: DEZn
Carrier concentrations: 1016 cm-3
14
-
8/2/2019 GaAs MOS_SKP
15/43
The GaAs samples were degreased in trichloroethylene,
acetone, and methanol and then cleaned in a solution of H2O2
NH4OHH2O in the ratio of 1:1:2 to remove native oxide and elemental
As, then rinsed with de-ionized water for 3 min, and dried the surfaceby N2 gun. Additionally, HF treatment was carried out by dipping the
sample in HF (1%) solution for 1 min.
ii. Degreasing of GaAs
2. Surface passivation of GaAs
i. Sulfur passivationThe sulfur passivation was done by dipping in (NH4)2S (20%) for
10 min. This was carried out at room temperature.
ii. Ultra thin layer ZnO passivation
Ultra thin ZnO passivation layer (1.8 nm) on GaAs was grown
by MOCVD . Diethylzinc(DEZn) and tertiary butanol (tBuOH) were
used as the Zn and O precursors, respectively. Nitrogen (N2) was used
as the carrier gas and the growth was carried out at 350 C.
15
-
8/2/2019 GaAs MOS_SKP
16/43
3. Sol-gel preparation of TiO2 and ZrO2 high-k dielectrics
TiO2 (0.25 0.33 M) preparation
Precursor: Titanium butoxide and 2-methoxyethanol
Preparation temperature: 70C
ZrO2 (0.25 0.30 M) preparation
Precursor: Zirconium butoxide and 2-methoxyethanol
Preparation temperature: 70C
After the surface passivation, the substrates were immediatelyloaded into a spin coater to obtain layers of high-kdielectrics onto GaAs.
Finally, the dried films were annealed in an N2-flow horizontal tube furnace
at a temperature of 500 C for 5 min. The thickness of the high-kdielectrics
was determined by ellipsometry.
16
4 M lli i b h l i
-
8/2/2019 GaAs MOS_SKP
17/43
4. Metallization by thermal evaporation
Gate electrode: Al; Back side ohmic contact: Pd-Ag
Diameter: 1.9610-3 cm2
Then annealing of the metal contacts was done at 300 C for 3 min
in a quartz tube in argon ambient.
CharacterizationsPhysical characterizations
Photoluminescence (PL)
X-ray photoelectron spectroscopy (XPS)
Raman spectra
Field emission scanning electron microscope
Cross sectional transmission electron microscope
Electrical characterizations
Current density Voltage (J-V)
Capacitance Voltage (C-V)
Conductance Voltage (G-V) Constant voltage stress (CVS) analysis17
-
8/2/2019 GaAs MOS_SKP
18/43
Confirmation of sulfur
PL of sulfur passivated
and unpassivated GaAsXPS spectrum for S-2p
Raman spectrum for
anatase TiO2
XPS spectra: Ti core level spectrum.
(Inset) O1s core level spectrum.
Confirmation of TiO2
18
S lf t iti
-
8/2/2019 GaAs MOS_SKP
19/43
TiO2
GaAs20 nm
Sulfur transition
Frequency dispersion
4.9% per decade
C-V of Al/TiO2/GaAs as afunction of frequency
Cross sectional HRTEM
of GaAs/TiO2
C-V of Al/TiO2/GaAs as afunction of oxide thickness
G-f plot for determining
Dit
19
-
8/2/2019 GaAs MOS_SKP
20/43
Oxide Thickness (nm) QF (cm-2) EOT (nm) K Dit (cm
-2eV-1)
33 2.261011 4.76 27 1.481011
54 1.911011 7.88 26.7 1.841011
71 1.671011 10.33 26.8 2.91011
.1
2
1
2
2
2
2
m
m
maOXaOX
m
m
amaOX
P
G
CCCCCC
G
CCCCC
G
Effect of series resistance (RS) on D
it
Summary of the extracted electrical parameters
GP is the peak conductance; is the angular freq.;
Ca is actual device capacitance; Cm and Gm are the
measured capacitance and conductance, respectively;
Cox is the oxide capacitance.
Dit= 3.41011 eV-1cm-2
(without RS)
Dit= 4.21011 eV-1cm-2
(with RS)Non-inclusion of RS may change the Dit value 20
-
8/2/2019 GaAs MOS_SKP
21/43
-4 -2 0 20
20
40
60
80
100
120
GP/(
x1
0-10
F)
Voltage (V)
Thickness of TiO2
33 nm54 nm
71 nm
GP/ vs V plot for Al/TiO2/GaAsTangent loss vs V plot. Inset ac conductivity
vs voltage for Al/TiO2/GaAs
A MOS device with high-k dielectric has small leakage current comparedto its displacement current. Loss tangent is defined as the ratio of the leakage
current to the displacement current. When the voltage is increased beyond1 V,
the leakage current gets saturated; however, the displacement current increases,
so the dielectric loss tangent will decrease. It was also observed that the loss
tangent peak increased with the increase in oxide thickness. 21
-
8/2/2019 GaAs MOS_SKP
22/43
J-V plot for Al/TiO2/GaAs as a function
of oxide thickness.
J-V plot for Al/TiO2/GaAs as a function
of temperature.
At -1V, the leakage current is found to decrease by two orders of magnitude
while the temperature goes down from 290 to 100 K. This reduction in leakage
current density at low temperature suggests that thermally excited carriers play
a vital role in the current conduction at room temperature.
iTta 2
1
)(exp
At a voltage of1V, the current density was found to be of the order of10-7, 10-6
and 10-5 A cm-2for TiO2 thickness of71, 54 and 33 nm, respectively. The current
increased with the decrease in the thickness of TiO2 layer because of the increasein the transmission probability
22
-
8/2/2019 GaAs MOS_SKP
23/43
XPS spectra: Zr core level
spectrum. (Inset) O1s corelevel spectrum.
Cross sectional HRTEM
of GaAs/ZrO2
As 3d XPS spectra (i) with (ii) without
Sulfur passivation, Ga 3d spectra (b) with
and (c) without sulfur passivation.
As-O and Ga-O aresignificantly reduced
after sulfur passivation.
23
Effect of s lf r passi ation on electrical
-
8/2/2019 GaAs MOS_SKP
24/43
Effect of sulfur passivation on electrical
characteristics
C-V and J-V (inset) plots for GaAs MOS
with and without sulfur passivationC-V and G-V (inset) plots for GaAs MOS
as a function of frequency.
Hysteresis voltage for passivated MOS device: 150 mV
Hysteresis voltage for unpassivated MOS device: 400 mV
Very low leakage current, 10-7A/cm2 @ -1 V.
Frequency dispersion: 2% per decade. 24
-
8/2/2019 GaAs MOS_SKP
25/43
C-V plots for GaAs MOS as a function
of oxide thicknessC-V plots for GaAs MOS as a function
of substrate doping concentrationThe values of Dit (measured by conductance technique) were found to be 0.7510
12,
1.31012, and 2.41012 cm-2eV-1 for oxide thickness of25, 40, and 50 nm, respectively.
As the dielectric layer thickness increases, more and more strain is developed in theinterface leading to higher interface trap density.
The values of Dit were found to be 1.51012, 2.21012, and 3.81012 cm-2eV-1for the
substrate doping concentrations of11014, 2.51015, and 31016 cm-3, respectively.
With increased doping concentration, Dit increases possibly due to the exposed ions.
25
-
8/2/2019 GaAs MOS_SKP
26/43
Dielectric loss (k) vs voltage for
Al/ZrO2/GaAs MOS device
Dielectric loss vs voltage for
Al/ZrO2/GaAs MOS device
Dielectric loss vs voltage forAl/ZrO2/GaAs MOS device
K and tan values decrease with increasing frequency
due to the presence of interface polarization
mechanism and this interface states cannot follow the
ac signal at high frequencies.
The values ofac conductance decrease with
decreasing frequency possibly due to the effect of
series resistance26
-
8/2/2019 GaAs MOS_SKP
27/43
Since current transport across the interface is a temperature-activated process, electrons at
low temperatures are able to surmount the lower barriers, and so transport
mechanism will be dominated by the current flowing through the lower barrier height and,
consequently, ideality factor will be larger.
As the temperature increases, more and more electrons gain sufficient energy to surmount thehigher barrier. As a result, the apparent barrier height will increase with
the temperature.
An apparent increase in the ideality factor and a decrease in the barrier height at low
temperatures are caused possibly by effects such as nonuniformity of the interfacial charges,
barrier inhomogeneities at the interface, and potential drop across oxide layer. 27
-
8/2/2019 GaAs MOS_SKP
28/43
XPS spectra: Zn core level spectrum.
(Inset) Zn 3d core level spectrum.
PL spectra for unpassivated and passivated
GaAs surfaces using ZnO layer
Ultra thin (1.8 nm) passivation layer of ZnO is sufficient for fabricating devices.
PL reduction for thick (>7 nm) ZnO passivated GaAs is most probably due to the
strain induced defects and dislocation generation in the deposited layer.
28
Intens
ity
Wh lt thi (~1 8 ) i t f i ti
-
8/2/2019 GaAs MOS_SKP
29/43
Why ultra thin (~1.8 nm) interface passivation
layer is essential for fabricating devices ??
Thick passivation layer produces strain induced defects and dislocations.
The carriers can easily tunnel to the surface through the potential barriers by
using ultra thin passivation layer (< 2nm). However, in the case of thick
passivation layer(> 7nm), the surface potential repels the carriers to the surface.
Although it reduces the surface recombination, but surface state density is quite
large at the ZnO passivation layer surface. Thus the electrons will be localized and
thereby band bending will occur.
For MOS device applications, thick ZnO passivation on GaAs reduces the
hysteresis voltage, but at the same time it reduces the oxide capacitance due to
increment ofequivalent oxide thickness. Thus, ultra thin passivation layer of ZnO
on GaAs is indispensable for fabrication of devices.
29
-
8/2/2019 GaAs MOS_SKP
30/43
HRTEM of (b) ZrO2/ZnO/GaAs
Thickness
ZrO2 : 9.5 nm
ZnO IPL: 1.8 nm 30
HRTEM of (a) ZrO2/GaAs
a) Inhomogeneous interface was achieved between GaAs and high-kdue to the interdiffusion of Ga or As into the high-k.
b) A smooth interface of 1.8 nm ZnO IPL between GaAs and high-k
-
8/2/2019 GaAs MOS_SKP
31/43
XPS spectra: As 3d core level spectrum (a) without ZnO passivation (b) with ZnOpassivation; Ga3d core level spectrum (c) without ZnO passivation (d) with ZnO
passivation.
As-O and Ga-O are significantly reduced after ZnO passivation. Thus, Fermi
level pinning is minimized.31
-
8/2/2019 GaAs MOS_SKP
32/43
C-V and J-V (inset) plots for GaAs MOS
with and without ZnO passivationC-V plot for GaAs MOS as function of
frequency
Well stretched C-V with small hysteresis (0.13 V)
Very low leakage current, 10-6 A/cm2 @ -1 V.
Very low frequency dispersion, only 1% per decade
32
-
8/2/2019 GaAs MOS_SKP
33/43
The C-V curve was shifted towards negative gate voltage with stress time. This
phenomenon was attributed to the positive charge generation in the gate stack.The variation of flatband voltage (VFB) as a function of stress time under
constant gate voltage stress for the ZrO2/ZnO gate dielectric. The small flatband
voltage shift indicates reasonable reliability due to the presence ofinterfacial ZnO
layer in between ZrO2 and GaAs
C-V plot in constant voltage stress @-3 V; (inset) flatband voltage shift vs.
stress time
33
-
8/2/2019 GaAs MOS_SKP
34/43
GaAs
ZrO2/GaAs
ZrO2
GaAs
ZrO2/ZnO/GaAs
ZrO2
0.3 eV
2.96 eV
0.3 eV
0.3 eV
0.3 eV
3.45 eV
Intensity(a.u)
The effective VBO for ZrO2 andGaAs is 2.66 eV
The effective VBO for ZrO2 and
GaAs is 3.15 eV (with ZnO IPL)
The effective CBO for ZrO2 and
GaAs is 1.59 eV
The effective VBO for ZrO2 and
GaAs is 1.1 eV (with ZnO IPL)
34
IPL Thi k C i H D ( L k
-
8/2/2019 GaAs MOS_SKP
35/43
IPL Thickness
(nm)
Capacitan
ce
Hystere
sis (V)
Dit (cm-
2eV-1)
Leakage
current @-
1V (A/cm2)
Sulfur 10.5
(Al2O3)
0.6
F/cm2
0.43 51011 310-8
Ge 6.5 (HfO2)
+ 1.5 Ge
2.6
F/cm2
0.27 51011 310-4
Si 7 HfO2 +
1.5 Si
1.2
F/cm2
0.8
_
10-6
AlON 10.8 (TiO2)
+ 3.3
(AlON)
1 F/cm2 _ 6.91012 2.810-5
TaN 3 (TaN) 4 fF/ cm2
_ _
10-6
Si/SiO2 3-5 nm 510-11 F
_
1010 10-5
ZnO 9.5 (high-
k) + 1.8
(ZnO)
1.8
F/cm2
0.14 2.51011 10-6 Present
work35
-
8/2/2019 GaAs MOS_SKP
36/43
36
-
8/2/2019 GaAs MOS_SKP
37/43
37
The emission rate is given by
]exp[kT
EENVe
VT
VthPP
(1)
The eq.(1) can be written as
]exp[2
kT
ETe
PP
Where ]exp[kT
EAP
AVT
EEEE )(and
The eP can be obtained by the rate window t1 and t2 in DLTS measurement, and isgiven by
12
12 )/ln(
tt
tt
eP
(3)(2)
1
23 ln t
tkT
C
CNCD
O
AOXGaAsit
The interface trap density (Dit) can be calculated by
-
8/2/2019 GaAs MOS_SKP
38/43
38
The activation energy and capture crosssection were determined using theArrhenius plot eP/T
2 vs 1000/T
The conventional DLTS spectra of theMOS capacitor with different ratewindows
The activation energy was found to be0.30 eV
The capture cross section was found to be5.7010-19 cm2
The interface trap density was found to be1.801011 eV-1cm-2
-
8/2/2019 GaAs MOS_SKP
39/43
39
In the pulse period, the relationship between DLTS signal intensity and the pulsetime is given by
C
U
U
tCtC
exp1)()( maxmax
:
:
:
)(max UtC Max DLTS signal intensity when pulse time is tu
)(max C Max DLTS signal intensity when traps are completely filled
CThe capture time constant
(4)
The hole capture cross section is given by
PVthC
P
1
The active energy for capture cross section can be written as
P
AkTE ln
The energy level position of the trap is given by
AVT
EEEE
-
8/2/2019 GaAs MOS_SKP
40/43
40
The capture time constant was found to be0.84 S
The capture cross section for traps was found to be6.61022 cm2
The active energy for capture cross section was found to be0.17 eV
The energy level position of the trap was found to be 0.14 eV by IF DLTS
The interface trap density at 0.14 eV and minimum were found to be5.31011
eV-1cm-2 and 1.51011 eV-1cm-2 , respectively.
The IF-DLTS spectra as a functionof pulse time
The variations in Dit as a functionof ET-EV.
Summary
-
8/2/2019 GaAs MOS_SKP
41/43
SummaryThe oxide thickness-dependent electrical and dielectrical properties such as
interface trap density, flatband voltage, fixed oxide charges, ac conductivity ,
dielectric loss, capacitance and leakage current of Al/high-k/p-GaAs MOS devices
were investigated
Very smooth interface was achieved between high-k and sulfur passivated GaAs
(from HRTEM image). The interface trap density is very low, thus, assuring very
good interface.
For sulfur passivated MOS devices, Fermi level was removed, as a result low
leakage current, low frequency dispersion, and low hysteresis voltage was observed
non-inclusion of series resistance may result in underestimation of the value of
the interface trap density in GaAs-based MOS devices
The dielectric loss decreases with increase in frequency, whereas, the ac
conductivity shows the opposite trend.
Barrier height increases with increase in temperature whereas, the ideality factor
shows the opposite trend. 41
Ultra thin ZnO passivation layer (1 8 nm) is indispensable for fabricating GaAs
-
8/2/2019 GaAs MOS_SKP
42/43
Ultra thin ZnO passivation layer (1.8 nm) is indispensable for fabricating GaAs
based MOS devices
A very good interface was achieved in between ZnO passivated GaAs and high-k.
The interface trap density was found to be very low, only 2.510
11
eV
-1
cm
-2
andthe frequency dispersion is very low, only 1%/decade.
Ga-O and As-O were fully suppressed at the interface between high-k and ZnO
passivated GaAs. Thus, Fermi level pinning was removed.
The VBO and CBO for ZrO2/GaAs stacks were 2.66 and 1.59 eV, respectively,
whereas, for ZrO2/ZnO/GaAs stacks these were 3.15 eV and 1.1 eV, respectively.
The variation of flatband voltage (VFB) as a function of stress time under
constant gate voltage stress for the high-k/ZnO gate stacks. The small flatband
voltage shift indicates reasonable reliability due to the presence of interfacial ZnO
layer in between high-k and GaAs.
The DLTS study for ZnO passivated GaAs MOS devices clearly reveals that the
activation energy is very low and consistency with Si/SiO2 MOS devices. Theinterface trap density was found to be very low, 1.51011 eV-1cm-2
42
-
8/2/2019 GaAs MOS_SKP
43/43
top related