hardware implementation of tactile data processing methods for the reconstruction of contact force...

Alternative educational activity a.a. 2014/2015

Hardware Implementation of Tactile Data Processing Methods for the Reconstruction

of Contact Force Distributions

by Davide Cimino

February 3rd 2016

The system

Transducers

Interface

electronics

Digital

filtering

Data processin

g

Data processing

Contact Force Reconstruction

From the measured normal stress component in the sensors, the goal is to reconstruct complete contact force vectors, at discrete points on the upper surface layer.

Algorythm

Boussinesq’s equation allows the resolution of direct problem:

=

𝑏=𝐶𝑥

=

𝑥=𝐶−1𝑏Inverse: ?𝑚=𝑛 𝑚=3𝑛

𝑠𝑖𝑧𝑒 (𝑥 )=𝑚𝑠𝑖𝑧𝑒 (𝑏 )=𝑛

Maximization of a Global Efficiency Functional

A few HW issues

Main target:

Translate Matlab code into VHDL designMatlab minimization

• Minimization is performed by a too complex Matlab algotythm for HW design. It has to be translated into HW friendly procedure.

Precision

• All operations involve fractional values, whose order of magnitude varies widely. A smart fixed point arithmetic is required.

Vector calculus

• Most of the operations involve vector calculus. A smart vectorial architecture has to be developed to manage vectors.

Main blocks

Start from basic blocks:

• Matrix – Vector multiplier• Vectors Adder and Subtracter• Elements accumulator• Vector and scalar product

Five main structures:1. Double loop operations2. Elements accumulators3. Element by element operations4. Vector – Scalar operations5. Scalar product

1.

2.

3.

4.

5.

General BehaviorThe block itself generates addresses to: Read from memory Write on memory

READ address

WRITE address

DATA out

DATA in

Read memory Write memory

Main components

FSM•Generates control signals for datapath•Manages write and read addresses

Datapath•Implements fixed-point operations•Contains registers to be used as accumulators

Fixed point operationsAccording to a statistical analysis a 16 bits fixed-point arithmetic has to be considered. Most of the device will be based on a one integer part bit fixed-point arithmetic:

Integer part Fractional part

Datapath will handle fixed-point operations

Software

VHDL code development, circuit design and simulations have been performed using

Which allows deployment on most of Xilinx’s FPGA families .

Results

In the following slides a few Xilinx simulations outputs will be presented.

Adder

Vector-Vector Adder

clk

resetstart

begin_read1begin_read2begin_write

din1din2

addRead1addRead2addWrite

we

dout

is_inactive

Adder

Conclusions

The following blocks have been successfully designed and properly tested:

Matrix-Vector product

Scalar Product

Vector Product

Vector Addition

ISICT

Economics and Management

Technical and Scientific Subjects

Alumni network

Thank you!