hardware interrupts (hwi) chapter 5 c6000 integration workshop copyright © 2005 texas instruments....

Hardware Interrupts (HWI)

Chapter 5

C6000 Integration Workshop

Organization

Channel

2. EDMA copies values from one buffer to another

Lab 5…

1. CPU writes buffer with sine values

Frame Transfer Complete3

3. When the EDMA transfer is complete EDMA signals CPU to refill the buffer EDMA re-initializes itself

Technical TrainingOrganization

Outline

Hardware Interrupts (HWI) Generating Interrupt with the EDMA Enabling & Responding to HWI’s

EDMA Auto-Initialization

Exercise

Optional Topics

Generate EDMA Interrupt

You can prevent (or enable) the channel from sending an interrupt…

What causes an EDMA channel to send an interrupt?

The channel’s “Transfer Count” going to zero

EDMA Channels

Channel #

EDMA Channels

Generate EDMA Interrupt (TCINT)

OptionsOptions TCINT20 Channel’s Options register allows you to enable/disable

interrupt generation

Similar to the CPU's interrupt recognition, the EDMA has flag/enable bits ...

Channel #

TCINT=0

Options

Generate EDMA Interrupt (TCINT)EDMA Channels

Channel #

TCINT=0

Options

OptionsOptions TCINT20 The Channel Interrupt Pending Register (CIPR) records

that an EDMA transfer complete has occurred

How do you pick which CIPR bit gets set?

EDMA Interrupt Generation

CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

EDMAINT

Generate EDMA Interrupt (TCC)EDMA Channels

Channel #

TCINT=1

TCINT=0

TCINT=1

TCINT=0

TCC=1515

Options

OptionsOptions TCCTCINT20 19 16 Any channel can set any CIPR bit

Value in TCC bit field selects CIPR bit that will get set Setting any CIPR bit is allows for EDMA channel chaining

(described later in Optional Topics)

To read/write CIPR or enable/disable CIER …

CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

EDMAINT

Generate EDMA Interrupt (TCC)EDMA Channels

Channel #

TCINT=1

TCINT=0

TCINT=1

TCINT=0

TCC=1515

Options

OptionsOptions TCCTCINT20 19 16

Where does EDMAINT go?

CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

EDMAINT

Enabling/disabling CIER bits using: EDMA_intEnable(#) EDMA_intDisable(#)

Access CIPR bits using: EDMA_intTest(#) EDMA_intClear(#) EDMA_intAlloc(-1 or #) EDMA_intFree(#)

EDMA Interrupts the CPU

CPU Interrupt Logic

C6000CPU

EDMA Channels EDMA Interrupt

GenerationChannel #

EDMAINT

1. First, we examined how the EDMA generates interrupts to the CPU

2. Next, we explore how CPU interrupts (HWI’s) work

How do Interrupts Work?

•EDMA

•HPI

•Timers

•Ext pins

•Etc.

1. An interrupt occurs

2. Sets flag in IFR register

Interrupting the CPU

IER“Individual Enable”

GIE“Master

Enable”

‘C6000CPU

IFRInterrupt

EDMAINT

Interrupt Flag Reg (IFR)bit set when int occurs

Interrupt Enable Reg (IER)enables individual int's

IRQ_enable(IRQ_EVT_XINT2)IRQ_enable(IRQ_EVT_EDMAINT)

Global Interrupt Enable (GIE) bit in Control Status Reg

enables all IER-enabled interruptsIRQ_globalEnable() IRQ_globalDisable()

How do Interrupts Work?

•DMA

•HPI

•Timers

•Ext pins

•Etc.

1. An interrupt occurs

3. CPU acknowledges interrupt and …• Stops what it is doing• Turn off interrupts globally

• Clears flag in register

• Saves return-to location

• Determines which interrupt

• Calls ISR

2. Sets flag in IFR register

4. ISR (Interrupt Service Routine)• Saves context of system*• Runs your interrupt code (ISR)

• Restores context of system*

• Continues where left off*

* Must be done in user code, unless you choose to use the DSP/BIOS HWI dispatcherTechnical Training

Organization

Outline

Generating an EDMA Interrupt (EDMAINT)

Hardware Interrupts (HWI) How do interrupts work Interrupt service routines Configuring HWI’s Interrupt initialization (enabling int’s)

Exercise

Optional TopicsTechnical Training

Organization

Interrupt Service Routine

What do we want to happen when the EDMA interrupts the CPU?

void edmaHWI()

Interrupt Service Routine

What do we want to happen when the EDMA interrupts the CPU?

void edmaHWI()

SINE_blockFill();

EDMA_setChannel();

Outline

Hardware Interrupts (HWI) How do interrupts work Interrupt service routines Configuring HWI’s Interrupt initialization (enabling int’s)

Exercise

Organization

HWI Objects

C6000 has 16 hardware interrupts (HWI)

When multiple interrupts are pending, they are serviced in the order shown

Each interrupt object is associated with an: Interrupt source Interrupt service routine

Configure HWI Object

Notes: HWI_INT8 happens to be default for EDMA interrupt

void edmaHwi() { ... }

Configure HWI Object

Notes: HWI_INT8 happens to be default for EDMA interrupt Dispatcher saves/restores context for the ISR

How does the dispatcher work?Technical TrainingOrganization

HWI Interrupt Dispatcher

Count = 0 C6000CPU

EDMAINT

EDMA Channel

0 Reset _c_int00

… … HWI_nothing

4 EXTINT4 HWI_nothing

5 EDMAINT _edmaHWI

… … HWI_nothing

15 XINT2 HWI_nothing

HWI Dispatcher

void edmaHWI(){ …}

Context Save

Context Restore

Outline

Hardware Interrupts (HWI) How do interrupts work Interrupt service routines Configuring HWI’s (source, ISR) Interrupt initialization (enabling int’s)

Exercise

Organization

Enable CPU Interrupts

void initHWI(void)

Exercise: Fill in the lines of code required to enable the EDMAINT hardware interrupt:

Enable CPU Interrupts

void initHWI(void)

IRQ_enable(IRQ_EVT_EDMAINT);

IRQ_globalEnable();

Exercise 1: Fill in the lines of code required to enable the EDMAINT hardware interrupt:

Outline

Hardware Interrupts (HWI)

EDMA Dispatcher

Exercise

Optional Topics

EDMA ISR Problem

How many EDMA channels?

How many EDMA interrupt service routines could exist?

How many EDMA interrupts?

16 (or 64)

Therefore ...Technical Training

Organization

Which Channel?EDMA Channels EDMA Interrupt Generation

Channel #

TCINT=1

TCINT=0

TCINT=1

TCINT=0

TCC=1515

0CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

CIERCIPROptions

EDMAINT

Since there is only one EDMA interrupt to the CPU, how does the CPU know which channel caused it?

Which Channel?EDMA Channels EDMA Interrupt Generation

Channel #

TCINT=1

TCINT=0

TCINT=1

TCINT=0

TCC=1515

0CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

CIERCIPROptions

EDMAINT

Since there is only one EDMA interrupt to the CPU, how does the CPU know which channel caused it?Two methods:

1. Test each CIPR bit using: EDMA_intTest(bit #)

2. Automate testing each CIPR bit using EDMA Interrupt Dispatcher

EDMA Interrupt Problem?

Count = 0 C6000CPU

EDMAINT

EDMA Channel

0 Reset _c_int00

5 EDMAINT _edmaHWI

HWI Dispatcher

Context Save

Context Restore

EDMA_intDispatcher

Previously, our EDMAINT vectored directly to our Interrupt Service Routine

Can you think of a problem this might create? What if two different EDMA channels cause an interrupt? Do you want all channels to use the same ISR?

(Not very convenient) To solve this problem, CSL provides a simple

EDMA Interrupt Dispatcher

Count = 0 C6000CPU

EDMAINT

EDMA Channel

0 Reset _c_int00

5 EDMAINT _EDMA_intDispatcher

HWI Dispatcher

Context Save

Context Restore

EDMA Int Dispatcher1. Read CIPR & CIER2. For each enabled CIPR bit,

(starting with CIPR0), call the associated (“hooked”) function

CIPR bit

Function to Call (“hooked” function)

0 ….8 _edmaHWI

void edmaHWI(CIPR bit){ …}

How do you "hook" a function to a CIPR bit?Technical TrainingOrganization

EDMA_intHook

CIPR bit

Function to Call (“hooked” function)

0 ….8 _edmaHWI

void initEDMA(){ ...

EDMA_intHook(8, edmaHWI);

void initEDMA(){ ...

EDMA_intHook(8, edmaHWI);

Plugs entry in EDMA Interrupt Dispatch table

Outline

Chapter Objective

HWI – Hardware Interrupts

EDMA – Interrupt Generation

EDMA – Auto-Initialization What is it? How many are there? 6 Step Procedure

Summary & Exercise

Organization

When the Transfer is Complete …

Source = 0x0

Destination = 0x10

Transfer Count = 5

Options

Link AddrCount Reload31 16 15 0

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

When TC (transfer count) reaches 0 …

Options

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

Source = 0x1

Destination = 0x11

Transfer Count = 4

Options

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

Source = 0x2

Destination = 0x12

Transfer Count = 3

Options

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

Source = 0x3

Destination = 0x13

Transfer Count = 2

Options

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

Source = 0x4

Destination = 0x14

Transfer Count = 1

Options

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

When TC (transfer count) reaches 0: Channel stops moving data EDMA can send interrupt to CPU

(just discussed)

Which registers have changed since EDMA was started?

Source, Destination, Count

How can the EDMA parameters get reloaded?

Source = 0x5

Destination = 0x15

Transfer Count = 0

When the Transfer is Completes …

Options

When TC (transfer count) reaches 0: EDMA can reload the channel’s parameters

from one of the many Reload sets Each Reload set consists of six 32-bit values

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA Channel

Reload 21 (69)

Reload 1

Reload 2

Reload 0

Essentially, the EDMA has its own 2KB parameter RAM split between channels & reloads

How can you choose a specific reload set?

Source = 0x5

Destination = 0x15

Transfer Count = 0

When the Transfer is Completes …

31 16 15 0

Channel 63 (15)

Channel 1

Channel 2

Channel 0

EDMA EDMA ChannelLINK=1

Essentially, the EDMA has its own 2KB parameter RAM split between channels & reloads

Source = 0x5

Destination = 0x15

Transfer Count = 0

Options

Link AddrCount Reload

Reload 21 (69)

Reload 1

Reload 2

Reload 0

When TC (transfer count) reaches 0: EDMA can reload the channel’s parameters

from one of the many Reload sets Each Reload set consists of six 32-bit values Link Address points to the next Reload setup Auto-Init, Reload, and Linking all refer to the

same EDMA feature

Creating a “Linked-List” of Transfers

Offloads CPU ... can reinitialize all six registers of an EDMA channel Next transfer specified by Link Address Perform simple re-initialization or create linked-list of events Useful for ping-pong buffers, data sorting, circular buffers, etc.

Source

Destination

Transfer Count

Options (Link=1)

Channel 0 Source

DestinationTransfer Count

Options (Link=1)

IndexLink AddrCount Reload

Reload 1

Source

DestinationTransfer Count

Options (Link=1)

IndexLink AddrCount Reload

Reload 2

Why auto-initialization? What resources does EDMA have? What are the steps?

Reloading an EDMA channel in 6 Steps

Channel 0

Channel 15

hMyHandle Options (Link = 1)

Source

Destination

Link AddrCnt Reload

Transfer Count

Reload 1

Reload 21 (69)

1Procedure

1. Choose LINK option

Channel 0

Channel 15

Source

Destination

Link AddrCnt Reload

Transfer Count

Reload 1

Reload 21 (69)

hMyReload2

Procedure

2. Allocate handle for reload values

Channel 0

Channel 15

Source

Destination

Link AddrCnt Reload

Transfer Count

Reload 1

Reload 21 (69)

hMyReload2 3

Procedure

3. Allocate a reload set

Channel 0

Channel 15

Source

Destination

Link AddrCnt Reload

Transfer Count

Reload 1

Reload 21 (69)

Options

Source

Destination

Link AddrCnt Reload

Transfer Count

hMyReload2 3 4

And the 5th step is ...

Procedure

3. Allocate a reload set

4. Configure reload set (with same values as original channel)

Steps 5 & 6: Set the Link Address fields

Channel 0

Channel 15

hMyHandle Options

Source

Destination

Link AddrCnt Reload

Transfer Count

Reload 1

Reload 21 (69)

Options

Source

Destination

Link AddrCnt Reload

Transfer Count

hMyReload

EDMA_link(hMyReload, hMyReload)

EDMA_link(hMyHandle, hMyReload)

EDMA_link() pokes hMyReload address into Link Address field

3 Allocate a Reload location (reserve a reload set; -1 for “any”)

hMyReload = EDMA_allocTable(-1);

1 Modify your config to enable linking:EDMA_OPT_RMK( … EDMA_OPT_LINK_YES, … ),

2 Create a handle to reference a Reload location:

EDMA_Handle hMyReload;

4 Configure reload set (writes config structure to reload set)

EDMA_config(hMyReload, &myConfig);

Update Link Address fields (modifies field in chan, not myConfig struct)

EDMA_link(hMyHandle, hMyReload);EDMA_link(hMyReload, hMyReload);6

Outline

Chapter Objective

EDMA – Auto-Initialization

Summary Generate Interrupt (EDMA, HWI) EDMA ISR Summary of CSL’s EDMA functions

Exercise

LabTechnical Training

Organization

Generate EDMA Interrupt Summary

Set EDMA to generate an interrupt to the CPU:1. (CIPR) Reserve CIPR bit using EDMA_intAlloc()2. (Options) TCINT = 1

TCC = set # to match reserved CIPR bit3. (CIER) Set CIER bit to match TCC value

Set CPU to respond to interrupt from EDMA1. (IER) Enable individual EDMA interrupt2. (CSRGIE) Enable interrupts globally

EDMA Channels EDMA Int Generation

Channel #

TCINT=1

TCINT=0

TCINT=1

TCINT=0

TCC=1515

0CIER0 = 0

CIER1 = 0

CIER8 = 1

CIER15 = 0

CIERCIPROptions

CPU Interrupts

IER4 = 0

IER5 = 0

IERx = 1

IER15 = 0

IERIFR

CPUEDMAINT

Part 1:Allow EDMA to

Generate Ints

Part 2:Enabling CPU Ints

1 Modify EDMA Config structure for TCINT & TCC

EDMA_OPT_TCINT_YES, //set channel to interrupt CPUEDMA_OPT_TCC_OF(0), //set TCC in code

gTcc = EDMA_intAlloc(-1); //reserve TCC (0-15)myConfig.opt |= EDMA_FMK(OPT,TCC, gTcc); //set TCC in myConfig

EDMA Interrupts (6 steps)

What does the _FMK macro do?

CSL’s _FMK macro (field make)

19 160011

gTCC=3

EDMA Options Register

Peripheral Register Field Value

EDMA_FMK(OPT, TCC, gTCC)

= 0x00030000

Part 1:Allow EDMA to

Generate Ints

EDMA Interrupts (Part 1)1 Modify EDMA Config structure for TCINT & TCC

EDMA_OPT_TCINT_YES, //set channel to interrupt CPUEDMA_OPT_TCC_OF(0), //set TCC in code

gTcc = EDMA_intAlloc(-1); //reserve TCC (0-15)myConfig.opt |= EDMA_FMK(OPT,TCC, gTcc); //set TCC in myConfig

What about setting up hardware interrupts?

3 Set the appropriate bit in the CIER register

EDMA_intEnable(gTcc); // must match chosen TCC value

2 Hook the ISR to the appropriate TCC value:

EDMA_intHook(gTcc, myISR);

Part 2:Enabling CPU Ints

EDMA Interrupts (Part 2)

5 Set the appropriate bit in the IER register

IRQ_enable(IRQ_EVT_EDMAINT);

6 Turn on global interrupts

IRQ_globalEnable( ); // turn on interrupts globally

4 Include the header file

#include <csl_irq.h>

When the transfer completes…what happens?Technical TrainingOrganization

Summary

Generate Interrupt (EDMA, HWI) EDMA ISR Summary of CSL’s EDMA functions

EDMA ISR

Count = 0C6000

CPUEDMAINT

void edmaHwi(CIPR bit) {

SINE_blockFill(…);

EDMA_setChannel(hMyChannel);

When the transfer count reaches zero: EDMA interrupt is sent to the CPU Channel reg’s are re-initialized (autoinit)

EDMA Dispatcher will:

Read CIPR and CIER Clear CIPR bits Call ISR functions for set (and enabled) CIPR bits

Your ISR needs to:

Perform whatever your system requires Initiate the next block transfer with EDMA_setChannel

(unless your system uses EDMA synchronization – discussed in Ch 6)

HWI Dispatcher

EDMA Dispatcher

Summary

Generate Interrupt (EDMA, HWI) EDMA ISR Summary of CSL’s EDMA functions

EDMA_intEnableEDMA_intDisable

EDMA_getChannel ER

EDMA_setChannel ESR

EDMA_clearChannel ECR

EDMA_enableChannelEDMA_disableChannel

EDMA_intAllocEDMA_intFreeEDMA_intTest

EDMA_intClear

EDMA_enableChainingEDMA_disableChaining

EDMA Functions (Which Registers they Affect)

Outline

Chapter Objective

Summary

Exercise

Optional Topics

Exercise 1 (Review)

void edmaHwi(void){

SINE_blockFill(gBuf0, BUFFSIZE); // Fill buffer with sine data

EDMA_setChannel(hEdma); // start EDMA running

• Complete the following Interrupt Service Routine.

Here’s a few hints: Follow the code outlined on the “EDMA ISR” slide. Don’t forget, though, that our exercise (and the upcoming lab) uses

different variable names than those used in the slide’s example code. To “fill the buffer”, what function did we use in Labs 2 and 4 to create

a buffer of sine wave data?

Exercise 2: Step 1

EDMA_Config gEdmaConfig = { EDMA_OPT_RMK(

EDMA_OPT_PRI_LOW, // Priority?EDMA_OPT_ESIZE_16BIT, // Element size?EDMA_OPT_2DS_NO, // 2 dimensional source?EDMA_OPT_SUM_INC, // Src update mode?EDMA_OPT_2DD_NO, // 2 dimensional dest?EDMA_OPT_DUM_INC, // Dest update mode?EDMA_OPT_TCINT_NO, // Cause EDMA interrupt?EDMA_OPT_TCC_OF(0), // Transfer complete code?EDMA_OPT_LINK_NO, // Enable link parameters?EDMA_OPT_FS_YES ), // Use frame sync?

... };

1. Change gEdmaConfig so that it will: (Just cross-out the old and jot in the new value)

Interrupt the CPU when transfer count reaches 0 Auto-initialize and keep running

Exercise 2: Step 1

EDMA_Config gEdmaConfig = { EDMA_OPT_RMK(

EDMA_OPT_PRI_LOW, // Priority?EDMA_OPT_ESIZE_16BIT, // Element size?EDMA_OPT_2DS_NO, // 2 dimensional source?EDMA_OPT_SUM_INC, // Src update mode?EDMA_OPT_2DD_NO, // 2 dimensional dest?EDMA_OPT_DUM_INC, // Dest update mode?EDMA_OPT_TCINT_NO, // Cause EDMA interrupt?EDMA_OPT_TCC_OF(0), // Transfer complete code?EDMA_OPT_LINK_NO, // Enable link parameters?EDMA_OPT_FS_YES ), // Use frame sync?

... };

1. Change gEdmaConfig so that it will: (Just cross-out the old and jot in the new value)

Interrupt the CPU when transfer count reaches 0 Auto-initialize and keep running

Exercise 2: Steps 2-42. Reserve “any” CIPR bit (save it to gXmtTCC). Then set this value in the

gEdmaConfig structure.

3. Allow the EDMA’s interrupt to pass through to the CPU.

That is, set the appropriate CIER bit.

(Hint: the TCC value indicates which bit in CIPR and CIER are used)

4. Hook the ISR function so it is called whenever the appropriate CIPR bit

is set and the CPU is interrupted.

Exercise 2: Steps 2-42. Reserve “any” CIPR bit (save it to gXmtTCC). Then set this value in the

gEdmaConfig structure.

3. Allow the EDMA’s interrupt to pass through to the CPU.

That is, set the appropriate CIER bit.

(Hint: the TCC value indicates which bit in CIPR and CIER are used)

4. Hook the ISR function so it is called whenever the appropriate CIPR bit

is set and the CPU is interrupted.

gXmtTCC = EDMA_intAlloc(-1);gEdmaConfig.opt |= EDMA_FMK (OPT, TCC, gXmtTCC);

EDMA_intEnable(gXmtTCC);

EDMA_intHook(gXmtTCC, edmaHWI);

Exercise 2: Steps 5

5. Enable the CPU to accept the EDMA interrupt. (Hint: Add 3 lines of code.)

void initHwi(void){

Exercise 2: Steps 5

5. Enable the CPU to accept the EDMA interrupt. (Hint: Add 3 lines of code.)

#include <csl_irq.h>

void initHwi(void){

IRQ_enable(IRQ_EVT_EDMAINT); IRQ_globalEnable(void);

Exercise 2: Steps 6-9 (EDMA Reload)

6. Declare a handle for an EDMA reload location and name it

hEdmaReload:

7. Allocate one of the Reload sets: (Hint: hEdmaReload gets this value)

8. Configure the EDMA reload set:

9. Modify both the EDMA channel and the reload set to link to the

reload set of parameters:

Exercise 2: Steps 6-9 (EDMA Reload)

6. Declare a handle for an EDMA reload location and name it

hEdmaReload:

7. Allocate one of the Reload sets: (Hint: hEdmaReload gets this value)

8. Configure the EDMA reload set:

9. Modify both the EDMA channel and the reload set to link to the

reload set of parameters:

EDMA_Handle hEdmaReload;

hEdmaReload = EDMA_allocTable( -1 );

EDMA_config (hEdmaReload,&gEdmaConfig);

EDMA_link(hEdma, hEdmaReload);EDMA_link(hEdmaReload, hEdmaReload);

Outline

Chapter Objective

Summary

Exercise

Optional Topics

Lab 5 – Programming the EDMA

CPUgBuf0

Frame Transfer Complete

Pseudo Code

1. CPU generates 32 sine values into buf0

2. EDMA transfers 32 elements from buf0 to buf1

3. EDMA sends “transfer complete” interrupt to CPU

4. Go to step 1

Lab 5 Debrief

1. Why did we use HWI_INT8? Why not HWI_INT7?

2. What should we check if we never get to the EDMA’s Interrupt Service Routine?

3. In an EDMA ISR, what needs to be checked and cleared? How did we do this in the lab?

4. Why do we need to allocate both a set of reload registers AND an EDMA channel?

Chapter 5: Optional Topics Saving Context in HWI’s (3 methods) Interrupts and the DMA (vs. EDMA) Chaining EDMA channels Additional HWI topics

Click Here for Chapter 6

Using the McBSP Serial Port

hardware interrupts (hwi) chapter 5 c6000 integration workshop copyright © 2005 texas instruments....

edma interrupt summaryonly

tcc valuecount interrupt

interrupt signal

edma channel chaining

intallocoptions tcint

cpus interrupt recognition

cipr bitvalue

ciprreserve cipr

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