hardware reference manual for i.mx53 quick...
Post on 24-Jul-2018
250 Views
Preview:
TRANSCRIPT
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 i
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
i.MX53 Quick Start Board Take your Multimedia Experience to the max
semiconductorfreescale TM
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 ii
PUBI – Public Use Business Information
How to Reach Us:
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Learn More: For more information about Freescale products, please visit www.freescale.com. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2011. All rights reserved.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 iii
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
TableofContents1. Introduction .......................................................................................................................................... 1
1.1. i.MX53‐QUICK START Board Overview ......................................................................................... 1
1.2. i.MX53‐QUICK START Board Kit Contents ..................................................................................... 2
2. List of Acronyms .................................................................................................................................... 3
3. Specifications ........................................................................................................................................ 4
3.1. i.MX535 Processor ........................................................................................................................ 4
3.2. DDR3 DRAM Memory ................................................................................................................... 7
3.3. Dialog DA9053 PMIC ..................................................................................................................... 7
3.4. MicroSD Card Slot (J4) ................................................................................................................... 8
3.5. SD Card Slot (J5) ............................................................................................................................ 8
3.6. SATA 7‐pin Data Connector (J7) .................................................................................................... 8
3.7. VGA Video Output (J8) .................................................................................................................. 8
3.8. LVDS Video Output (J9) ................................................................................................................. 9
3.9. Ethernet (J2B) ................................................................................................................................ 9
3.10. Dual USB Host Connector (J2A) ................................................................................................. 9
3.11. Micro‐B USB Device Connector (J3) ........................................................................................ 10
3.12. Audio Input/Output (J6/J18) ................................................................................................... 10
3.13. 5V Power Connector (J1)......................................................................................................... 10
3.14. Debug UART Connector (J16) .................................................................................................. 11
3.15. JTAG Connector (J15) .............................................................................................................. 11
3.16. Expansion Header (J13) ........................................................................................................... 12
3.17. User Interface Buttons ............................................................................................................ 12
3.18. User Interface LED Indicators .................................................................................................. 13
3.19. Optional Li‐ION Batter Connector (J14) .................................................................................. 14
3.20. Optional Back‐Up Coin Cell posts (JP1, JP2) ............................................................................ 14
3.21. PCB Shorting Traces ................................................................................................................ 15
4. Quick Start Board Connectors and Expansion Port............................................................................. 15
4.1. Wall 5V Power Jack (J1) ............................................................................................................... 16
4.2. RJ45 Ethernet Connector (J2B) ................................................................................................... 17
4.3. VGA DB15 Connector (J8) ........................................................................................................... 18
4.4. Debug UART DB9 Connector (J16) .............................................................................................. 19
4.5. Headphone Output Connector (J18) ........................................................................................... 20
4.6. Microphone Input Connector (J6) ............................................................................................... 21
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 iv
PUBI – Public Use Business Information
4.7. Dual USB Host Jack (J2) ............................................................................................................... 22
4.8. micro‐B USB Device Connector (J3) ............................................................................................ 23
4.9. SATA 7‐pin Data Connector (J7) .................................................................................................. 24
4.10. SD Card Connector (J5) ........................................................................................................... 25
4.11. microSD Card Connector (J3) .................................................................................................. 26
4.12. 20‐pin ARM JTAG Connector (J15) .......................................................................................... 27
4.13. LVDS Connector (J9) ................................................................................................................ 28
5. Quick Start Board Architecture and Design ........................................................................................ 29
5.1. 5V Power Supply ......................................................................................................................... 30
5.2. Dialog DA9053 PMIC ................................................................................................................... 31
5.2.1. Quick Start Power Rails ....................................................................................................... 33
5.2.2. Li‐ION Battery Charging ...................................................................................................... 35
5.2.3. Backlight LED Driver ............................................................................................................ 35
5.2.4. Touch‐Screen Operation ..................................................................................................... 36
5.2.5. Miscellaneous ..................................................................................................................... 36
5.3. 3.2V Secondary Voltage Regulator ............................................................................................. 38
5.4. i.MX53 Applications Processor.................................................................................................... 39
5.4.1. Peripheral Module Logic Voltage Levels ............................................................................. 39
5.4.2. Boot Mode Operations and Selections ............................................................................... 41
5.4.3. Clock Signals ........................................................................................................................ 48
5.4.4. i.MX53 Internal Regulators ................................................................................................. 49
5.4.5. Watch Dog Timer ................................................................................................................ 49
5.5. DDR3 SDRAM Memory ................................................................................................................ 51
5.6. Micro SD Card Connector ............................................................................................................ 52
5.7. Full Size SD Card Connector ........................................................................................................ 53
5.8. VGA Video Output ....................................................................................................................... 54
5.9. LVDS Video Output...................................................................................................................... 55
5.10. Expansion Port ........................................................................................................................ 56
5.11. Audio ....................................................................................................................................... 57
5.12. Ethernet .................................................................................................................................. 58
5.13. USB Host connections ............................................................................................................. 59
5.14. SATA ........................................................................................................................................ 60
5.15. Debug UART Serial Port........................................................................................................... 61
5.16. JTAG Operations ...................................................................................................................... 62
6. Connector Pin‐Outs ............................................................................................................................. 63
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 v
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
7. Board Accessories ............................................................................................................................... 80
7.1. HDMI Daughter Card ................................................................................................................... 80
7.2. LCD Display Daughter Card ......................................................................................................... 82
7.3. LVDS Display Set (Coming Soon) ................................................................................................. 84
8. Mechanical PCB Information .............................................................................................................. 86
9. Board Verification ............................................................................................................................... 88
10. Troubleshooting .............................................................................................................................. 92
10.1. PMIC Voltage Rail Test Points ................................................................................................. 93
11. Known Issues ................................................................................................................................... 95
12. PCB Component Locations .............................................................................................................. 96
13. Schematics .................................................................................................................................... 101
14. Bill of Materials ............................................................................................................................. 115
15. PCB information ............................................................................................................................ 122
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 vi
PUBI – Public Use Business Information
List of Figures Figure 1. DC Power Jack …………………………………………………………………………………………………………… 16 Figure 2. RJ45 Ethernet Connector……………………………………………………………………………………………. 17 Figure 3. VGA Connector………………………………………………………………………………………………………….. 18 Figure 4. Debug UART Connector…………………………………………………………………………………………….. 19 Figure 5. Headphone Output Connector………………………………………………………………………………….. 20 Figure 6. Microphone Connector (J6) …………………………………………………………………………………….. 21 Figure 7. Dual USB Host Connectors (J2) ……………………………………………………………………………….…. 22 Figure 8. micro‐B USB Device Connector (J3) ………………………………………………………………………….. 23 Figure 9. SATA Data Connector (J7) ………………………………………………………………………………………… 24 Figure 10. SD Card Connector (J5) …………………………………………………………………………………………….. 25 Figure 11. microSD Card Connector (J4) ……………………………………………………………………………………. 26 Figure 12. JTAG Connector (J15) ……………………………………………………………………………………….….…… 27 Figure 13. LDVS Connector (J9) ……………………………………………………………………………………..…….…….. 28 Figure 14. i.MX53 Smart‐Start Block Diagram…………………………………………………………………………….. 29 Figure 15. Board Main Power Circuit. ……………………………………………………………………………………….… 30 Figure 16. Boot Mode Resistor Locations TOP…………………………………………………………………………….. 46 Figure 17. Boot Mode Resistor Locations BOTTOM…………………………………………………………………….. 47 Figure 18. Clock Source Locations………………………………………………………………………………………………. 48 Figure 19. Watch Dog Timer Reset Trigger…………………………………………………………………………………. 50 Figure 20. Power Jack (J1) …………………………………………………………………………………………………………. 64 Figure 21. Micro‐B USB Connector (J3) …………………………………………………………………………………….. 64 Figure 22. Ethernet/Dual USB Conn (J2) …………………………………………………………………………………… 65 Figure 23. Headphone Connector (J18) ……………………………………………………………………………………. 66 Figure 24. Microphone Connector (J6) ……………………………………………………………………………………. 66 Figure 25. VGA DB15 Connector (J8) …………………………………………………………………………………………. 67 Figure 26. LVDS Connector (J9) …………………………………………………………………………………………………. 68 Figure 27. SATA Data Connector (J7) …………………………………………………………………………………………. 69 Figure 28. SD Card Connector (J5) …………………………………………………………………………………………….. 70 Figure 29. microSD Card Connector (J4) ……………………………………………………………………………………. 71 Figure 30. Debug UART Connector (J16) ……………………………………………………………………………………. 72 Figure 31. JTAG Connector (J15) ……………………………………………………………………………………………….. 73 Figure 32. Expansion Port (J13) ……………………………………………………………………………………………….… 74 Figure 33. Optional HDMI Daughter Card…………………………………………………………………………………… 80 Figure 34. MCIMX28LCD 4.3” WVGA Display Daughter Card…………………………………………….………… 82 Figure 35. LVDS Display Kit………………………………………………………………………………………………………… 84 Figure 36. Quick Start Board Dimensions…………………………………………………………………………………… 86 Figure 37. Ethernet Loopback Cable………………………………………………………………………………………….. 91 Figure 38. Regulator Output Capacitor Positions Bottom………………………………………………………….. 93 Figure 39. Regulator Output Capacitor Positions Top………………………………………………………………… 94 Figure 40. Major Component Highlights Top…………………………………………………………………………….. 97
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 vii
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
List of Figures (con)
Figure 41. Major Component Highlights Bottom………………………………………………………………………… 98 Figure 42. Assembly Drawing Top………………………………………………………………………………………………. 99 Figure 43. Assembly Drawing Bottom…………………………………………………………………………………………100 Figure 44. DC 5V INPUT……………………………………………………………………………………………….……………..102 Figure 45. MX53 POWER……………………………………………………………………………………………….……………103 Figure 46. MX53 DDR3 MEMORY…………………………………………………………………………………….………….104 Figure 47. MX53 CONTROL…………………………………………………………………………………………………………105 Figure 48. MX53 USB……………………………………………………………………………………………………….…………106 Figure 49. MX53 SD INTERFACE………………………………………………………………………………………….………107 Figure 50. MX53 AUDIO……………………………………………………………………………………………………….…….108 Figure 51. MX53 SATA…………………………………………………………………………………………………………..……109 Figure 52. MX53 VGA……………………………………………………………………………………………………………..….110 Figure 53. MX53 ETHERNET…………………………………………………………………………………………………….…111 Figure 54. EXPANSION HEADER……………………………………………………………………………………………….…112 Figure 55. DA9053 PMIC…………………………………………………………………………………………………………….113 Figure 56. DEBUG, ACCELEROMETER……………………………………………………………………………………….…114 Figure 57. Top Etch Layer…………………………………………………………………………………………………………..123 Figure 58. Second Etch Layer……………………………………………………………………………………………………..124 Figure 59. Third Etch Layer…………………………………………………………………………………………………………125 Figure 60. Fourth Etch Layer………………………………………………………………………………………………………126 Figure 61. Fifth Etch Layer………………………………………………………………………………………………………….127 Figure 62. Sixth Etch Layer………………………………………………………………………………………………………….128 Figure 63. Seventh Etch Layer……………………………………………………………………………………………………..129 Figure 64. Bottom Etch Layer………………………………………………………………………………………………………130 Figure 65. Soldermask Top………………………………………………………………………………………………………….131 Figure 66. Soldermask Bottom……………………………………………………………………………………………………132 Figure 67. Pastemask Top…………………………………………………………………………………………………………..133 Figure 68. Pastemask Bottom……………………………………………………………………………………………………..134 Figure 69. Silkscreen Top…………………………………………………………………………………………………………….135 Figure 70. Silkscreen Bottom………………………………………………………………………………………………………136
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 viii
PUBI – Public Use Business Information
List of Tables
Table 1. Regulator Timing Sequence…………………………………………………………………………………………32 Table 2. Quick Start Board Power Supply Rails…………………………………………………………………………33 Table 3. Port ID Resistor Values……………………………………………………………………………………………….36 Table 4. Module Voltage Supplies…………………………………………………………………………………………….40 Table 5. BOOT_MODE pin Settings………………………………………………………………………………………..…41 Table 6A. BOOT_CFG Word1……………………………………………………………………………………………………… 41 Table 6B. BOOT_CFG Word2……………………………………………………………………………………………………… 41 Table 6C. BOOT_CFG Word3……………………………………………………………………………………………………… 42 Table 7. Boot Mode Resistors TOP……………………………………………………………………………………………46 Table 8. Boot Mode Resistors BOTTOM…………………………………………………………………………………… 47 Table 9. DDR3 SDRAM Chip Organization………………………………………………………………………………… 51 Table 10. Micro‐SD Card Boot Options……………………………………………………………………………………… 52 Table 11. Full Size SD Card Boot Options…………………………………………………………………………………… 53 Table 12. SATA Boot Mode Configuration Table. ……………………………………………………………………… 60 Table 13. Terminal Setting Parameters……………………………………………………………………………………… 61 Table 14. Power Jack (J1) …………………………………………………………………………………………………………. 64 Table 15. Micro‐B USB Connector (J3) ………………………………………………………………………………………. 64 Table 16. Ethernet/Dual USB Conn (J2) ……………………………………………………………………………………..65 Table 17. Headphone Connector (J18) ……………………………………………………………………………………… 66 Table 18. Microphone Connector (J6) ………………………………………………………………………………………. 66 Table 19. VGA DB15 Connector (J8) …………………………………………………………………………………………. 67 Table 20. LVDS Connector (J9) …………………………………………………………………………………………………. 68 Table 21. SATA Data Connector (J7) …………………………………………………………………………………………. 69 Table 22. SD Card Connector (J5) ……………………………………………………………………………………………… 70 Table 23. microSD Card Connector (J4) ……………………………………………………………………………………. 71 Table 24. Debug UART Connector (J16) ……………………………………………………………………………………. 72 Table 25. JTAG Connector (J15) ……………………………………………………………………………………………….. 73 Table 26. Expansion Port (J13) …………………………………………………………………………………………………. 74 Table 27. Expansion Port Pin‐Mux Table……………………………………………………………………………………. 76 Table 28. Board Stack up information………………………………………………………………………………………… 87 Table 29. Problem Resolution Table………………………………………………………………………………………….. 92 Table 30. Output Capacitors and Values BOTTOM…………………………………………………………………….. 93 Table 31. Output Capacitors and Values TOP……………………………………………………………………………. 94
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 1
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
1. Introduction
This document is the Hardware Reference Manual for the i.MX53 Quick Start board based on the Freescale Semiconductor i.MX53 Applications Processor. This board is fully supported by Freescale Semiconductor. This Manual includes system setup and debugging, and provides detailed information on the overall design and usage of the i.MX53 Quick Start board from a Hardware Systems perspective.
1.1. i.MX53‐QUICKSTARTBoardOverview The Quick Start Board is an i.MX535 platform designed to showcase many of the most commonly used features of the i.MX535 Applications Processor in a small, low cost package. The MCIMX53‐START is an entry level development board and a near perfect subset of its larger sister board, the MCIMX53SMD, which is available as a full, near‐form factor tablet. Developers can start working with code on the Quick Start board, and then port it over to the SMD Tablet if additional features are desired. This gives the developer the option of becoming familiar with the i.MX535 Applications Processor before investing a large amount or resources in more specific designs. Features of the i.MX53 Quick Start board are: Processor: Freescale Applications Processor MCIMX535DVV1B
DRAM Memory: Micron 8Gb DDR3 SDRAM MT41J128M16HA‐187E:D
PMIC: Dialog Semiconductor DA9053
Mass Storage: 5 in 1 SD/MMC/SDIO Card Connector microSD Card Connector 7‐pin SATA Data Connector
Video Output: 15‐Pin D‐Sub VGA Connector 30‐Pin LVDS Connector
Ethernet: RJ‐45 Connector for 10/100 Base‐T
USB: Dedicated HS USB 2.0 Standard‐A Host Connector Shared HS USB 2.0 Standard ‐ Host and Micro‐B Device Connectors
Audio Connectors: 3.5mm Stereo Head Phone output 3.5mm Mono‐Microphone input and Mono Head Phone (right channel) output
Power Connectors: 5V mm Barrel Connector
Debug Connectors: 9‐Pin D‐Sub Debug UART Connector 20‐Pin Standard ARM JTAG Connector
Expansion Header: 120‐Pin Header (Populated) to Support 1 of the following: Optional HDMI Output Daughter Card (orderable) Optional WVGA and WQVGA LCD Display Daughter Cards (orderable) Camera Daughter Card (custom) SDIO Based WiFi Daughter card (custom)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 2
PUBI – Public Use Business Information
User Interface Buttons: Power, Reset, 2 User‐Defined Buttons
Indicators: 8 Status LEDs – External Power, PMIC ON, Fault Condition, and more
Li‐ION Battery Connector: 3‐Pin Header (unpopulated) for Li‐ION Battery for Low Power Operation
Coin Cell: Connection point for 2‐Pin Coin Cell (unpopulated) for RTC Operation
PCB: 3.0 inch x 3.0 inch (76.2 mm x 76.2 mm), 10 ‐ layer board
1.2. i.MX53‐QUICKSTARTBoardKitContents The i.MX53‐Quick Start Board comes with the following items:
i.MX53‐QUICK START Board microSD Card preloaded with Ubuntu Demonstration Software USB Cable (Standard‐A to Micro‐B connectors) 5V/2.0A Power Supply Quick Start Guide Documentation DVD
1.3. i.MX53QuickStartBoardRevisionHistory
Rev A – Proof of Concept Rev B – Prototype (Internal Freescale Development) Rev C – Prototype (Internal Freescale Development) Rev D – Production (Silicon: i.MX53 Rev 2.0, DA9053 Rev AA) Rev E – Production (Silicon: i.MX53 Rev 2.0, DA9053 Rev BB)
The board assembly version will be printed on a label, usually attached to the side of the Ethernet/Dual USB Connector (J2). The assembly version will be the letter designation following the schematic revision: 700‐26565 REV _
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 3
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
2. ListofAcronyms The following acronyms will be used throughout this document. AC97 ‐ Audio Codec ‘97 CMC ‐ Common Mode Choke CODEC ‐ Compression/Decompression DDR ‐ Double Data Rate DNP ‐ Do Not Populate HDMI ‐ High Definition Multimedia Interface I2C ‐ Inter‐Integrated Circuit I2S ‐ Integrated Interchip Sound IC ‐ Integrated Circuit IDE ‐ Integrated Debug Environment LAN ‐ Local Area Network LCB ‐ i.MX53 Smart‐Start LCD ‐Liquid Crystal Display LPDDR2 ‐ Low Power DDR2 MMC ‐ Multi Media Card PMIC ‐ Power Management Companion IC RMII ‐ Reduced Media Independent Interface RTC ‐ Real‐Time Clock SDRAM ‐ Synchronous Dynamic Random Access Memory SD ‐ Secure Digital SPI ‐ Serial Peripheral Interface SSI ‐ Synchronous Serial Interface ULPI ‐ UTMI Low Pin Interface USB ‐ Universal Serial Bus UTMI ‐ Universal Transceiver Macrocell Interface WDOG ‐ Watch Dog WLAN ‐ Wireless LAN
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 4
PUBI – Public Use Business Information
3. Specifications
3.1. i.MX535ProcessorThe i.MX535 Applications Processor (AP) is based on ARM Cortex‐A8TM Platform, which has the following features:
• MMU, L1 Instruction and L1 Data Cache • Unified L2 cache • Target frequency of the core (including Neon, VFPv3 and L1 Cache): 1.0 GHz • Neon coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP‐Lite)
coprocessor supporting VFPv3 • TrustZone
The memory system consists of the following components: • Level 1 Cache:
− Instruction (32 Kbyte) − Data (32 Kbyte)
• Level 2 Cache: − Unified instruction and data (256 Kbyte)
• Level2 (internal) memory: − Boot ROM, including HAB (64 Kbyte) − Internal multimedia/shared, fast access RAM (128 Kbyte) − Secure/non‐secure RAM (16 Kbyte)
• External memory interfaces: − 16/32‐bit DDR2‐800, LV‐DDR2‐800 or DDR3‐800 up to 2 Gbyte − 32 bit LPDDR2 − 8/16‐bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16‐bit ECC − 16‐bit NOR Flash. All WEIMv2 pins are muxed on other interfaces (data with NFC pins).
I/O muxing logic selects WEIMv2 port, as primary muxing at system boot. − 16‐bit SRAM, cellular RAM − Samsung One NANDTM and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode) The i.MX53 system is built around the following system on chip interfaces:
• 64‐bit AMBA AXI v1.0 bus – used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32‐bit AMBA AHB 2.0 bus – used by the rest of the bus master peripherals operating at 133 MHz.
• 32‐bit IP bus – peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz.
The i.MX53 makes use of dedicated hardware accelerators to achieve state‐of‐the‐art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 5
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
The i.MX53 incorporates the following hardware accelerator:
• VPU, version 3 – video processing unit • GPU3D – 3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Htri/s, 200 Mpix/s, and 800
Mpix/s z‐plane performance, 256 Kbyte RAM memory. • GPU2D – 2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance. • IPU, version 3M – image processing unit • ASRC – asynchronous sample rate converter
The I.MX53 includes the following interfaces to external devices: NOTE
Not all the interfaces are available simultaneously depending on I/O
multiplexer configuration.
• Hard disk drives: − PATA, up to U‐DMA mode 5, 100 MByte/s − SATA II, 1.5 Gbps
• Displays: − Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to
two interfaces may be active as once. − Two parallel 24‐bit display ports. The primary port is up to 165 Mpix/s (for example,
UXGA @ 60 Hz). − LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single
channel ports up to 85 MP/s (for example, WXGA @ 60 Hz) each. − TV‐out/VGA port up to 150 Mpix/s (for example, 1080p60).
• Camera sensors: − Two parallel 20‐bit camera ports. Primary up to 180‐MHz peak clock frequency,
secondary up to 120‐MHz peak clock frequency. • Expansion cards:
− Four SD/MMC card ports: three supporting 416 Mbps (8‐bit i/f) and one enhanced port supporting 832 Mbps (8‐bit, eMMC 4.4)
• USB − High‐speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY − Three USB 2.0 (480 Mbps) hosts:
High‐speed host with integrated on‐chip high speed PHY Two high‐speed hosts for external HS/FS transceivers through ULPI/serial,
support IC‐USB
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 6
PUBI – Public Use Business Information
• Miscellaneous interfaces: − One‐wire (OWIRE) port − Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio
multiplexer (AUDMUX) providing four external ports. − Five UART RS232 ports, up to 4.0 Mbps each. One supports 8‐wire, the other four
support 4‐wire. − Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port − Three I2C ports, supporting 400 kbps. − Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps − Two controller area network (FlexCAN) interfaces, 1 Mbps each − Sony Philips Digital Interface (SPDIF), Rx and Tx − Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel − Key pad port (KPP) − Two pulse‐width modulators (PWM) − GPIO with interrupt capabilities − Secure JTAG controller (SJC)
The system supports efficient and smart power control and clocking:
• Supporting DVFS (Dynamic Voltage and Frequency Scaling) and DPTC (Dynamic Process and Temperature Compensation) techniques for low power modes.
• Power gating SRPG (State Retention Power Gating) for ARM core and Neon • Support for various levels of system power modes. • Flexible clock gating control scheme • On‐chip temperature monitor • On‐chip oscillator amplifier supporting 32.768 kHZ external crystal • On‐chip LDO voltage regulators for PLLs
Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on)
• Secure JTAG controller (SJC) – Protecting JTAC from debug port attacks by regulating or blocking the access to the system debug features.
• Secure real‐time clock (SRTC) – Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches.
• Real‐time integrity checker, version 3 (RTICv3) – RTIC type 1, enhanced with SHA‐256 engine • SAHARAv4 Lite – Cryptographic accelerator that includes true random number generator (TRNG) • Security controller, version 2 (SCCv2) – Improved SCC with AES engine, secure/nonsecure RAM
and support for multiple keys as well as TZ/non‐TZ separation. • Central Security Unit (CSU) – Enhancement for the IIM (IC Identification Module). CSU is
configured during boot and by e‐fuses and determines the security level operation mode as well as the TrustZone (TZ) policy.
• Advanced High Assurance BOOT (A‐HAB) – HAB with the next embedded enhancements: SHA‐256, 2046‐bit RSA key, version control mechanism, warm boot, CSU and TZ initialization.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 7
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
3.2. DDR3DRAMMemory The i.MX53‐Quick Start board uses four 2‐Gigabit DDR3 SDRAM ICs manufactured by Micron for a total onboard RAM memory of 1 GigaByte. The SDRAM data width for each IC is 16‐bits. The chips are arranged in pairs that are controlled by each of the two chip select pins to form 32‐bit words for the i.MX53 CPU. On Die Termination (ODT) functionality has been implemented on the board, as well as the ability to separate out the I/O Voltage Supply from the main SDRAM Voltage Supply if desired.
3.3. DialogDA9053PMIC The DA9053 device is a small (7 x 7 mm, 0.5mm pitch) 169 ball VFBGA that provides nearly all power supply functions for the Quick Start board. The following is a feature list of the major functionality provided by the DA9053 PMIC for the Quick Start board:
• Power Supply resources: o 12 Low Drop Out (LDO) regulators
1 for internal PMIC purposes only (LDOCORE) 1 for charging optional back up coin cell 10 for platform needs
o 4 DC/DC Buck Converters (3 with DVS) 1 for the ARM Core supply (VBUCKCORE) 1 for the Peripheral Core supply (VBUCKPRO) 1 for the external SDRAM memory (VBUCKMEM) 1 for the internal cache memory (VBUCKPERI)
o 1 White LED driver and boost converter • Li‐ION battery Charger • Resistive touch screen interface • Expansion Port Card ID detect • Wall voltage supply over‐voltage protection • 1 HS‐I2C interface • External LDO regulator enable
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 8
PUBI – Public Use Business Information
3.4. MicroSDCardSlot(J4) The microSD Card slot is used as the primary means to boot the Quick Start board. The power source for the microSD Card slot is VLDO3_3V3. The microSD Card slot is not normally configured with a card detect feature. The MicroSD Card slot can be configured to boot from a MMCmicro card with an alternate boot option setting (see section on Boot Options).
3.5. SDCardSlot(J5) The SD Card slot is a 5‐in‐1 SD/MMC connector that acts as a secondary external memory media slot. The power source for the SD Card Slot is the auxiliary LDO regulator (DCDC_3V2). The SD Card slot can be configured as the boot source with an alternate boot option setting, as well as being configured for either SD or MMC card operation (see section on Boot Options). The SD Card Slot supports full 8‐bit parallel data transfers and can support SDIO cards (WiFi, BT, etc) designed to fit in a standard SD card slot. The Quick Start board has specifically been tested with an Atheros SD‐25 WiFi card.
3.6. SATA7‐pinDataConnector(J7) The SATA connector provides the means to connect an external SATA memory device to the Quick Start board. Commonly, this would be an External hard drive or a DVD/CD reader. Power for the SATA device needs to be supplied externally by the user via a 12‐pin power connector. It is possible to boot from a SATA drive by making OTP fuse changes. Once the fuse changes are made, they cannot be reversed.
3.7. VGAVideoOutput(J8) A standard VGA signal is output directly from the i.MX53 Processor with minimum external components required. Power for the TVE module of the i.MX535 Processor is supplied by VLDO7 of the PMIC and is set to 2.75V. If VGA output is not desired, it is possible to program the PMIC to turn off VLDO7 to conserve power. The VGA output supports a variety of video formats up to 150 Mega‐Pixels per second. Level shifters are required on the Horizontal and Vertical Synchronization signals as well as the VGA I2C communications signals in order to meet VGA specifications.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 9
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
3.8. LVDSVideoOutput(J9) The LVDS module of the i.MX53 Processor is connected to a 30‐pin LVDS connector. While the i.MX53 Processor is capable of outputting to two separate LVDS displays, only one connector is pinned out on the Quick Start board. The pin outs on the LVDS connector match the optional cable and 10” HannStar LVDS display that can be purchased optionally from Freescale. The single LVDS connector will support video formats up to 165 Mega‐Pixels per second. The power source for the LVDS module is a switchable output of the VBUCKPERI DCDC converter. This rail is shared with the SATA module and the USB module. If these modules are not being used, the PMIC can be programmed to turn off power to these three modules without affecting other 2.5V supplies to the remainder of the i.MX53 Applications Processor.
3.9. Ethernet(J2B) The i.MX53 Processor Fast Ethernet Module outputs RMII formatted signals to an external Ethernet PHY. The processor is capable of 10/100 Base‐T speeds. The Quick Start board uses the SMSC LAN8720A Ethernet Transceiver in a QFN‐24 package. 3.2V power is supplied to the Ethernet IC from the external LDO regulator. The output of the Ethernet PHY is connected to an RJ45 jack with integrated magnetic.
3.10. DualUSBHostConnector(J2A) The USB module of the i.MX53 Processor provides two high speed USB PHYs that are connected to each of the USB‐A Host Jacks on connector J2. One PHY provides Host‐only functionality and is connected to the upper USB jack on the connector tower. The second PHY is USB 2.0 OTG capable and is connected to the lower USB jack on the connector tower. Both jacks receive 5V power directly from the 5V Wall Power Supply, via a FET that can be controlled by software, and a 1.1A Poly‐fuse. The PMIC provides an over‐voltage functionality to limit voltage applied to the USB jack in the event that a DC Power Supply other than the original supply provided is used. Also, there is no current regulating device to limit current supplied to each jack, other than the Poly‐fuse.
NOTE The lower USB Host Jack is cross connected with the Micro‐B USB Device connector. This was done as a convenience to the user as cables with micro‐A plugs are still uncommon at the time the board was designed. The USB OTG PHY will switch to ‘device’ mode if a USB Host is attached to the micro‐B connector with a cable. This design is not recommended for release to the general electronics consumer population. This board has not been tested for USB compliance.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 10
PUBI – Public Use Business Information
3.11. Micro‐BUSBDeviceConnector(J3) The micro‐B USB connector is connected to the USB OTG PHY on the i.MX53 Processer, and is also connected to the Lower USB Host Jack on the connector tower. The connector’s external USB 5V power pin is connected to the USB_OTG_ID pin, which is normally pulled to ground via a 3.3K Ohm resistor. When a powered USB Host device is attached to the micro‐B USB connector, the USB_OTG_ID pin is pulled high and sends a signal to the USB OTG PHY to operate in device mode. The connector’s external USB 5V power pin is not connected to the PMIC, or any other power rails on the Quick Start board. Therefore, it is not possible to supply power to the Quick Start board via the USB connections.
3.12. AudioInput/Output(J6/J18) Analog audio input and output are provided by Freescale’s Low Power Stereo Codec, SGTL5000. The audio codec is connected to the i.MX53 Applications Processor via 4‐wire I2S communications, utilizing the AUDMUX5 port of the processor. The audio codec’s Headphone Amp provides up to 58 mW output to 16‐Ohm headphones at a typical SNR of 98 dB and THD+N of ‐86 dB. Typical power consumption is 11.6 mW. In addition, the audio codec can perform several enhancements to the output including virtual surround, added bass and three different types of equalization. The Microphone Input module of the Stereo Codec is also used, with the microphone input connected to the tip pin of the Microphone Jack (J6). Microphone Bias voltage is applied on the Quick Start board and not as a separate connection to the Microphone Jack. If the user desires to use a combined microphone, mono headphone device, the ferrite bead on L25 can be moved to the L22 pads, redirecting the right channel output to the Microphone Jack. A 2.5mm to 3.5mm adapter may be necessary to convert the microphone, mono headphone device to fit the Microphone Jack. On both the Headphone Jack and Microphone jack, a fourth pin is used to detect the insertion of a plug into either jack. When a standard 3‐pin device is inserted into the 4‐pin jack, the detect line is grounded, indicating to the i.MX53 Processor that the plug has been inserted.
3.13. 5VPowerConnector(J1) A 2.0mm x 6.5mm barrel connector is used which should fit standard DC Plugs with an inner dimension of 2.1mm and an outer dimension of 5.5mm. If an alternate power supply is used (not the original, supplied power supply), it should supply no more than 5.25V / 3A output. If the PMIC senses too high voltage at the connector input, it will turn off isolation FET Q1 to protect the Quick Start board. In between the Power Connector and the isolation FET is a single blow, fast acting fuse to protect the Quick Start board from an over current situation fault. If a Wall Power Supply is properly connected to the Quick Start board, and the green 5V power LED indicator is not lit, it could mean that either the fuse has been blown, or that the voltage output of the power supply is too high.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 11
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
3.14. DebugUARTConnector(J16) UART1 of the i.MX53 Processor is connected to an RS‐232 output to be used as a debug output for the developer. The Transmit (TX) and Receive (RX) signals are sent through two 1.8V to 3.2V level shifters to convert the logic signal voltages to the correct values for the Sipex SP3232 RS‐232 transceiver. The CTS and RTS signals are not used on the Quick Start board. The RS‐232 transceiver receives its power from the external 3.2V LDO Regulator. If the output of the regulator is turned off for power savings measures, debug output will be lost. If the designer wishes to use the port as an Applications UART Port, changes can be made in software to reconfigure the port. A male‐to‐male gender changer can be used to properly convert the port. To access the debug data output during development, connect the Debug UART Connector to a suitable host computer and open a terminal emulation program (ie, Teraterm or HyperTerminal). Proper settings for the terminal program are:
• BAUD RATE: 115,200 • DATA: 8 bit • PARITY: None • STOP BIT: 1‐bit • FLOW CONTROL: None
3.15. JTAGConnector(J15) A standard 20‐pin ARM JTAG connector is provided on the Quick Start board. Logic signals to the JTAG connector are 1.8V signals. A 1.8V reference signal is provided to pin 1 of the connector so that the attached JTAG tool can automatically configure the logic signals for the right voltage. If the JTAG tool does not have an automatic logic voltage sense, make sure that the tool is configured for 1.8V logic. JTAG tools that have been specifically tested with the Quick Start board are:
• JTAG Commander (Macraigor) • DS‐5 and RealView (ARM Ltd.) • Trace32 (Lauterbach) • J‐Link (Segger/Codesourcery) • J‐Link (IAR)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 12
PUBI – Public Use Business Information
3.16. ExpansionHeader(J13) A 120‐pin Expansion Port Header is provided on the Quick Start board for use with many optionally expansion boards available from Freescale, or for custom designed boards made be the developer. At the time of initial production, the following expansion boards are available from Freescale:
• MCIMXHDMICARD HDMI signal output daughter card • MCIMX28LCD 4.3” WVGA Touch Panel LCD Display
The Expansion Port makes the following features of the i.MX53 Processor available to be used on a custom built expansion card:
• Two Serial Peripheral Interfaces (SPI) CSPI, eCSDPI2 • Two I2S/SSI/AC97 Ports AUDMUX4, AUDMUX5 • Two Inter‐Integrated Circuits (I2C) I2C1, I2C2 • 2 UARTs UART4, UART5 • SPDIF Audio • USB ULPI Port USBH2 • 24‐bit Data and display control signals • Resistive Touch Screen Interface • Various Voltage rails
3.17. UserInterfaceButtons There are four user interface buttons on the Quick Start board. Their functionality is as follows: POWER: In the ‘Power Off’ state, momentarily pressing the POWER button will begin the PMIC
power on cycle. The PMIC supplied voltage rails will come up in the proper sequence to power the i.MX53 Processor. When the processor is fully powered, the boot cycle will be initiated. In the ‘Power On’ state, momentarily pressing the POWER button will send a signal to a GPIO port for user defined action, but will not initiate a hardware shutdown. In the ‘Power On’ state, holding the power button down for greater than 5 seconds will result in the PMIC initiating a shutdown to the ‘Standby’ power condition. This will also be the result from the ‘Power Off’ state as the PMIC will transition into the ‘Power On’ state and will still see the POWER button as held down.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 13
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
RESET: Pressing the RESET button in the ‘Power On’ state will force the i.MX53 Applications
Processor to immediately turn off, and reinitiate a boot cycle from the Processor Power Off state. The RESET button has no effect on the PMIC or the voltage rails. Pressing the RESET button when the Quick Start board is powered off will have no effect.
USERDEF1: These two buttons are user defined buttons attached to PATA_DATA14 (P6) for USERDEF2: USERDEF1 and PATA_DATA15 (P5) for USERDEF2. The two GPIO pins are normally pulled
high by an internal resistor. The two buttons function by connecting the pins to ground, thus inserting a low signal. The developer is left to determine the actions of these two pins in code. Sample codes do not assign functionality to either pin.
3.18. UserInterfaceLEDIndicators There are eight LED status indicators located next to the microSD card connector. These LEDs have the following functions: 5V: The 5V status LED (D1) is a Green LED connected directly to the 5V_MAIN power rail.
This LED indicates that 5V wall power is being properly supplied to the Quick Start board. If this light is not lit, it would indicate one of three problems:
1) Fuse F1 has been blown and needs to be replaced. 2) Voltage from the wall supply is greater than 5.5V and the over voltage
protection feature is disabling power to the board. 3) The DC Power supply is not plugged in or malfunctioning.
PMIC: The PMIC status LED (D9) is a Green LED gated by the PMIC SYS_UP signal from the
PMIC. This LED indicates that the PMIC is in the fully on condition and supplying power to the processor and other voltage rails as directed by software.
USER: The User status LED (D16) is a Green LED gated by the PATA_DATA1 (L3) GPIO pin. The developer is left to determine the action of this pin in code. Sample codes do not assign functionality to the pin. The LED comes on by default when the processor starts up.
FLT: The FLT status LED (D14) is a Red LED gated by the NVDD_FAULT signal from the PMIC.
The LED will turn on anytime the PMIC is not outputting the requested voltages or when the PMIC senses a fault condition and will begin to power down the voltage rails. This may aid in trouble shooting power problems if both the PMIC and FLT LEDs are on at the same time, it indicates that the PMIC is causing a shutdown based on a fault it has sensed.
3.3V: The 3.3V status LED (D10) is a Blue LED gated by the External Regulator 3.2V power rail. This power rail can be turned off by software for power savings measures. This LED provides an easy visual recognition as to the status of this bus.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 14
PUBI – Public Use Business Information
SATA: The SATA status LED (D11) is a Blue LED gated by the SATA_1V3 (VLDO5) power rail.
This power rail can be turned off by software for power savings measures. This LED provides an easy visual recognition as to the status of this bus.
VGA: The VGA status LED (D12) is a Blue LED gated by the TVDAC_2V75 (VLDO7) power rail.
This power rail can be turned off by software for power savings measures. This LED provides an easy visual recognition as to the status of this bus.
LCD: The LCD status LED (D13) is a Blue LED gated by the LCD_3V2 power rail.
Normally the LCD_3V2 power rail receives power directly from the DCDC_3V2 power rail, but the LCD can also be configured to receive power from VIOHI_2V772 (VLDO4). In the alternate voltage supply configuration, this LED will provide visual recognition as to the status of the LCD bus.
3.19. OptionalLi‐IONBatteryConnector(J14) On the Quick Start board, there is a footprint (J14) available to solder a three pin wafer connector (Molex 0530470310 or equivalent). This connector will mate to Li‐ION batteries commercially available as replacement batteries to commonly available MP3 players. The developer should make sure that the polarity of the battery matches the polarity of the connector as replacement batteries may vary from different manufacturers. When installed, a battery can be charged from the external 5V wall power source. A battery will not be charged when only a USB cable is connected to the Quick Start board. When powering a board from only a battery, the 5V power rail and the DCDC_3V2 power rail will not be powered. Therefore, the Ethernet subsystem and Audio subsystem will not be operational under normal board configurations. Depending on the battery capacity, it may be necessary to power down additional subsystem voltage rails to extend battery life to a usable amount. The battery charging feature is an autonomous operation of the Dialog DA9053 PMIC that does not require software support. Battery charging may be prevented by software by making registry changes to the PMIC. The developer may need to verify in software that PMIC registry settings are proper for battery charging operations. The footprints for testing with a battery were included for skilled developers looking to experiment.
3.20. OptionalBack‐UpCoinCellposts(JP1,JP2) On the Quick Start board, there are two through‐holes (JP1 and JP2) next to the power connector. These through‐holes are positioned to hold a Lithium coin cell battery (Sanyo ML1220‐VM1 or equivalent). For proper operation, the coin cell posts should be soldered direction to the Quick Start board, with the positive terminal connected to JP1 and the negative terminal connected to JP2. The DA9053 PMIC will charge the coin cell when 5V Wall Power is available. When 5V Wall Power is removed, the coin cell will provide power only to the RTC power rail (VLDO1) supplying power to the i.MX53 processor. The length of time a coin cell can power the RTC subsystem may vary.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 15
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
3.21. PCBShortingTraces On the Quick Start PCB, there are 29 sets of standard footprints with a copper trace between them to short the two pads together. The PCB is produced with these pads unpopulated. These shorting traces are placed throughout the PCB at locations in line with major power rails and critical components. The purpose of these shorting traces it to allow the skilled developer to manually cut the trace between the pads to either: 1) Isolate power to major subsystems or components. 2) Install small value precision resistors to measure current consumption of major subsystems. 3) Or reconfigure power sources to subsystems or components using wires soldered to the pads. To restore a shorting trace back to normal after the trace is cut, it is only necessary to solder a Zero Ohm resistor to the pads.
4. QuickStartBoardConnectorsandExpansionPort The Quick Start board provides a number of connectors for a variety of inputs and outputs to and from the board. The following subsections describe these connections in detail.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 16
PUBI – Public Use Business Information
4.1. Wall5VPowerJack(J1) The 5V/2A AC‐to‐DC power supply that comes with the Quick Start board is plugged into the Power Jack (J1) on the board as show in Figure 1. If the original power supply is lost, it is possible to use a substitute power supply for the Quick Start board. Voltage above 5.5V, and below 12V, will trigger the Over‐Voltage protection circuitry on the board. It is not recommended to use a higher voltage since, in the event of a failure to the protection circuitry, damage to the board will result. A voltage supply above 12V will damage the PMIC part.
Figure 1. DC Power Jack
Power Jack (J1)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 17
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.2. RJ45EthernetConnector(J2B) A standard Cat‐V Ethernet cable is attached to the Quick Start board at the Ethernet/Dual USB connector J2. The connector contains integrated magnetic which allows the Ethernet IC to auto configure the port for the correct connection to either a switch or directly to a host PC on a peer‐to‐peer network. It is not necessary to use a crossover cable when connecting directly to another computer. The Ethernet/Dual USB connector is shown in Figure 2.
Figure 2a. Ethernet Port
Figure 2. RJ45 Ethernet Connector
Ethernet/Dual USB Connector (J2)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 18
PUBI – Public Use Business Information
4.3. VGADB15Connector(J8) To connect the Quick Start board to a computer monitor in the base configuration, a VGA cable is required. Connect the free end of the VGA cable to connector J8 to the point shown in Figure 3.
Figure 3. VGA Connector
VGA DB15 Connector (J8)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 19
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.4. DebugUARTDB9Connector(J16) To connect a host PC to the Quick Start board to receive Debugging information, a Null Modem serial cable is required. This cable is not supplied with the Quick Start kit. The male plug end of the serial cable is connected to the board at the point shown in Figure 4. The other end of the serial cable is connected to a PC. For newer generation computers that do not have a serial port, a USB‐to‐Serial cable can be used. There is no need for any special cabling to support debug information output.
Figure 4. Debug UART Connector
Debug UART DB9 Connector (J16)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 20
PUBI – Public Use Business Information
4.5. HeadphoneOutputConnector(J18) Any set of ear buds or head phones with a standard 3.5mm stereo jack can be connected to the Audio Output jack at the point shown in Figure 5. Ear buds are not supplied as part of the Quick Start kit.
Figure 5. Headphone Output Connector
Head Phone Connector (J18)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 21
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.6. MicrophoneInputConnector(J6) The Quick Start board provides a 3.5mm stereo connector for a microphone input. The microphone is not provided as part of the Quick Start kit. The developer has several choices as to the type of device plugged into this connector. A mono microphone will input its signal though the tip of the 3.5mm plug. The microphone bias is applied on the Quick Start board, therefore a microphone which uses a wire to send the bias signal to the actual condenser is not necessary, but will not interfere with the microphone operation. The Quick Start board can also be configured for use with a microphone/mono‐output ear bud commonly used on cellular phones. To have right channel sound output on this connector, it would be necessary for the developer to move the ferrite bead from the L25 pads and solder it to the L22 pads. This will remove the signal from the headphone output connector. The developer may also find it necessary to use a 2.5mm to 3.5mm adapter with most cellular microphone/earphone sets. As manufactured, the developer may also use a two plug headphone, microphone set commonly used for VOIP services on a PC. The microphone is connecter at the point shown in Figure 6.
Figure 6. Microphone Connector (J6)
Microphone Connector (J6)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 22
PUBI – Public Use Business Information
4.7. DualUSBHostJack(J2) The Quick Start board has two USB Host only connectors that can be used to support USB devices. The upper USB port is connected to the High‐speed (HS) USB 2.0 module of the i.MX53 processor and can support; 1) Any single, high‐power USB device, 2) Any combination of USB devices though a self‐powered hub not to exceed 500 mA current draw, or 3) Any combination of USB devices through a powered hub. The lower USB port is connected to the High‐speed (HS) USB 2.0 OTG module of the i.MX53 processor and is cross‐connected with the micro‐B USB device connector (J3). As long as the Quick Start board is not connected to a USB Host device through the micro‐B USB connector, the same combinations of USB devices can be used on the lower port as used on the upper port. The lower USB port requires configuration as a Host port in software, and is not available as a Host port during the initial boot sequence. USB cables can be inserted into the Dual USB connector at the point shown in Figure 7.
Figure 7a. USB Connectors Figure 7. Dual USB Host Connectors (J2)
Ethernet/Dual USB Connector (J2)
Upper
Lower
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 23
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.8. micro‐BUSBDeviceConnector(J3) The Quick Start board has one micro‐B USB device connector that can be used to connect the Quick Start board to a USB Host computer. The micro‐B connector is connected to the High‐speed (HS) USB 2.0 OTG module of the i.MX53 processor and is cross connected with the lower USB Host port on J2. When a 5V supply is seen on the micro‐B connector (from the USB Host), the i.MX53 processor will configure the OTG module for device mode, which will prevent the lower USB Host port from operating correctly. The 5V power provided by the attached USB Host is only used by the i.MX53 processor for sensing that the host is present. The Quick Start board will not draw power from the connected USB Host and will not operate without a 5V DC power source or charged Li‐ION battery. The micro‐B connector is keyed and will not accept a micro‐A plug from a cable. A micro‐B to USB‐A cable is supplied as part of the Quick Start kit and can be inserted into the micro‐B USB connector at the point shown in Figure 8.
Figure 8. micro‐B USB Device Connector (J3)
micro‐B USB Connector (J3)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 24
PUBI – Public Use Business Information
4.9. SATA7‐pinDataConnector(J7) A SATA 7‐pin Data connector (J7) is provided on the Quick Start Board and is connected to the SATA module of the i.MX53 processor. The Quick Start board is capable of communicating with any standard SATA device, such as a hard drive or optical DVD/CD reader. The SATA device, SATA cables and power supply for the SATA device are not provides as part of the Quick Start kit and are the responsibility of the developer. It is possible to initiate a boot from an attached SATA device. See the software reference manuals for instructions on how to configure the Quick Start board for SATA boot. The SATA Data cable is plugged into the Quick Start board at the location shown in Figure 9.
Figure 9. SATA Data Connector (J7)
SATA 7‐pin Data Connector (J7)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 25
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.10. SDCardConnector(J5) The Quick Start board has one full size SD/MMC connector that can be used for memory, or for third‐party SDIO type cards such as WiFi or Bluetooth. The SD Card Connector (J5) connects a full 8‐bit parallel data bus to the SD3 port of the i.MX53 processor. The SD Card Connector receives power from the DCDC_3V2 power rail supplied by the supplementary Voltage Regulator. The Quick Start board does not come pre‐configured to boot from the full size SD Card Connector, but the board can be modified to support booting from this connector instead of the microSD Card Connector. See the section on Quick Start boot options on how to make the necessary changes (Section 5.4.2). The SD Card Connector is not spring loaded, so pushing the card into the slot will not initiate an action to disengage the SD Card. The SD Card is inserted facing up at the location shown in Figure 10.
Figure 10. SD Card Connector (J5)
SD Card Connector (J5)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 26
PUBI – Public Use Business Information
4.11. microSDCardConnector(J4) The Quick Start board has one micro SD/MMC connector that can be used for memory. The micro SD Card Connector (J4) connects a 4‐bit parallel data bus to the SD1 port of the i.MX53 processor. The micro SD Card Connector receives power from the VLDO3 power rail. The Quick Start board comes configured to boot from the micro SD Card Connector by default. The micro SD Card Connector is spring loaded and will eject a properly inserted card if the card is pushed in again. Caution: If the card is ejected while serving as the file system, the processor will undergo a software crash. The micro SD Card is inserted facing up at the location shown in Figure 11.
Figure 11. microSD Card Connector (J4)
microSD Connector (J4)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 27
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
4.12. 20‐pinARMJTAGConnector(J15) The Quick Start board contains a standard 20‐pin ARM JTAG connector (J15) for advanced debugging with a third‐party emulator. The header is configured for use with 1.8V data signals. The developer should exercise caution when selecting the appropriate debugging tools. If an emulator set for 3.3V power and data is connected to the Quick Start board, the i.MX53 processor will be damaged. The emulator JTAG cable is connected to the bottom side of the Quick Start board at the location shown in Figure 12.
Figure 12. JTAG Connector (J15)
VGA DB15 Connector (J8)
JTAG Connector
(J15)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 28
PUBI – Public Use Business Information
4.13. LVDSConnector(J9) The Quick Start board includes a 30‐pin (Hirose, DF19G‐30P‐1H(56)) connector for use with an LVDS display. The developer can create custom cables that will allow the Quick Start board to be used with a wide variety of commercially available LVDS displays. The pin‐out for this connector is used on other Freescale designed boards in the i.MX53 series, such as the MCIMX53SMD tablet. Freescale has available a cable and LVDS display (HannStar, HSD100PXN1‐A00‐C11) for purchase if the developer wishes to use a pre‐tested configuration. The LVDS display can be used in conjunction with the optional LCD display, the VGA output or the optional HDMI card, as long as the total video output does not exceed the specified limits of the i.MX53 processor. The pin‐out table for the connector is located in different section of this user guide. This connector is located on the bottom side of the board in the location shown in Figure 13.
Figure 13. LDVS Connector (J9)
LDVS Connector
(J9)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 29
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5. QuickStartBoardArchitectureandDesign This section is designed to provide the developer detailed information about the electrical design and practical considerations that went into the Quick Start board. This section is organized to discuss each block in the following high level block diagram of the Quick Start board, as shown in Figure 14.
Figure 14. i.MX53 Smart‐Start Block Diagram
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 30
PUBI – Public Use Business Information
5.1. 5VPowerSupply 5V power from an external wall power supply is connected to the Quick Start board at connector J1. From the connector, the 5V supply is sent directly to a 3A over current protection fuse (F1). In between the connector and the fuse, there are two capacitors to bleed off voltage transients and a single trace that leads to the sense pin for the over‐voltage protection circuitry of the Dialog PMIC. From the protection fuse, the 5V supply is connected to the over‐voltage protection POWERFET Q1 which is controlled by the PMIC. This circuit limits to a very small area of the Quick Start board the physical location of where unprotected 5V power can reach. The 5V_MAIN power seen by the rest of the Quick Start board is protected from over‐voltage and over‐current. The circuit is shown below in Figure 15.
Figure 15. Board Main Power Circuit.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 31
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.2. DialogDA9053PMIC
The Dialog PMIC provides all regulated power to the Quick Start board with the exception of a supplemental 3.2V/1A voltage regulator. Physically, the PMIC is located in the upper right corner of the Quick Start board, as close to the power connector as possible, while still maintaining room for supporting components. From this location, power is supplied to the rest of the board. When 5V power is first attached to the Quick Start board, the PMIC will remain in an OFF state until the POWER button is pressed. In the OFF state, the PMIC will generate power on the VDDOUT rail at approximately 3.6V (different if Li‐ION battery attached) for use by the PMIC as a supply for all regulators. In addition, the PMIC generates a VDDCORE voltage of 2.5V for internal PMIC use, and to serve as a pull‐up source for the nONKEY/KEEPACT and nSHUTDOWN control inputs. This ensures that these two button are active whenever power is available to the Quick Start boar. When the POWER button is initially pressed, the PMIC senses the Active Low signal on the nONKEY pin and begins to power on all voltage rails in preprogrammed sequence. The sequence is determined primarily by the order in which power must be supplied to the i.MX53 processor. Once the core operations of the processor are fully powered, other power rails are turned on. The first voltage regulator to power on is always VLDO1. This regulator supplies a maximum of 40 mA current at 1.3V and powers on only the Secure RTC module of the i.MX53 Processor. This turns on the RTC Clock (32.768KHz) and Watch Dog features. In the event a System Reset is triggered, or the Quick Start board is placed into Standby, VLDO1 will remain powered ON. The only time that VLDO1 will turn off is if all power is removed from the Quick Start board, or if a software command is sent to the PMIC to turn off VLDO1. In the case that a developer attaches an optional coin cell to JP1/JP2, the coin cell will provide power to keep VLDO1 operating. The power sequence requirements for the i.MX53 Applications Processor from the data sheet are as follows:
1. NVCC_SRTC_POW (VLDO1) 2. VCC, VDDA, VDDGP, VDD_REG [in any order] 3. All other supplies [in any order]
NOTE: in case the internal regulator is used for VDDA generation, the VDD_REG should be powered up together with VCC and VDDGP, before the other supplies. In case the internal regulator is not used to generate VDDA (as on the Quick Start board), the VDD_REG is independent and has no power‐up restrictions. The power on timing sequence shown in Table 1 is the sequence programmed into the Dialog PMIC. It is one way of providing sequences power to the i.MX53 processor. Designers are free to change the power timing sequence on their own board designs as long as the timing requirements are met. Freescale has not formally tested other power on timing sequences.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 32
PUBI – Public Use Business Information
Regulator Time Slot VBUCKPRO 19 mSEC VBUCKPERI VLDO6 VLDO8 VLDO10
23 mSEC
VBUCKCORE 27 mSEC VBUCKMEM VBUCKPERI/SW VLDO2 VLDO5
31 mSEC
VLDO4 VLDO7
35 mSEC
VLDO3 VLDO9 DCDC_3V2
64 mSEC
Table 1. Regulator Timing Sequence The Dialog PMIC will enter a SHUTDOWN/STANDBY condition by one of three ways; By a command from the i.MX53 Processor via I2C communications, by i.MX53 Processor action to hold the nONKEY/KEEPACT pin low for at least five seconds, or by hardware if the user holds down the POWER button for more than five seconds. All three actions result in the Dialog PMIC powering down the voltage regulators in reverse order of the power on sequence, except for VLDO1. A subsequent press of the POWER button will initiate the same power on sequence as shown in Table 1. The various power rails supplied by the PMIC are discussed in the section on Quick Start Power Rails. Other features of the Dialog PMIC implemented by the Quick Start board are discussed in subsequent sub‐sections including: Li‐ION Battery Charging, Backlight LED Driver, Touch‐Screen Operation, Miscellaneous.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 33
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.2.1. QuickStartPowerRails Table 2 shows all the voltage supply rails used on the Quick Start board, their voltages and the major subsystems they supply on the board: Regulator Voltage Named Rails Powers VBUCKCORE 1.1V VBUCKCORE VDDGP VDDGP VBUCKPRO 1.3V VBUCKPRO VCC_1V3 VCC VBUCKMEM 1.5V VBUCKMEM DDR_1.5V
DDRQ_1.5V NVCC_EMI_DRAM DDR3 SDRAM
VBUCKMEM/SW 1.5V VMEM_SW DDR_1.5V (ALT) DDRQ_1.5V (ALT)
ALTERNATE FOR: DDR3 SDRAM LOGIC DDR3 SDRAM CORE
VBUCKPERI 2.5V VBUCKPERI VDD_REG_2V5 NVCC_XTAL_2V5 LVDS_2V5 (ALT) SATA_PHY_2V5 (ALT) VUSB_2V5 (ALT)
VDD_REG NVCC_XTAL ALTERNATE FOR: LVDS MODULE SATA MODULE USB MODULE 2.5V
VBUCKPERI/SW 2.5V VPERI_SW LVDS_2V5 SATA_PHY_2V5 VUSB_2V5
LVDS MODULE SATA MODULE USB MODULE 2.5V
BOOST Current Source VLCD_BLT EXPANSION PORT LCD BACKLIGHT SUPPLY
VLDO1 1.3V VLDO1_1V3_RTC NVCC_SRTC
NVCC_SRTC
VLDO2 1.3V DIG_PLL_1V3 ALTERNATE FOR: DIG_PLL
VLDO3 3.3V VLDO3_3V3 SD1_3V3 MICROSD CARD (SD1) I2C1/I2C2 BOOT_SEL NVCC‐EIM‐MAIN NVCC_EIM_SEC NVCC_SD1&2 NVCC_PATA NVCC_FEC NVCC_GPIO NVCC_KEYPAD
Table 2. Quick Start Board Power Supply Rails
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 34
PUBI – Public Use Business Information
VLDO4 2.775V VIOHI_2V775 LCD_3V2
(ALT) NVCC_LCD1 NVCC_LCD2 EXPANSION PORT (LCD)
VLDO5 1.3V VLDO5_1V3 SATA_1V3 SATA MODULE 1.3V VLDO6 1.3V VLDO6_1V3
VDDAL_1V3 VDDAL
VLDO7 2.75V VLDO7_2V75 TVDAC_2V75
VGA MODULE (TV DCA)
VLDO8 1.8V VLDO8_1V8 NVCC_RESET NVCC_JTAG NVCC_CKIH NVCC_NANDF NVCC_CSI VDD_ANA_PLL BOOT_SEL
VLDO9 1.5V VLDO9_1V5 EXPANSION PORT VLDO10 1.3V VLDO10_1V3
VDDA_1V3 VDDAL
DCDC‐3V2 3.2V DCDC‐3V2 AUDIO_3V2 FEC_3V2 VDD_FUSE LCD_3V2
ETHERNET AUDIO VGA_IO_SIGNALS USB 3.3V SD CARD (SD3) EXPANSION PORT
Table 2. Quick Start Board Power Supply Rails (con)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 35
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.2.2. Li‐IONBatteryCharging The Dialog PMIC contains a fully autonomous Li‐ION battery charger. When wall power is first applied to the Quick Start board, the PMIC will begin to apply a pre‐charge to the positive battery terminal. If the PMIC senses a fully discharged battery or a fault condition (eg, no battery), the PMIC will disconnect VDDOUT from the battery and allow the regulators to receive power independent what is attached to VBAT. The footprints for testing with a battery were included for skilled developers looking to experiment. As manufactured, the Quick Start board does not support Li_ION battery operations without modifications by the developer. If the PMIC senses the battery voltage above the BAT_FAULT threshold for 40 msec, the PMIC will then begin a fast linear charge of the Li‐ION battery by controlling the voltage on VDDOUT. If the PMIC is unable to increase VDDOUT above VBAT to continue charging the battery, the PMIC has an alternate current charging method using an active diode. Charging will continue until the battery voltage reaches the programmed level. The Li‐ION charging circuit also makes use of a temperature sensor (thermistor) attached to the body of the battery. If the resulting voltage measurement at TBAT falls outside the threshold value programmed into the registry settings, the PMIC will suspend the charging current until the battery temperature reduces back to with the threshold values. See the Dialog PMIC datasheet for a more detailed explanation. The PMIC is initially programmed with default settings to charge most Li‐ION batteries. These settings may be changed by software and the software documentation should be consulted for actually PMIC registry values. These values can be changed in software as the developer sees fit. For more detailed information on how the battery charging function works and how to change default charging parameters. Since the 5V power pin of the USB micro‐B connector is not connected to the PMIC, all discussion concerning battery charge current limits due to exceeding the USB standards do not apply to the Quick Start board. In designing a board using the Dialog PMIC, it is important to include a capacitor of 47 uF or greater attached to the VBAT pin if any operations are planned without a Li‐ION battery. If during the initial pre‐charge phase, the Dialog PMIC does not sense any voltage present when the pre‐charge voltage is momentarily removed and VBAT voltage is measured, the PMIC will assume a massive board failure and will not supply any voltage via the regulators.
5.2.3. BacklightLEDDriver The Dialog PMIC provides a Boost circuit which controls an external MOSFET Q8. The PMIC is capable of driving 3 independent strings of up to 5 white LEDs each with a voltage of approximately 24 Volts and a maximum of 50 mA. The Quick Start board does not have a direct connection for white backlight LEDs, but does supply one connection to the Expansion Port that can be used to support an attached LCD Daughter Card. The Expansion Port uses the LED1_IN port of the PMIC.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 36
PUBI – Public Use Business Information
When designing a circuit to use the Backlight LED driver, it is important to connect the cathode (negative) end of the LED string directly to the LED_IN port of the PMIC. The PMIC controls the supply voltage to the Backlight LEDs by ensuring that the voltage sensed on the LED_IN port is above a threshold voltage of 0.7V. If more than one LED_IN ports are used, the lowest port must be above the threshold value. If the designer connects the cathode end of the Backlight LED string to GROUND, the boost circuit will not work. The MOSFET used in the boost circuit should have a low ON Resistance value for best efficiency. The MOSTFET chosen for the Quick Start board, ON Semiconductor NTLJF4156NT1G, also contains a necessary diode used in the boost circuitry. This helps reduce the number of components.
5.2.4. Touch‐ScreenOperation The Dialog PMIC contains an autonomous Touch Screen Interface which will measure the XY positions from a standard 4‐WIRE resistive touch panel. The single ADC channel will detect the presence of a pen touch on the panel, and that will trigger a series of voltage measurements on each of the four touch panel wires (X+, X‐, Y+, Y‐) by the ADC in a pre‐selected sequence. The resulting voltage readings are then reported to the i.MX53 Applications Processor for conversion to a panel X‐Y position via the I2C communications link. To ensure the Touch Screen Interface wakes up autonomously with a pen stroke, it is necessary to supply a 1.8V reference voltage to the TSIREF_GPIO_7 pin of the PMIC. It is recommended that one of the high PSSR Regulators of the PMIC be used to supply this voltage. VLDO6 – VLDO9 are possible sources for supplying this reference voltage.
5.2.5. Miscellaneous If a coin cell battery is attached to the Quick Start board, it will automatically charge using the programmed charging settings whenever wall power is supplied to the Quick Start board. When the battery voltage reaches the programmed level, charging will stop. Battery discharge will not begin until wall power is removed from the board and, if a Li‐ION battery is attached, the main battery discharges to the battery cut off level. There are two port ID traces connected from the Expansion Port header to two of the ADC pins of the PMIC. Each unique Daughter Card designed by Freescale has a different resistor value attached to the two ID traces on the Daughter Card. It is possible to use this voltage divider identification system to determine at boot time if a daughter card is attached, and if so, which specific daughter card it is. Resistor values for the two daughter cards commonly used with the Quick start board are shown in Table 3.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 37
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
PORT_ID0 Measured Voltage PORT_ID1 Measured Voltage MCIMX28LCD 18.0K 1.61 V 130.0K 2.32 V MCIMXHDMICARD 2.74K 0.54 V 130.0K 2.32 V
Table 3. Port ID Resistor Values Over‐Voltage protection is sensed by the DCIN (B4) pin of the PMIC. The voltage sensed by this pin must be between 4.5V and 5.5V. If the voltage meets this threshold value, the voltage seen at DCIN is blocked from the DCIN_SEL (B3) pin and the P‐Channel MOSFET turns ON. Otherwise, DCIN_SEL remains high and power is blocked from the rest of the Quick Start Board. The TP (L5) pin of the PMIC must be connected to ground. When designing with a 0.5mm pitch uBGA package, there is limited space for vias and traces under the BGA. To assist with layout, Freescale has confirmed that all pins labeled ‘NO CONNECT’ on the PMIC are in no manner bonded out to the silicon. Therefore, for routing purposes, it is possible to route the trace from an interior pin through one or more ‘NO CONNECT’ pins, or to place a via directly under a ‘NO CONNECT’ pin without requiring a via‐in‐pad technique. If the CAD Layout Engineer decides to place a via under a ‘NO CONNECT’ pin, the via should not be tented as trapped gases during the assembly process may cause the solder ball from the ‘NO CONNECT’ pin to blow out into other pins and cause internal shorts under the BGA. The I2C communications channel between the Processor and the PMIC is Channel 1. This channel is only shared with the accelerometer. This channel operates at TTL logic level of 1.8V. The NRESET (F10) pin of the PMIC is directly connected to the Active Low POR_B (C19) pin of the i.MX Processor. The PMIC will hold the Processor in the RESET state until all the power rails are fully powered. The NIRQ (E10) pin of the PMIC is connected to the GPIO_ 16 (C6) pin of the Processor. This pin is not a dedicated pin for an interrupt request, but can be programmed in Software to inform the Processor that the PMIC has information to be given to the Processor. The PMIC has several different options for Pull‐Up levels on each of its output pins. In some cases, VDDOUT is one option, along with power supplied to both the VDD_IO1 (L4) and VDD_IO2 (K4) pins as Pull‐Up source. The exact source of Pull‐Up power is determined by the registry settings of the PMIC and can be pre‐programmed at the factory as the designer wishes. Some Pull‐Up registry settings apply to groups of pins, so care must be made in selecting which source power source is used for a particular grouping of pins. The Dialog PMIC Datasheet contains much more detailed information on the registry settings. For the Quick Start board, VLDO3 (3.3V) is connected to VDD_IO1 primarily to ensure that the 3V3_EN signal sent to the external regulator is sufficient to turn on the regulator, and VLDO8 (1.8V) is connected to VDD_IO2 to provide for proper I2C TTL logic levels.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 38
PUBI – Public Use Business Information
5.3. 3.2VSecondaryVoltageRegulator To provide power in excess of the Dialog PMIC’s capability, an external Voltage Regulator (Richtek, RT8010) is used. The regulator is adjustable and is set to 3.2V so that, in the event the processor may see two different sources for the required 3.3V power supply, the i.MX53 processor will preferentially draw from VLDO3_3V3. The regulator is controlled (enabled) from the PWR_UP_GP_FB2 (J10) pin of the Dialog PMIC. This is the only GPIO pin that can be programmed to turn on during the voltage timing sequence of the Dialog PMIC and is timed to turn on at the same time VLDO3_3V3 comes on. The internal pull‐up power source for this GPIO is programmed to be from VDD_IO1 (VLDO3_3V3) which is the same voltage source for the Dialog RTC system. Since the i.MX53 standby power system is operated at 1.3V, this prevented using the Dialog RTC system as an input to the i.MX53 processor. If the developer does not want to enable the external voltage regulator from the Dialog GPIO pin, it would be possible to reconfigure VDD_IO1 to be 1.3V and use the Dialog RTC clock instead. This is a design choice for the developer. The external voltage regulator supplies power to the following general board areas and is expected to supply up to the maximum specified currents as follows:
i.MX53 USB Phy 10 mA VGA Connector Output 10 mA Audio 10 mA Debug UART 60 mA Ethernet 100 mA Expansion Port (HDMI) 30 mA SD Card 60 mA
For the Expansion Port and the SD Card socket, it may be that the current draws exceed the above estimates if a custom designed board is added to the Expansion Port, or if an SDIO device is plugged into the SD Card Socket (ie, WiFi, Bluetooth). The external voltage regulator is capable of supplying up to 1A of current and should be capable of accommodating most custom configurations. Since the Quick Start board was originally designed, it has been found that VDDA, VDDAL, and DIG_PLL can all be powered internally by the i.MX53 processor (with the correct eFuse settings). This would then free the PMIC VLDO2, VLDO6 and VLDO10 power sources for other uses. VLDO6 and VLDO10 will be able to supply the above expected loads, provided a high current draw SDIO card is not inserted in the SD Card Socket. The designer is free to rearrange power rails as desired.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 39
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.4. i.MX53ApplicationsProcessor The i.MX53 Applications Processor is physically located in the central portion of the Quick Start board. The most critical components for placement after the processor are the DDR3 SDRAM ICs. The remainder of the components and connectors are arranged around the periphery of the board in locations that minimize trace routing. The i.MX53 Processor is a highly integrated system‐on‐chips with many modules controlled by the main Arm Cortex‐A8 core. Most modules have Logic Voltage inputs which allow the designer to modify logic levels to suit the needs of connected ICs. A more detailed explanation of these Logic Voltage Inputs is presented in the Peripheral Module Logic Voltage Levels subsection. The information for voltage levels and other chip specific details come from the I.MX53 Data Sheet, which may be revised from time to time. In the event that the most recent data sheet and the User Guide do not agree, the Data Sheet should always take precedence. Every effort will be made to keep the User Guide current to the most recent Data Sheet. The i.MX53 Processor initializes out of reset according to its preprogrammed ROM code. After initial wakeup, it then attempts to read the logic levels on 26 different pins. Depending which pins are high/low, the Processor will then select one of the allowed boot options to begin the boot process. This is further explained in the subsection on Boot Mode Operations and Selections. The clock signals required by the i.MX53 Processor and the rest of the Quick Start board are further explained in the section on Clock Signals. The i.MX53 Processor has the ability to supply a limited amount of filtered power for internal purposes using an internal voltage regulator. The operation of this regulator is explained further in the i.MX53 Internal Regulator subsection. The Processor also has an internal Watch Dog Timer (WDOG) circuit that can be used to reset the Processor in the event it stops functioning correctly. The supporting circuitry is explained in further detail in the subsection titled Watch Dog Time.
5.4.1. PeripheralModuleLogicVoltageLevels By convention, pins used on the I.MX53 Processor to set module logic voltage levels begin with NVCC_. This is to aid the developer in the design of a project based on the i.MX53 Processor. There are 25 such pins used, and practically speaking, they supply the internal pull‐up voltages for pins designated for data output. These 25 pins are shown in detail in Table 4. Module Voltage Supplies. Once a voltage level is selected for a particular module, all pins within that module will use the same voltage level. It is important for the developer not to try to use an external pull‐up to a different voltage level for individual pins. Level shifters must be used if certain pins need to have different voltage levels to interface with external ICs. If a different voltage level is used on an external pull‐up, one or both of the affected power rails will most likely have a different voltage level than intended throughout the design. On a newly designed board that shows unexpected voltage levels, this may be the first thing to check. On the Quick Start board, there are a number of unpopulated pull‐up resistors. This is a result of the initial design being conservative, and the addition of external pull‐up resistors to supplement internal i.MX53 pull‐up supply voltage. Subsequent Quick Start board usage has shown these pull‐ups to be unnecessary, so they are unpopulated.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 40
PUBI – Public Use Business Information
Module Allowed Values Quick Start board NVCC_EMI_DRAM_1 NVCC_EMI_DRAM_2 NVCC_EMI_DRAM_3 NVCC_EMI_DRAM_4 NVCC_EMI_DRAM_5
External Memory Interface 1.425V ‐ 1.9V 1.5V (Match DDR3 Memory)
NVCC_NANDF NAND Flash 1.65V ‐ 3.6V 1.8V NVCC_EIM_MAIN_1 NVCC_EIM_MAIN_2 NVCC_EIM_SEC
External Interface Module 1.65V ‐ 3.6V 3.3V
NVCC_RESET Reset Logic Levels 1.65V ‐ 3.1V 1.8V (Match PMIC) NVCC_SD1 SD Card Module 1 1.65V ‐ 3.6V 3.3V (Match SD Cards) NVCC_SD2 SD Card Module 2 1.65V ‐ 3.6V 3.3V NVCC_PATA Parallel ATA 1.65V ‐ 3.6V 3.3V NVCC_LCD_1 NVCC_LCD_2
LCD Module 1.65V ‐ 3.1V 2.775V
NVCC_CSI Camera Sensor Interface 1.65V ‐ 3.6V 1.8V NVCC_FEC Fast Ethernet Controller 1.65V ‐ 3.6V 3.3V (Match Ethernet PHY) NVCC_GPIO General Purpose I/O 1.65V ‐ 3.6V 3.3V NVCC_JTAG JTAG Module 1.65V ‐ 3.1V 1.8V NVCC_KEYPAD Keypad Port 1.65V ‐ 3.6V 3.3V (Match Audio CODEC) NVCC_CKIH Clock Amplifier Circuit 1.65V ‐ 1.95V 1.8V NVCC_XTAL 24MHz Crystal Supply 2.25V ‐ 2.75V 2.5V NVCC_SRTC_POW Secure Real Time Clock 1.1V ‐ 1.3V 1.3V NVCC_LVDS Low Voltage Differential Signaling 2.375V ‐ 2.625V 2.5V NVCC_LVDS_BG LVDS Band Gap 2.375V ‐ 2.625V 2.5V
Table 4. Module Voltage Supplies
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 41
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.4.2. BootModeOperationsandSelections The i.MX53 Applications Processor can be directed to boot from the logic levels on 24 different pins designated for boot mode configurations, or it can be directed to boot from internal eFUSE settings, or it can be directed to boot from a serial downloader (USB/UART). The method used to determine where the Processor finds its boot information is from two dedicated BOOT_MODE pins. Table 5 shows the values used of each of these methods. It is important for the developer to remember that these two pins are tied to the NVCC_RESET modules, and therefore, on the Quick Start board, use a 1.8V logic level (unlike the Boot Configuration pins which use a 3.3V logic level). The default boot selection for the Quick Start board is 00 – Boot from hardware settings. Since it is not expected that developers will want to burn eFUSES on the Quick Start board, the two BOOT_MODE pins are tied together through one switch position of the optional DIP Switch (SW1). If the developer wishes to populate SW1, the position 10 switch can be moved to ON so that the BOOT_MODE pins are both pulled high. Then the developer will be able to use the serial downloader method of loading bootable code into the Processor.
BOOT_MODE1 BOOT_MODE0 Boot Source 0 0 Determined By Board Hardware 0 1 Reserved 1 0 Determined By eFUSE Settings 1 1 Use Serial Downloader
Table 5. BOOT_MODE pin Settings
If the method of determining the bootable source code is selected to be from hardware, then 21 i.MX53 pins are sampled at the beginning of the boot process. These 21 pins are shown in Tables 6A – 6C along with their default setting on the Quick Start Board. Note that three bits in the BOO_CFG words do not have corresponding pins to read. BOOT_
CFG1[7] BOOT_ CFG1[6]
BOOT_ CFG1[5]
BOOT_ CFG1[4]
BOOT_ CFG1[3]
BOOT_ CFG1[2]
BOOT_ CFG1[1]
BOOT_ CFG1[0]
PIN EIM_A22 EIM_A21 EIM_A20 EIM_A19 EIM_A18 EIM_A17 EIM_A16 EIM_LBA Default 0 1 0 0 0 0 0 1
Table 6A. BOOT_CFG Word1 BOOT_
CFG2[7] BOOT_ CFG2[6]
BOOT_ CFG2[5]
BOOT_ CFG2[4]
BOOT_ CFG2[3]
BOOT_ CFG2[2]
BOOT_ CFG2[1]
BOOT_ CFG2[0]
PIN EIM_EB0 EIM_EB1 EIM_DA0 EIM_DA1 EIM_DA2 EIM_DA3 N/A N/A Default 0 0 1 1 1 0 ‐ ‐
Table 6B. BOOT_CFG Word2
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 42
PUBI – Public Use Business Information
BOOT_
CFG3[7] BOOT_ CFG3[6]
BOOT_ CFG3[5]
BOOT_ CFG3[4]
BOOT_ CFG3[3]
BOOT_ CFG3[2]
BOOT_ CFG3[1]
BOOT_ CFG3[0]
PIN EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_DA10 N/A Default 0 0 0 0 0 0 0 ‐
Table 6C. BOOT_CFG Word3 Of these 21 pins, four of them have the same meaning regardless of the selected boot source. These four BOOT_CFG bits with their meanings are as follows: BOOT_CFG1[1] Processor Speed setting during boot: 0 – 800 MHz 1 – 400 MHz BOOT_CFG1[0] MMU Enabled during boot: 0 – MMU not enabled 1 – Initializing MMU with L1 Cache during boot BOOT_CFG2[3] AXI/DDR Speed setting during boot: 0 – PLL2: 400MHz 1 – PLL2: 333MHz BOOT_CFG2[2] Oscillator Frequency Select: 0 – Auto Detect 1 – Set to 24MHz The six pins that determine where bootable code is stored are BOOT_CFG1[7:2]. Depending on which boot source is selected, some of these pins may have different meanings. Those pins will show up as an ‘X’ for logic level. The specific logic levels and their meanings are as follows: BOOT_CFG1[7:2] Boot Code Source Selection 0000 ‐ NOR/OneNAND Boot 0001 ‐ Reserved 0010 ‐ PATA/SATA Boot 0011 ‐ Serial ROM (I2C/SPI) Boot 01XX ‐ SD/MMC (eSD/eMMC) Boot 1XXX ‐ NAND Flash Boot For each of the bootable source selections, the remaining BOOT_CFG pins have different meanings. The pins are meant to choose initialization settings required for each specific boot source. The following paragraphs will specify those choices base by bootable source:
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 43
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
NOR/OneNAND BOOT_CFG1[3] Memory Type 0 – NOR Flash 1 – OneNAND BOOT_CFG2[7:6] Muxing Scheme 00 – Muxed, 16‐bit data (low half) interface 01 – Not muxed, 16‐bit data (high half) interface
10 – Reserved 11 – Reserved
BOOT_CFG3[7:6] OneNAND Page Size 00 – 1KB 01 – 2KB 10 – 4KB 11 – Reserved HD (PATA/SATA) BOOT_CFG1[3] HD Type 0 – PATA 1 – SATA Serial‐ROM BOOT_CFG1[3] Serial ROM Select 0 – I2C 1 – SPI BOOT_CFG2[5] SPI Addressing 0 – 2‐byte (16‐bit) 1 – 3‐byte (24‐bit) BOOT_CFG3[5:4] Port Select 00 – I2C1/eCSPI1 01 – I2C2/eCSPI2 10 – I2C3/CSPI 11 – Reserved BOOT_CFG3[3:2] Chip Select (SPI Only) 00 – CS0 01 – CS1 10 – CS2 11 – CS3
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 44
PUBI – Public Use Business Information
SD/eSD BOOT_CFG1[4] Fast Boot 0 – Regular 1 – Fast Boot BOOT_CFG1[3] SD/MMC Speed 0 – High 1 – Normal BOOT_CFG2[5] Bus Width 0 – 1‐bit 1 – 4‐bit BOOT_CFG3[5:4] Port Select 00 – eSDHC1 01 – eSDHC2 10 – eSDHC3 11 – eSDHC4 MMC/eMMC BOOT_CFG1[4] Fast Boot 0 – Regular Boot 1 – Fast Boot BOOT_CFG1[3] SD/MMC Speed 0 – High 1 – Normal BOOT_CFG2[7:5] Bus Width 000 – 1‐bit 001 – 4‐bit 010 – 8‐bit 011 – Reserved 100 – Reserved 101 – 4‐bit DDR (MMC 4.4) 110 – 8‐bit DDR (MMC 4.4) 111 – Reserved BOOT_CFG3[5:4] Port Select 00 – eSDHC1 01 – eSDHC2 10 – eSDHC3 (eMMC4.4) 11 – eSDHC4 BOOT_CFG3[3] DLL Override 0 – Use Default ROM 1 – Use eFUSE DLL Override BOOT_CFG3[2] Fast Boot Acknowledge 0 – Enabled 1 – Disabled
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 45
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
NAND BOOT_CFG1[6] Muxed On: 0 – PATA 1 – WEIM BOOT_CFG1[5:4] Interleave Scheme: 00 – No Interleaving 01 – 2 Device 10 – 4 Device 11 – Reserved BOOT_CFG1[3:2] Address Cycles: 00 – 3 01 – 4 10 – 5 11 – 6 BOOT_CFG2[7:6] Page Size: 00 – 512 + 16 Bytes (4‐bit ECC) 01 – 2KB + 64 Bytes 10 – 4KB + 128 Bytes 11 – 4KB + 218 Bytes BOOT_CFG2[5] NAND Interface 0 – 8‐bit 1 – 16‐bit BOOT_CFG2[2] NAND Flash Clock Frequency 0 – AXI DDR Frequency divide by 12 1 – AXI DDR Frequency divide by 28 BOOT_CFG3[7] Bad Block Skip Step (Stride Size) 0 – 1 Block 1 – 8 Block BOOT_CFG3[6] LBA‐NAND Select 0 – Non LBA (11ms delay) 1 – LBA (22ms delay) BOOT_CFG3[5] NAND use R/nB Signals? 0 – No 1 – Yes BOOT_CFG3[4:3] ECC/Spare Select 00 – 8‐bit ECC 01 – 14‐bit ECC 10 – 16‐bit ECC 11 – ECC Off BOOT_CFG3[2:1] Pages in Block 00 – 32 Pages 01 – 64 Pages 10 – 128 Pages 11 – 256 Pages
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 46
PUBI – Public Use Business Information
When the Quick Start board was originally designed, several of the BOOT_CFG pins were selectable by the 10 position DIP Switch (SW1). After initial testing of the Quick Start board, the optimum BOOT_CFG settings for flexibility and ease of use were determined. These are the default settings on the board, which set the microSD card connector (SD1) as the default boot source. As the developer becomes more familiar with the board and wishes to experiment more, it is recommended that the next step for the developer is to write code for the microSD card to initialize as alternative boot source and pass off the boot process to the new source. As further experience is gained, the developer may wish to install the optional DIP switch on SW1 (Multicomp MCNHDS‐10‐T). The boot‐switch was originally removed to improve ease of use and ensure all members of the community are developing the same way. Installing the boot‐switch will allow the developer to gain access to selecting either SD card socket as the bootable source, or to select the serial downloader method. Finally, for the skilled developers, it is possible to desolder and rearrange some of the pull‐up and pull‐down resistors on the Quick Start board. Figures 16 and 17 highlight all of the pull‐up and pull‐down resistors used, and also highlights sources of either high (3.3V) or low (GND) logic levels.
Figure 16. Boot Mode Resistor Locations TOP
Table 7. Boot Mode Resistors TOP
Resistor Boot Configuration Bit Pull UP/Down R46 BOOT_CGF1[6] Pull Up R47 BOOT_CGF1[7] Pull Down R48 BOOT_CGF2[7] Pull Up (DNP)
R46
R47R48
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 47
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 17. Boot Mode Resistor Locations BOTTOM
Table 8. Boot Mode Resistors BOTTOM
Resistor Boot Configuration Bit Pull UP/Down R56 BOOT_CGF1[1] Pull Down R62 BOOT_CGF2[3] Pull Up R64 BOOT_CGF3[4] Pull Down R65 BOOT_CGF3[3] Pull Down R57 BOOT_CGF1[0] Pull Up R60 BOOT_CGF2[5] Pull Up R61 BOOT_CGF2[4] Pull Up R59 BOOT_CGF2[6] Pull Down
R65R64
R62
R59R61
R60R57
R56
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 48
PUBI – Public Use Business Information
5.4.3. ClockSignals
The Quick Start board has three external clocks, two of which are dedicated to the i.MX53 Processor, and one dedicated to the Ethernet PHY. The 24 MHz crystal (Y1) is the main clock source for the Processor. The crystal is located on the bottom side of the board as shown in Figure 18. It is driven by its own 2.5V supply pin, NVCC_XTAL. Although the crystal frequency for the board is set to be 24MHz, the default BOOT_CFG2[2] pin that controls specifying the frequency is left to auto detect. In the case of 24MHz, the actual setting is not important. If a clock oscillator is used, it would be connected to the pin EXTAL (AB11) and the pin XTAL (AC11) should be left floating. The 24 MHz clock signal can be output from any GPIO pin for use in other locations. On the Quick Start board, the clock signal is output on GPIO_0 and is the net is labeled GPIO_0(CLK0). The clock signal is sent to the Audio Codec as the clock source for the audio sub‐system, and it is also sent to the expansion port as an available clock signal for a custom designed card as needed. The 32.768KHz crystal (QZ1) is the clock source used by the i.MX53 Processor for the Secure Real Time Clock module. It receives power from the NVCC_SRTC pin which is connected to the VLDO1 1.3V voltage regulator. The 32.768KHz clock signal is not sent anywhere else on the Quick Start board. The location of the crystal is also shown in Figure 18.
Figure 18. Clock Source Locations The clock source for the Ethernet PHY is a 50 MHz Oscillator (X1) with an enable pin and is shown in Figure 18. The oscillator was originally placed to support both the SATA module and the Ethernet PHY. It is no longer used for the SATA module, and only supplies a clock signal to the Ethernet PHY. It is powered by the DCDC_3V2 power rail and, by default, is always on when the DCDC_3V2 rail is powered on. It is possible for the developer to remove resistor R110 and place a zero Ohm resistor across R197 to give the developer software control of the oscillator through pin GPIO_4 (D4).
Y1
QZ1
X1
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 49
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.4.4. i.MX53InternalRegulatorsThe i.MX53 Applications Processor contains two internal voltage regulators which can supply VDDA, VDDAL, VDD_DIG_PLL and VDD_ANA_PLL. The power input for this pin is VDD_REG (pin G18). On the Quick Start board, this pin is connected to VBUCKPERI and is set to 2.5V. The Digital PLL voltage regulator can be selected to supply VDD_DIG_PLL through an internal (on die) connection. The VDD_DIG_PLL pin can also be connected to the VDDA and VDDAL pins through an external connection to allow the Digital PLL regulator to supply these rails as well. The Digital PLL regulator is set to start at a reduced voltage value of 1.2V, but is programmed by software to increase to 1.3V early in the boot process. On the Quick Start board, the VDD_DIG_PLL connection to VLDO2 is not populated by default, so that VDD_DIG_PLL power is supplied by the internal regulator. The VDDA supply pins are connected to VLDO10 through a shorting trace SH22. If the developer wishes to experiment with supplying VDDA from the internal regulator, the trace between the two pads of SH22 can be cut, and a wire soldered between SH22 pin 2 and resistor R210 pin 2. The VDDAL supply pin is connected to VLDO6 through a shorting trace SH24. If the developer wishes to experiment with supplying VDDAL from the internal regulator, the trace between the two pads of SH24 can be cut, and a wire soldered between SH24 pin 2 and resistor R210 pin 2. The Analog PLL voltage regulator can be selected to supply VDD_ANA_PLL through an internal (on die) connection. The Analog PLL is set to supply a voltage of 1.8V. On the Quick Start board, the VDD_ANA_PLL connection to VLDO8 is not populated by default, so that VDD_ANA_PLL is supply by the internal regulator. Developer Note: During the boot process, it takes approximately 310msec for VDD_DIG_PLL to change from 1.2V to 1.3V. During this time, the i.MX53 core will not run at full speed/maximum processor loading. It will operate in the reduced power mode, and the limitations of the reduced power mode discussed in the datasheet apply. It is expected that during the first 310msec, processor loading will not be an issue.
5.4.5. WatchDogTimer The i.MX53 Application Processor has an internal Watch Dog Timer circuit. On the Quick Start board, the WDOG output is assigned to GPIO_9. The WDOG is an active low signal. The Dialog PMIC does not have a specific pin to accept a Watch Dog signal to force a Processor reset. Therefore, the WDOG signal is modified by hardware components on the Quick Start board and applied to the Processor Reset pin (POR_B, pin C19). By using an active‐low enabled buffer, the active low WDOG signal can be transformed into a low pulse, which returns back to the logic high state immediately after the i.MX53 Processor resets ( ~ 700 nsec). This allows the processor to reset the WDOG signal and then come out of reset. The buffer IC also is in a tri‐state condition when the WDOG signal is normally high, thus allowing the push‐button reset circuitry to work. The Watch Dog circuitry is shown in Figure 19.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 50
PUBI – Public Use Business Information
Figure 19. Watch Dog Timer Reset Trigger In normal operation, WDT_OUTPUT is high, which keeps WDT_OUT_FLT high and the buffer in the OFF state. As soon as the WDOG goes active low, WDT_OUT_FLT is pulled low through C253, and the buffer (U22) is enabled. The always low input to the buffer is then sent to the POR_B pin and forces the Processor into reset. The RC circuit formed by R215 and C253 will then begin to raise the voltage level on WDT_OUT_FLT, until after XX msec, the active low output enable pin of U22 will turn off the Buffer and POR_B will return high. In coming out of reset, the WDOG will then return to the HIGH or OFF state, and the Processor will return to normal operations.
5.4.6. WakeupAfterUserInitiatedStandby Q13 is a dual P‐channel/N‐channel MOSFET designed to take a transition from a low state to a high state on PMIC_ON_REQ (pin W15) and turn it into a PMIC nONKEY request to bring the Dialog DA9053 chip out of a standby state to a fully on state. The PMIC_ON_REQ pin has been designed to work with the Freescale companion PMIC chip and is always in a high state even if the user forces the board into standby with the nONKEY. To configure the wakeup after user initiated standby feature, the user first has to program the software to transition the PMIC_ON_REQ to the low state after a start up or resume after standby operation. This will place the circuit in a correct configuration to request a startup from the standby state. Without this software change, pressing the nONKEY after a forced standby will not wake the board back up out of sleep. To keep the board operating correctly before this software modification is made, Q13 has not been populated on the board. When the developer has modified code to make this work, Q13 can be populated to complete the circuit. Information on Q13 can be found in section 14, Bill of Materials.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 51
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.5. DDR3SDRAMMemory The Quick Start board has four 128MX16 DDR3 SDRAM chips for a total of 1GB RAM memory. The chips are organized in two different arrays, differentiated by the chip selects, storing either the upper 16‐bits or the lower 16‐bits of a 32‐bit word. This organization is shown in Table 9 below.
Chip Select ‘0’ Chip Select ‘1’ Lower 16‐bits [15:0] U3 U4 Upper 16‐bits [31:16] U5 U6
Table 9. DDR3 SDRAM Chip Organization In this organization, there are 21 traces that connect to all four DDR3 chips and the i.MX53 Processor (14 Address, 3 Bank Address, 3 Control, and Reset). These are the most critical traces since they will see the most loading. The remaining traces are connected to two DDR3 chips and the Processor, and will only see one active DDR3 chip at a time. Note that the two clock traces are tied with the data traces (SDCLK_0 for the lower 16‐bits, SDCLK_1 for the upper 16‐bits). This limits the clock traces to only one active DDR3 chip at a time as well. In the physical layout, the DDR3 chips are placed to minimize routing of the address traces. The two chip select ‘0’ chips are placed on top, and the two chip select ‘1’ chips are placed on the bottom side, directly below the chips with the same data traces. The data traces are not necessarily connected to the DDR3 chips in sequential order, but for ease of routing, are connected as best determined by the layout and other critical traces. The i.MX53 Processor has the capability of remapping SDRAM word bit order based on chip select used, so that words can be physically stored in memory in correct order. If this is a feature the developer wishes to implement, there is more information in the software reference manual. The DDR_VREF is created by a simple voltage divider using 470 Ohm 1% resistors and 0.1 uF capacitors for stability. The relatively small value resistors provide enough current to maintain a steady mid‐point voltage. The calibration resistors used by the four DDR3 chips and the Processor are 240 Ohm 1% resistors. This resistor value is specified by the DDR3 Specifications. There is a 200 Ohm resistor between each clock differential pair to maintain the correct impedance between the two traces. The DDR3 SDRAM should be rated for 1066 MHz or faster. For skilled designers wishing to double the amount of DDR3 SDRAM available for use with the i.MX53 processor using eight x8 width DDR3 chips, the following considerations should be weighed carefully before proceeding: Four DDR3 chips on a chip select line will exceed the current supply capability of the VBUCKMEM power source. An additional 1.5V power source would need to be added. Also, attaching the address lines to eight DDR3 chips is a great amount of loading. Premium PCB materials would be required to reduce losses. Freescale has tested and validated using eight DDR2 SDRAM chips in this manner. Using eight DDR3 SDRAM chips has not yet been tried.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 52
PUBI – Public Use Business Information
Developers should note that using different configurations of SDRAM requires register changes on the i.MX53 Processor to ensure that timing and address sequencing is set up correctly. Software initialization settings will be different depending on SDRAM configuration.
5.6. MicroSDCardConnector The microSD Card Connector (J4) is directly connected to the eSDHC channel 1 module of the i.MX53 Applications processor. This card socket will support up to a 4‐bit data transfer from an microSD card or a microMMC card inserted into the socket. The Quick Start board is designed to boot a microSD Card from the microSD card socket with no additional modifications. If the developer wishes to boot from a microMMC card, the following options shown in Table 10 below are available: Option Net Condition Notes: SD Card Operations EIM_A20 Default Low Position 8 on DIP Switch SW1 MMC Card Operations EIM_A20 Pull High Position 8 on DIP Switch SW1
Table 10. Micro‐SD Card Boot Options The main power for the microSD Card Socket is 3.3V from (VLDO3_3V3). This ensures that if the external voltage regulator is turned off for power savings, the microSD Card Socket still has power. Power to the card socket is through SH1. If the developer wants to supply power from a different power source, this trace can be cut. The developer should note that the internal i.MX53 processor eSDHC module is powered by a 3V3 source, so changing the voltage of the cards socket on the Quick Start board is not recommended. The SD1 Clock trace has a 22 Ohm series termination resistor (R211). This resistor is inserted to prevent a reflected signal from being sensed by the i.M53 processor. This has been found to occur on MMC card operation and is recommended for all designs. In addition, the following eSDHC channel 1 trace is pulled high to 3.3V (VLDO2_3V3).
SD3 Command (R76) By default, the Quick Start board is manufactured with a 3M 29‐08‐05WB‐MG part for availability reasons. The combined Data3/Card Detect trace is not supported by the BSP software. It is possible for the developer to remove the original card socket and repopulate the position with an alternate microSD Card Socket made by Proconn, MSPN09‐A0‐2000. The developer should also then populate R108 with a suitable pull‐up resistor (10K). This will then give the developer the option to use the card detect trace for channel 1 connected to EIM_DA13 (pin AC7).
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 53
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.7. FullSizeSDCardConnector The full size SD Card connector (J5) is directly connected to the eSDHC channel 3 module of the i.MX53 Applications processor. This card socket will support up to a full 8‐bit data transfer from an SD card, SDIO device, or MMC card inserted into the socket. The Quick Start board was designed by default not to boot from the J5 card socket. If the developer wishes to boot from J5, the following options shown in Table 11 below are available: Option Net Condition Notes: Boot From J5 Card Socket EIM_DA6 Pull High Position 2 on DIP Switch SW1 High Speed Operations EIM_A18 Pull High Position 6 on DIP Switch SW1 Fast Boot EIM_A19 Pull High Position 7 on DIP Switch SW1 SD Card Operations EIM_A20 Default Low Position 8 on DIP Switch SW1 MMC Card Operations EIM_A20 Pull High Position 8 on DIP Switch SW1
Table 11. Full Size SD Card Boot Options The Quick Start board is configured to have the ROM code try to initiate boot operations in the 4‐bit data mode, by setting BOOT_CFG[6:5] to (01). Section 6.4.3.6 explains the SD/MMC boot options in greater detail for the interested developer. Main power to the SD Card Connector is from the external LDO regulator (DCDC_3V2). If this regulator is turned off for power savings purposes, the card socket will not function. It is possible for the developer to cut the trace between the pads of SH32 and attach a different source of power to the pad next to the card socket via a wire solder. Note that the eSDHC module internal to the i.MX53 processor is operating at 3.3V, therefore it is recommended that the alternate source also be 3.3V. Cutting the SH32 trace should only be used if a SDIO device inserted into the socket is drawing more power than the LDO Regulator is capable of supplying. The SD3 Clock trace has a 22 Ohm series termination resistor (R212). This resistor is inserted to prevent a reflected signal from being sensed by the i.M53 processor. This has been found to occur on MMC card operation and is recommended for all designs. In addition, the following eSDHC channel 3 traces are pulled high to 3.2V (DCDC_3V2).
SD3 Command (R89) SD3 Card Detect (R88) SD3 Write Protect (R87)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 54
PUBI – Public Use Business Information
5.8. VGAVideoOutput The i.MX53 Applications Processor TV Encoder module provides three component video output signals that can be used as either a TV signal or as a VGA signal to a connected monitor. The Quick Start board configures these signals for use as a VGA output through connector J8. In addition to the 3 video signals, Horizontal and Vertical Synchronization signals, I2C Data and Clock and a 5V reference signal are connected to the VGA output in accordance with the VGA Video Standard. The video data signals are referenced to 2.75V (TVDAC_2V75), while all other signals are referenced to 5V. The synchronization signals leave the i.MX53 Processor referenced to 3.3V, but go through a pair of one‐way level shifters (U12, U13) to meet the VGA standard required 5V reference. Similarly, the I2C Channel two signals leave the processor referenced to 3.2V, but go through a bi‐directional level shifter (U14) to also become referenced to 5V. See the connector section for the actual pin‐out of J8. The Component Video signals are terminated to ground, each with a 75 Ohm resistor to meet cabling requirements. A separate VGA ground plane has been created to minimize noise on the video signals by necking through a small trace. The voltage reference signal for the TVDAC module is provided by placing a 1.05K 1% Ohm resistor at pin Y18. The constant current source provided by the TVDAC module generates the exact voltage reference required by the VGA standard. A 0.1uF capacitor should be connected to pin AA19 to reduce noise on the voltage reference sense point. Each of the Component Video output traces should be connected to their respective feedback pins. This provides the Cable Detection (CD) circuitry the ability to detect whether a cable has been plugged into the connector. The CD circuitry is not active for TV signal output, so it would not be necessary to connect the feedback circuit in that case. If any signal filtering or conditioning components are added to the Component Video traces, the feedback pins should be connected after the additional components (ie, feedback pins should tap into to the connector side of the Component Video signals). A ferrite bead is recommended near the voltage input pins of the TVDAC module to reduce noise in the video module.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 55
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.9. LVDSVideoOutput The i.MX53 Applications processor contains two separate LVDS modules that can be operated independently. Each module provides five sets of differential pair signals, four used for data and one pair for the clock signal. The Quick Start board uses only one of the two modules to provide an optional secondary display panel that can be used in conjunction with one of the other primary means of video output, or if desired, to be used as the sole video output. Developers who wish to use two LVDS outputs at the same time may wish to consider the MCIMX53SMD Tablet for development. The Quick Start board makes use of three of the differential pair data pins and the clock pins. These signals, combined with a display enable pin, a contrast pin, two separate channels of I2C communications, an interrupt pin, and power supplies (5V and 3.2V), will provide the necessary signals to support many of the LVDS display panels currently available on the Market. The connector used is a 30‐pin connector that meets the LVDS standards for connectors (Hirose, DF19G‐30P‐1H(56)). Development work with LVDS panels was done with the Hannstar HSD100PXN1‐A00‐C11 display. This display determined the signal ordering on the connector. To aid in development work, Freescale has purchased a large number of LVDS display and has contracted to make customer cables that will connect the displays to the Quick Start board. This LVDS display kit will be available from Freescale as described in the board accessory section. If the developer wishes to use a different LVDS display, a custom cable would most likely be required to ensure the plug on the cable end that connected to the display was the right type and to re‐order the signals to match the ordering on the display. For use with other displays, signals are referenced to the following voltages: LVDS Data/Clock 2.5V (LVDS_2V5) Display Control 3.3V (VLDO3_3V3) I2C channel two 3.2V (DCDC_3V2) I2C channel three 3.3V (VLDO3_3V3) Isolation resistors on the i2C channel two traces (R213, R214) provide a means of isolating the LVDS connector from other functions on the board if the LVDS connector is interfering with I2C communication. In addition, the empty pads can also serve as attachment points for hand soldered wires if the developer wishes to run different signals to this connector. The i.MX53 Applications Processor has both an internal and external method to measure Band Gap resistance. If the internal method is chosen by software, pin AA14 can be left floating. If the external method is desired, a 28.0K 1% Ohm resistor should be attached between pin AA14 and ground. It is recommended that this resistor be added routinely to give software the option of choosing between the two methods. It is also recommended to place a 49.9 1% Ohm resistor as the voltage input pin of U14 (NVCC_LVDS_BG) to filter the power used in measuring the Band Gap.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 56
PUBI – Public Use Business Information
5.10. ExpansionPort The function of the Quick Start board Expansion Port is to bring out many of the i.MX53 pins that are otherwise unused on the Quick Start board. The overriding design considerations for this port were to be able to support HDMI functionality through a daughter card (primary) while also being able to support an existing LCD daughter card (secondary). In meeting these considerations, the Expansion Port was also constrained to meet a general power/signal format adopted across all recent i.MX development board designs, primarily for safety and equipment damage consideration. For these reasons, there may be some functionalities of the i.MX53 chip that are not accessible on the i.MX53 Quick Start board. This board simply cannot be all things to all people. The MCIMX53SMD is available for developers looking for more options. For developers who are interested in designing custom daughter cards for use with the Quick Start board, the following capabilities are available from the Expansion Port. Please note that many pins are muxed, so that not all features are available at the same time:
• Two Serial Peripheral Interfaces (SPI) CSPI, eCSDPI2 • Two I2S/SSI/AC97 Ports AUDMUX4, AUDMUX5 • Two Inter‐Integrated Circuits (I2C) I2C1, I2C2 • 2 UARTs UART4, UART5 • SPDIF Audio • USB ULPI Port USBH2 • 24‐bit Data and display control signals • Resistive Touch Screen Interface • CSI Camera
In addition to the Data/Signal traces to support the above functionality, the following power sources are also included on the Expansion Port:
• 5V_MAIN 5V DC Power Supply • LCD_3V2 3.2V DCDC_3V2 • VIOHI_2V775 2.775V VLDO4 • VLDO8_1V8 1.8V VLDO8 • VLDO9_1V5 1.5V VLDO9 • VLCD_BLT Current Source PMIC LED Driver
Note that VLDO9 is only used by the Expansion Port on the Quick Start board. The developer is free to reprogram the voltage of the LDO regulator on the PMIC for whatever voltage may be required subject to the following limitations (1.25V – 3.6V, 100mA). The proper connector to mate with Expansion Port J13 is made by Samtec, QTH‐060‐XX‐L‐D‐A, where XX determines the height of the connector. For a table of available pin‐mux options, see the expansion port pin‐out in section 6.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 57
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.11. Audio The main Audio CODEC used on the Quick Start board is the Freescale SGTL5000 Low Power Stereo Codec with Headphone Amp. The i.MX53 Applications Processor provides digital sound information from the AUDMUX module channel 5 port via I2S communications protocol. The Audio CODEC also receives command instructions from the I2C channel 2 bus and receives a 24 MHz clock input signal from GPIO_0 of the i.MX53 processor. These seven connections with the processor are the only required signals. The Audio CODEC provides a Left and Right Stereo output signal capable of providing a 16 Ohm set of headphones/earbuds with up to 58 mW of power. The Audio CODEC is also capable of receiving a single microphone channel, and converting the information to a digital format and transmitting it back to the processor. The CODEC also generates the necessary microphone bias voltage to allow proper condenser operation. The Quick Start board was designed to be used with a range of microphone options, including the mono‐microphone/earbud sets commonly used with cellular phones. For this reason, the microphone bias voltage is connected to the microphone input signal on the Quick Start board, rather than connecting the bias voltage signal to a separate channel on the Microphone Jack (J6) and allowing a higher end microphone to connect the bias source closer to the connector. In addition, the right channel audio output of the Audio CODEC can be sent to the Microphone Jack. The Quick Start board does not come with this feature by default, but the developer can easily populate the L22 footprint with a ferrite bead or a zero Ohm jumper. The Quick Start board is also designed with a cable detect feature on both the Headphone and Microphone Jacks. One option would be to use an audio connector with an internal flag that would make or break depending on whether the connector barrel was inserted into the jack. These connectors are available, but are often more expensive and may have supply problems. On the Quick Start board, a four pin, Audio/Video style connector was chosen to implement the cable detect feature. When a three connector cable is inserted into the connector, the cable detect pin is shorted to the ground pin, sending an active low signal back to the processor to indicate that a cable was inserted. For this reason, the ground pin on the Microphone and Headphone Jacks must be system ground and not a virtual audio ground. Therefore, the Audio CODEC was designed to use the AC Coupled audio mode which makes use of two 220uF capacitors. If the developer wishes to design a board that uses a flagged jack for cable detection or does not implement a cable detection scheme, it would then be possible to use the Direct Drive feature of the Audio CODEC and eliminate the need for the large capacitors. The Audio CODEC can be reset by software via the I2C channel, but there is no hardware reset pin on the CODEC. Should I2C communications be lost between the Audio CODEC and the Processor, it may be necessary to shutdown DCDC_3V2 power to the Quick Start board and reinitialize the Audio CODEC by the power on sequence.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 58
PUBI – Public Use Business Information
5.12. Ethernet The Ethernet subsystem of the Quick Start board is provided by the SMSC LAN8720 Ethernet Transceiver (U17). The Ethernet Transceiver (or PHY) receives standard RMII Ethernet signals from the Fast Ethernet Controller (FEC) of the i.MX53 Applications Processor. The Processor takes care of all Ethernet protocols at the MAC layer and above. The PHY is responsible only for the Link Layer formatting. The PHY receives a 50MHz clock signal from the oscillator X1. On initial versions of the i.MX53 silicon, this clock signal was shared with the SATA module of the i.MX53 Processor. On current versions of the Quick Start board, the 50 MHz clock signal is only used to support the Ethernet subsystem. The two control traces from the i.MX53 Processor to the Ethernet PHY are and Active low Interrupt trace (FEC_nINT) and an Active Low reset line (FEC_nRST). When the PHY comes out of reset, it is internally programmed to establish communications with an attached Ethernet device and be ready to correctly format all communications, whether they are being transmitted or received by the processor. If communications become unreliable, the processor can restart the PHY by forcing it into reset and allowing the PHY come back out of reset normally. The PHY is connected directly to the integrated magnetics of the Ethernet/Dual USB connector (J2), with two pairs of differential traces for receive and transmit, and connections to the indicator LEDs. The differential pair traces are biased externally with 49.9 1% Ohm pull‐up resistors. The magnetics included in the Ethernet connector were chosen to enable the auto‐negotiation feature of the PHY to work correctly. When initially connected to another Ethernet device, the PHY will negotiate to determine if it connected to a switch type device or another Ethernet end device, and will reconfigure the Transmit and Receive inputs to correctly match the device attached. This eliminates the need for cross‐over cables when directly connecting to another Ethernet end device. The LED status indicators are driven by the PHY to show a connected link and activity on the link. It is important to note that the LED control lines from the PHY also serve as PHY feature selection options. At boot time, the LED1 control pin serves to determine whether the 1.2V internal regulator should be turned on or off, and the LED2 control pins determines whether the PHY accepts an external reference clock or internally generates the clock signal and outputs it to the processor for reference. See the LAN8720 datasheet for further details. If a board designer wishes to reduce costs in the implementation of Ethernet, it is possible to replace the oscillator with a lower cost 50 MHz crystal. The LAN8720 has more information on this implementation. The oscillator was originally designed to support two different subsystems on the board, and is no longer an necessary expense.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 59
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.13. USBHostconnections The i.MX53 Applications Processors contains three USB 2.0 Host ports and one USB 2.0 OTG port. Of these four ports, only two (Host1 and OTG) are connected internally to a transceiver to provide USB Data signals suitable (UTMI) for direct connection to a USB jack. The other two (Host2 and Host3) ports require a connection to an external serial transceiver or a direct connection to another USB device using ULPI communications. On the Quick Start board, only the Host1 and OTG ports are utilized The Host1 USB Port is connected to the Upper USB‐A Host slot of the Ethernet/Dual USB Connector (J2). A Common Mode Choke is inserted in the USB data lines to ensure compliance with North America and Europe emissions testing. The 5V‐Main power rail is connected to the USB_5V pins of the Ethernet/Dual USB Connector, after first going through a 1.1A fuse for over‐current protection and a PNP MOSFET to allow the Processor to control USB_5V power (USB_PWREN). No attempt is made on the Quick Start board to regulate the actual voltage level of this power rail, nor to regulate the amount of current drawn by each port (except by the 1.1A fuse). Power from the DCDC_3V2 and the VBUS_2V5 voltage rails are supplied to the HOST1 part through small value resistors for noise filtering. The USB_H1_VBUS is a reference voltage signal only and is provide by the 5V_Main power rail via the USB Bus Power control MOSFET. In much the same way as described above, the OTG Port is connected to the Lower USB‐A Host slot of the Ethernet/Dual USB Connector (J2). The USB_5V power source is the same source as supplied to the upper port, but the USB OTG data lines go through a separate Common Mode Choke. The difference between the Host1 and the OTG Port connections is that the OTG Port is also connected to a Micro‐B USB Device port. In the normal implementation of OTG, the same connector is used for both Host and Device USB connections. A high or low signal on the USB ID pin would indicate whether a Host (A) plug or a Device (B) plug was attached. Since most Host plugs available today are the full size plugs, but most portable USB Devices are moving toward the Micro‐B connector, a two connector approach was implemented on the Quick Start board. The USB_5V power supplied by an attached Host device through the Micro‐B connector will provide a TTL logic high signal to the OTG Port through USB_OTG_ID (pin C16). The ID signal is corrected to the proper logic by way of a simple voltage divider. When the OTG Port senses this logic high condition, the OTG Port will switch to device operations, regardless of whether there is a USB Device plugged into the Lower USB Host Port. This USB OTG configuration is used for demonstration purposes only and is not recommended for mass production. The developer is cautioned to only plug one cable into the Lower USB Host Port OR the micro‐B Device port at a time, since two cables might degrade the USB signal beyond acceptable operating limits. The External USB 5V power supplied by a connected USB device is only used in two locations on the Quick Start board. It is used to provide the USB ID signal (passive sense) and to provide the USB_OTG_VBUS reference signal. For the board designer, two 6.04K Ohm 1% resistors are used, one attached to each of the Host1 and OTG Ports. These resistors are used to set the Band Gap levels.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 60
PUBI – Public Use Business Information
5.14. SATA The internal SATA PHY of the i.MX53 Applications Processor provides the two differential pair data signals necessary for SATA operations. No external transceiver is required. Each of the four data lines pass through a 0.01 uF capacitor for decoupling. These capacitors are placed as close to the SATA connector as possible. The Processor SATA module receives 2.5V power from VBUCKPERI for the PHY portion of the module and 1.3V power from VLDO5_1V3 for the controller portion of the module. A 191 Ohm 1% resistor is required to be connected to the SATA_REXT pin (C13). This resistor received a small, constant current at the initialization of the SATA module to allow for cable impedance calibration. After module initialization, this resistor is not used. The i.MX53 Applications Processor provides two pins to receive an external differential pair clock input for use by the SATA module. Testing of the i.MX53 Processor confirms that the internally generated clock signal is working properly. Therefore the external clock components are not populated and the eFuses for the Processor are configured for internal clock operation. The 7‐pin SATA data connector is suitable for use will all SATA capable storage media devices including Hard Drives and Optical Media storage devices (DVD/CD). It is possible to configure the Quick Start Board to boot directly from a SATA device. To enable the Quick Start board to boot from SATA, the developer will have the make the following modifications to the board:
1) Solder a 10‐DIP Switch onto the pads for SW1. A suitable switch is manufactured by Multicomp (MCNHDS‐10‐T). Move Switches 6 and 8 to the ON (UP) position. Alternately, two wires can be soldered between pads 6 & 15 and 8 & 13 on the SW1 footprint (this effectively take the place of moving the switch to the on position.
2) Rotate R46 in the clockwise direction by 90 degrees pivoting around pad R46.2. Add a wire from the unconnected end of the 4.7K Ohm resistor to as suitable ground point. The pad for R47.2 is the closest ground point.
Table 12 below shows the TTL logic levels on the external boot configuration (BOOT_CFG1) scheme to modify the board from SD/MMC boot to use SATA boot. CFG1[7] CFG1[6] CFG1[5] CFG1[4] CFG1[3] SD/MMC Boot (Default) 0 1 ‐ ‐ ‐ SATA Boot 0 0 1 0 1
Table 12. SATA Boot Mode Configuration Table.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 61
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
5.15. DebugUARTSerialPort The i.MX53 Applications Processor has 5 independent UART Ports (UART1 – UART5). The Processor will boot by default using UART1 to output serial debugging information, specifically on pins CSI0_DAT10 (pin R5) and CSI0_DAT11 (pinT2). These two pins are output from the NVCC_CSI module, which is pulled up to 1.8V on the Quick Start board. In order to convert the UART Transmit and Receive signal to a 3.2V logic signal, two single‐direction level shifters (U25, U26) are used. The level shifted signals are sent to a low cost, RS232 transceiver, which reformats the signals to the correct voltages and drives the signals. The resulting cable ready signals are then connected to the RS232 Debug connector. No RTS or CTS signals are sent from the Processor to the Debug connector since these signals are commonly ignored by most applications. The required terminal settings to receive debug information during the boot cycle are shown in Table 13:
Table 13. Terminal Setting Parameters If the developer wishes to repurpose the Debug UART connector in software into an Applications connector, the Quick Start board can support this using a Null Modem Adapter. The adapters are readily available from most cable and electronics stores at a small cost. See the section on the Expansion Port to find how to access some of the other UART channels on the Quick Start board.
Data Rate 115,200 Baud Data bits 8 Parity None Stop bits 1 Flow Control None
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 62
PUBI – Public Use Business Information
5.16. JTAGOperations The i.MX53 Applications Processor accepts five JATG signals from an attached debugging device on dedicated pins. A sixth pin on the processor accepts a board HW configured input specific to the Quick Start board only. The five JTAG signal used by the Processor are:
JTAG_TCK TAP Clock JTAG_TMS TAP Machine State JTAG_TDI TAP Data In JTAG_TDO TAP Data Out JTAG_nTRST TAP Reset Request (Active Low)
The TAP Clock signal is provided by the attached debugging device and serves as a reference for data exchange between the debugging device and the Processor. The TAP Machine State is a logical signal provided by the debugging device to let the Processor (or Target) know what state to enter next. Per JATG specifications, all questions of state have two options that can be selected with either a ‘high’ or ‘low’ signal. The TAP Data In and TAP Data Out signal are used only for data transfer. The Active Low TAP Reset Request is initiated by the debugging device and resets the TAP (JTAG) module within the Processor. This gives the debugging device the ability to reset the internal Processor JTAG module if required without affecting the remainder of the Processor. The system JTAG reset signal provided by the attached debugging device does not go to the JTAG module of the processor, but goes to the external processor reset circuitry which will fully reset the i.MX53 processor, but not the power rails. The JTAG_MOD pin used by the JTAG module of the i.MX53 Processor determines how much of the i.MX53 processor is connected to the JTAG Debugging device. In the pull‐down mode (default on the Quick Start board) allows all of the i.MX53 TAPs (SJC, SDMA, ARM) to be connected to the debugging device in a daisy chain connection. If the JTAG_MOD pin is pulled high, then the attached debugging device can only access the SJC TAP. Three other common JTAG signals used by debugging devices (Return Clock, Data Enable, and Data Acknowledge) are not used by the i.MX53 Applications Processor and are either pulled‐up or pulled‐down by the Quick Start board. On the Quick Start board, the logic signals for JTAG are designed to be 1.8V. A 1.8V reference signal from VLDO8_1V8 is connected to pin 1 of the 20‐pin JTAG connector to provide this logic level signal to the attached debugging device. In addition, for debugging devices that required power, a limited amount (~0.5 A) of 3.2V power can be supplied to the debugging device. If the device requires 1.8V power (instead of 3.2V power), the Quick Start board can be configured to supply this as well, but in a very limited amount (100 mA).
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 63
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
6. ConnectorPin‐Outs This section fully describes the signals going to each of the 13 connectors used on the Quick Start board. Although this information is available on the schematic, the footprint used in manufacturing the PCB is also included to provide a map to the actual signals on the board. The image of the footprint provide is for the PCB side that the connector mounts. Therefore, to find corresponding pins on the opposite side of the PCB, the image should be reversed. In addition to the pin tables and footprints, there is also a pin‐mux table provided for the Expansion Port so that the developer can readily see the possible signals brought out through the Expansion Port. These details are included in the following tables and figures: Table 14. Power Jack (J1) Figure 20. Power Jack (J1) Table 15. Micro‐B USB Connector (J3) Figure 21. Micro‐B USB Connector (J3) Table 16. Ethernet/Dual USB Conn (J2) Figure 22. Ethernet/Dual USB Conn (J2) Table 17. Headphone Connector (J18) Figure 23. Headphone Connector (J18) Table 18. Microphone Connector (J6) Figure 24. Microphone Connector (J6) Table 19. VGA DB15 Connector (J8) Figure 25. VGA DB15 Connector (J8) Table 20. LVDS Connector (J9) Figure 26. LVDS Connector (J9) Table 21. SATA Data Connector (J7) Figure 27. SATA Data Connector (J7) Table 22. SD Card Connector (J5) Figure 28. SD Card Connector (J5) Table 23. microSD Card Connector (J4) Figure 29. microSD Card Connector (J4) Table 24. Debug UART Connector (J16) Figure 30. Debug UART Connector (J16) Table 25. JTAG Connector (J15) Figure 31. JTAG Connector (J15) Table 26. Expansion Port (J13) Figure 32. Expansion Port (J13) Table 27. Expansion Port Pin‐Mux Table
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 64
PUBI – Public Use Business Information
Power Jack (J1)
Micro‐B USB (J3)
Positive Terminal 1Negative Terminal 2Ground Terminal 3
Table 14. Power Jack (J1) Figure 20. Power Jack (J1)
5V Power 1Data Negative 2Data Positive 3No Connect (ID) 4Ground 5Chassis Ground 6Chassis Ground 7Chassis Ground 8Chassis Ground 9Chassis Ground 10Chassis Ground 11
Table 15. Micro‐B USB Connector (J3) Figure 21. Micro‐B USB Connector (J3)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 65
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Ethernet/Dual USB (J2)
Transmit Core Tap 1 Transmit Data Positive 2 Transmit Data Negative 3 Receive Data Positive 4 Receive Data Negative 5 NC6 6 NC7 7 NC8 8 NC9 9 Receive Core Tap 10 LED1 Anode 11 LED1 Cathode 12 LED2 Anode 13 LED2 Cathode 14 Top USB 5V Power T1 Top USB Data Negative T2 Top USB Data Positive T3 Top USB Ground T4 Bottom USB 5V Power B1 Bottom USB Data Negative B2 Bottom USB Data Positive B3 Bottom USB Ground B4 Shield Ground S1 Shield Ground S2 Shield Ground S3 Shield Ground S4 Shield Ground S5 Shield Ground S6 Shield Ground S7 Shield Ground S8
Table 16. Ethernet/Dual USB Conn (J2) Figure 22. Ethernet/Dual USB Conn (J2)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 66
PUBI – Public Use Business Information
Headphone Connector (J18)
Microphone Connector (J6)
Right channel 1Left Channel Ground Flag 3Left Channel (Tip) 4Analog Ground (Ring) 5Plug Sense 6
Table 17. Headphone Connector (J18) Figure 23. Headphone Connector (J18)
Right channel 1Microphone Ground Flag 3Microphone Signal (Tip) 4Analog Ground (Ring) 5Plug Sense 6
Table 18. Microphone Connector (J6) Figure 24. Microphone Connector (J6)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 67
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
VGA DB15 (J8)
Component Video Pr 1Component Video Y 2Component Video Pb 3No Connect 4Ground 5DAC Ref Ground 6DAC Ref Ground 7DAC Ref Ground 85V VGA REF 9Ground 10No Connect 11VGA I2C (Data) 12VGA Horiz Synch 13VGA Vert Synch 14VGA I2C (Clock) 15
Table 19. VGA DB15 Connector (J8) Figure 25. VGA DB15 Connector (J8)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 68
PUBI – Public Use Business Information
LVDS Connector (J9)
Table 20. LVDS Connector (J9) Figure 26. LVDS Connector (J9)
Backlight Enable 1 VCC 3V2 Supply 2 VCC 3V2 Supply 3 EDID 3V2 Supply 4 LED Brightness Adjust 5 EDID I2C (Clock) 6 EDID I2C (Data) 7 LVDS Transmit 0 Negative 8 LVDS Transmit 0 Positive 9 Ground 10 LVDS Transmit 1 Negative 11 LVDS Transmit 1 Positive 12 Ground 13 LVDS Transmit 2 Negative 14 LVDS Transmit 2 Positive 15 Ground 16 LVDS Clock Negative 17 LVDS Clock Positive 18 Ground 19 Touch Panel 5V Supply 20 Touch Panel 5V Supply 21 Ground 22 Ground 23 LED 5V Supply 24 LED 5V Supply 25 LED 5V Supply 26 LVDS I2C (Clock) 27 LVDS I2C (Data) 28 LVDS I2C Interrupt 29 No Connect 30
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 69
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
SATA DATA Connector (J7)
Table 21. SATA Data Connector (J7) Figure 27. SATA Data Connector (J7)
Ground 1Transmit Data Positive 2Transmit Data Negative 3Ground 4Receive Data Negtive 5Receive Data Positive 6Ground 7
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 70
PUBI – Public Use Business Information
SD Card Connector (J5)
Data3 1Command 2Ground 3VCC 3V2 Supply 4Clock 5Ground 6Data0 7Data1 8Data2 9Data4 10Data5 11Data6 12Data7 13Card Detect 14Write Protect 15Shield Ground 16Shield Ground 17Shield Ground 18Shield Ground 19
Table 22. SD Card Connector (J5) Figure 28. SD Card Connector (J5)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 71
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
microSD CardConnector (J4)
Data2 1Data3 2Command 3VCC 3V3 Supply 4Clock 5Ground 6Data0 7Data1 8Shield GND1 SH1Shield GND2 SH2Shield GND3 SH3Shield GND4 SH4
Table 23. microSD Card Connector (J4) Figure 29. microSD Card Connector (J4)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 72
PUBI – Public Use Business Information
Debug UART Connector (J16)
No Connect (CD) 1Data Transmit 2Data Receive 3No Connect (DTR) 4Ground 5No Connect (DSR) 6No Connect (RTS) 7No Connect (CTS) 8No Connect (RI) 9Shield Ground M1Shield Ground M2
Table 24. Debug UART Connector (J16) Figure 30. Debug UART Connector (J16)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 73
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
JTAG Connector (J15)
1.8V Logic Reference 13.3V JTAG Supply Voltage 2JTAG TAP Reset (Active Low) 3Ground 4JTAG Test Data In 5Ground 6JTAG TAP Machine State 7Ground 8JTAG TAP Clock 9Ground 10RTCK (Pulled Low) 11Ground 12JTAG Test Data Out 13Ground 14JTAG System Reset (Active Low) 15Ground 16Debug Request (Pulled High) 17Ground 18Debug Acknowledge (Pulled Low) 19Ground 20
Table 25. JTAG Connector (J15) Figure 31. JTAG Connector (J15)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 74
PUBI – Public Use Business Information
Expansion Port Connector (J13)
Table 26. Expansion Port (J13) Figure 32. Expansion Port (J13)
SH8 Shield Ground Shield Ground SH7120 No Connect No Connect 119 118 No Connect Display Read 117 116 Display Data Ready 1.5V Power (VLDO9) 115 114 Display Horiz Synch 1.5V Power (VLDO9) 113 112 Backlight Brightness Adj 1.5V Power (VLDO9) 111 110 Display Vert Synch Display Write 109 108 Display Data23 Disp Chip Sel1 (Act Low) 107 106 Display Data22 Disp Chip Sel0 (Act Low) 105 104 Display Data21 Ground 103 102 Display Data20 Touch Screen X‐Neg 101 100 Display Data19 Touch Screen X‐Pos 99 98 Display Data18 Touch Screen Y‐Neg 97 96 Display Data17 Touch Screen Y‐Positive 95 94 Display Data16 Ground 93 92 Display Data15 IIS Reset 91 90 Display Data14 IIS Clock 89 88 Display Data13 IIS Master Out‐Slave In 87 86 Display Data12 IIS Master In‐Slave Out 85 84 Display Data11 Exp Card ID1 83 82 Display Data10 IIS Chip Sel (Active Low) 81 80 Display Data09 Display Power Enable 79 78 Display Data08 5V Power 77 76 Display Data07 5V Power 75 74 Display Data06 5V Power 73 72 Display Data05 No Connect 71 70 Display Data04 No Connect 69 68 Display Data03 No Connect 67 66 Display Data02 No Connect 65 64 Display Data01 Audio System Clock 63 62 Display Data00 Exp Card ID0 61 SH6 Shield Ground Shield Ground SH5
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 75
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Expansion Port Connector (J13)
Table 26. Expansion Port (J13) Figure 32. Expansion Port
SH4 Shield Ground Shield Ground SH3 60 Ground Display Rst (Active Low) 59 58 Display Vert Synch No Connect 57 56 Display Horiz Synch No Connect 55 54 Ground Display Power Down 53 52 Display Data19 No Connect 51 50 Display Data18 3.2V Power 49 48 Ground 3.2V Power 47 46 Display Data17 3.2V Power 45 44 Display Data16 Display Data Clock 43 42 Ground No Connect 41 40 SPDIF Data Transmit No Connect 39 38 SPDIF Data Clock No Connect 37 36 Ground Display Pixel Clock 35 34 Display Data15 Display Reset 33 32 Display Data14 I2C Clock 31 30 Ground I2C Data 29 28 Display Data13 No Connect 27 26 Display Data12 1.8V Power (VLDO8) 25 24 Ground No Connect 23 22 No Connect No Connect 21 20 No Connect 1.8V Power (VLDO8) 19 18 Ground 1.8V Power (VLDO8) 17 16 No Connect Display Backlight Return 15 14 No Connect 5V Power 13 12 Ground 5V Power 11 10 No Connect Display Backlight Power 9 8 5V Power 5V Power 7 6 Ground 3.2V Power 5 4 5V Power 2.775V Power (VLDO4) 3 2 5V Power 1.8V Power (VLDO8) 1
SH2 Shield Ground Shield Ground SH1
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 76
PUBI – Public Use Business Information
J13 PIN J13 Name i.MX53 Pin Name ALT(1) ALT(2) ALT(3) 26 CSI0_DAT12 CSI0_DAT12 GPIO5_30 uart4 TXD_MUX 28 CSI0_DAT13 CSI0_DAT13 GPIO5_31 uart4 RXD_MUX 29 I2C2_SDA KEY_ROW3 GPIO4_13 H2_DP ASRC_EXT_CLK 31 I2C2_SCL KEY_COL3 GPIO4_12 H2_DM spdif IN1 32 CSI0_DAT14 CSI0_DAT14 GPIO6_0 uart5 TXD_MUX 33 DISP0_RESET EIM_WAIT GPIO5_0 WEIM_DTACK_B 34 CSI0_DAT15 CSI0_DAT15 GPIO6_1 uart5 RXD_MUX 35 CSI0_PIXCLK CSI0_PIXCLK GPIO5_18 38 PCLOCK GPIO_7 GPIO1_7 EPITO can1 TXCAN 40 SPDIF_TX GPIO_17 GPIO7_12 SDMA_EXT_EVENT0 PMIC_RDY 43 DISP0_DCLK DI0_DISP_CLK GPIO4_16 USBH2_DIR 44 CSI0_DAT16 CSI0_DAT16 GPIO6_2 uart4 RTS 46 CSI0_DAT17 CSI0_DAT17 GPIO6_3 uart4 CTS 50 CSI0_DAT18 CSI0_DAT18 GPIO6_4 uart5 RTS 52 CSI0_DAT19 CSI0_DAT19 GPIO6_5 uart6 CTS 53 SCSI0_PWDN NANDF_RB0 GPIO6_10 56 CSI0_VSYNCH CSI0_VSYNCH GPIO5_21 58 CSI0_HSYNCH CSI0_MCLK GPIO5_19 ccm CSI0_MCLK 59 CSI0_RSTB NANDF_WP_B GPIO6_9 62 DISP0_DAT0 DISP0_DAT0 GPIO4_21 cspi SCLK USBH2_DAT0 63 GPIO_0(CLK0) GPIO_0 GPIO1_0 KEY_COL5 SSI_EXT1_CLK 64 DISP0_DAT1 DISP0_DAT1 GPIO4_22 cspi MOSI USBH2_DAT1 66 DISP0_DAT2 DISP0_DAT2 GPIO4_23 cspi MISO USBH2_DAT2 68 DISP0_DAT3 DISP0_DAT3 GPIO4_24 cspi SS0 USBH2_DAT3 70 DISP0_DAT4 DISP0_DAT4 GPIO4_25 cspi SS1 USBH2_DAT4 72 DISP0_DAT5 DISP0_DAT5 GPIO4_26 cspi SS2 USBH2_DAT5 74 DISP0_DAT6 DISP0_DAT6 GPIO4_27 cspi SS3 USBH2_DAT6 76 DISP0_DAT7 DISP0_DAT7 GPIO4_28 cspi RDY USBH2_DAT7 78 DISP0_DAT8 DISP0_DAT8 GPIO4_29 pwm1 PWMO wdog1 WDOG_B
Legend UART4 AUDMUX4 I2C1 ECSPI2 USBH2 UART5 AUDMUX5 I2C2 CSPI SPDIF
Table 27. Expansion Port Pin‐Mux Table
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 77
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
J13 PIN J13 Name ALT(4) ALT(5) ALT(6) ALT(7) 26 CSI0_DAT12 USBH3_DATA0 DEBUG_PC6 EMI_DEBUG41 tpiu TRACE9 28 CSI0_DAT13 USBH3_DATA1 DEBUG_PC7 EMI_DEBUG42 tpiu TRACE10 29 I2C2_SDA i2c2 SDA 32K_OUT ccm PLL4_BYP usb1 LINESTATE0 31 I2C2_SCL i2c2 SCL ecspi1 SS3 fec CRS usb1 SIECLOCK 32 CSI0_DAT14 USBH3_DATA2 DEBUG_PC8 EMI_DEBUG43 tpiu TRACE11 33 DISP0_RESET 34 CSI0_DAT15 USBH3_DATA3 DEBUG_PC9 EMI_DEBUG44 tpiu TRACE12 35 CSI0_PIXCLK DEBUG_PC0 EMI_DEBUG29 38 PCLOCK uart2 TXD_MUX firi RXD spdifPLOCK ccm PLL2_BYP 40 SPDIF_TX CE_RTC_FSV_TRIG spdif OUT1 SNOOP2 JTAG_ACT 43 DISP0_DCLK DEBUG_CORE_STATE0 EMI_DEBUG0 usb1 AVALID 44 CSI0_DAT16 USBH3_DATA4 DEBUG_PC10 EMI_DEBUG45 tpiu TRACE13 46 CSI0_DAT17 USBH3_DATA5 DEBUG_PC11 EMI_DEBUG46 tpiu TRACE14 50 CSI0_DAT18 USBH3_DATA6 DEBUG_PC12 EMI_DEBUG47 tpiu TRACE15 52 CSI0_DAT19 USBH3_DATA7 DEBUG_PC13 EMI_DEBUG48 usb2 BISTOK 53 SCSI0_PWDN usb1 VSTATUS3 56 CSI0_VSYNCH DEBUG_PC3 EMI_DEBUG32 tpiu TRACE0 58 CSI0_HSYNCH DEBUG_PC1 59 CSI0_RSTB usb1 VSTATUS2 62 DISP0_DAT0 DEBUG_CORE_RUN EMI_DEBUG5 usb2 TXREADY 63 GPIO_0(CLK0) EPITO SRTC_ALARM_DEB USBH1_PWR csu TD 64 DISP0_DAT1 DEBUG_EVENT_CHAN_SEL EMI_DEBUG6 usb2 RXVALID 66 DISP0_DAT2 DEBUG_MODE EMI_DEBUG7 usb2 RXACTIVE 68 DISP0_DAT3 DEBUG_EVENT_BUS_ERROR EMI_DEBUG8 usb2 RXERROR 70 DISP0_DAT4 DEBUG_BUS_RWB EMI_DEBUG9 usb2 SIECLOCK 72 DISP0_DAT5 DEBUG_MATCHED_DMBUS EMI_DEBUG10 usb2 LINESTATE0 74 DISP0_DAT6 DEBUG_RTBUFFER_WRITE EMI_DEBUG11 usb2 LINESTATE1 76 DISP0_DAT7 DEBUG_EVENT_CHANNEL0 EMI_DEBUG12 usb2 VBUSVALID 78 DISP0_DAT8 DEBUG_EVENT_CHANNEL1 EMI_DEBUG13 usb2 AVALID
Legend UART4 AUDMUX4 I2C1 ECSPI2 USBH2 UART5 AUDMUX5 I2C2 CSPI SPDIF
Table 27. Expansion Port Pin‐Mux Table (con)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 78
PUBI – Public Use Business Information
J13 PIN J13 Name i.MX53 Pin Name ALT(1) ALT(2) ALT(3) 79 DISP0_POWER_EN EIM_D24 GPIO3_24 uart3 TXD_MUX ecspi1 SS2 80 DISP0_DAT9 DISP0_DAT9 GPIO4_30 pwm2 PWMO wdog2 WDOG_B 81 DSIP0_SER_nCS EIM_D20 GPIO3_20 DI0_PIN16 SER_DISP0_CS 82 DISP0_DAT10 DISP0_DAT10 GPIO4_31 USBH2_STP 84 DISP0_DAT11 DISP0_DAT11 GPIO5_5 USBH2_NXT 85 DISP0_SER_MISO EIM_D22 GPIO3_22 DI0_PIN1 DISPB0_SER_DIN 86 DISP0_DAT12 DISP0_DAT12 GPIO5_6 USBH2_CLK 87 DISP0_SER_MOSI EIM_D28 GPIO3_28 uart2 CTS DISPB0_SER_DI0 88 DISP0_DAT13 DISP0_DAT13 GPIO5_7 AUD5_RXFS 89 DISP0_SER_SCLK EIM_D21 GPIO3_21 DI0_PIN17 DISPB0_SER_CLK 90 DISP0_DAT14 DISP0_DAT14 GPIO5_8 AUD5_RXC 91 DISP0_SER_RS EIM_D29 GPIO3_29 uart2 RTS DISPB0_SER_RS 92 DISP0_DAT15 DISP0_DAT15 GPIO5_9 ecspi1 SS1 ecspi2 SS1 94 DISP0_DAT16 DISP0_DAT16 GPIO5_10 ecspi2 MOSI AUD5_TXC 96 DISP0_DAT17 DISP0_DAT17 GPIO5_11 ecspi2 MISO AUD5_TXD 98 DISP0_DAT18 DISP0_DAT18 GPIO5_12 ecspi2 SS0 AUD5_TXFS 100 DISP0_DAT19 DISP0_DAT19 GPIO5_13 ecspi2 SCLK AUD5_RXD 102 DISP0_DAT20 DISP0_DAT20 GPIO5_14 ecspi1 SCLK AUD4_TXC 104 DISP0_DAT21 DISP0_DAT21 GPIO5_15 ecspi1 MOSI AUD4_TXD 105 DISP0_nCS0 EIM_D23 GPIO3_23 uart3 CTS uart1 DCD 106 DISP0_DAT22 DISP0_DAT22 GPIO5_16 ecspi1 MISO AUD4_TXFS 107 DISP0_nCS1 EIM_A25 GPIO5_2 ecspi2 RDY DI1_PIN12 108 DISP0_DAT23 DISP0_DAT23 GPIO5_17 ecspi1 SS0 AUD4_RXD 109 DISP0_WR EIM_D30 GPIO3_30 uart3 CTS CSI0_D3 110 DISP0_VSYNCH DI0_PIN3 GPIO4_19 AUD6_TXFS 112 DISP0_CONTRAST GPIO_1 GPIO1_1 KEY_ROW5 SSI_EXT2_CLK 114 DISP0_HSYNCH DI0_PIN2 GPIO4_18 AUD6_TXD 116 DISP0_DRDY DI0_PIN15 GPIO4_17 AUD6_TXC 117 DISP0_RD EIM_D31 GPIO3_31 uart3 RTS CSI0_D2
Legend UART4 AUDMUX4 I2C1 ECSPI2 USBH2 UART5 AUDMUX5 I2C2 CSPI SPDIF
Table 27. Expansion Port Pin‐Mux Table (con)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 79
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
J13 PIN J13 Name ALT(4) ALT(5) ALT(6) ALT(7) 79 DISP0_POWER_EN cspi SS2 AUD5_RXFS ecspi2 SS2 uart1 DTR 80 DISP0_DAT9 DEBUG_EVENT_CHANNEL2 EMI_DEBUG14 usb2 VSTATUS0 81 DSIP0_SER_nCS cspi SS0 EPITO uart1 RTS USBH2_PWR 82 DISP0_DAT10 DEBUG_EVENT_CHANNEL3 EMI_DEBUG15 usb2 VSTATUS1 84 DISP0_DAT11 DEBUG_EVENT_CHANNEL4 EMI_DEBUG16 usb2 VSTATUS2 85 DISP0_SER_MISO cspi MISO USBOTG_PWR 86 DISP0_DAT12 DEBUG_EVENT_CHANNEL5 EMI_DEBUG17 usb2 VSTATUS3 87 DISP0_SER_MOSI cspi MOSI i2c1 SDA EXT_TRIG DI0_PIN13 88 DISP0_DAT13 DEBUG_EVT_CHN_LINES0 EMI_DEBUG18 usb2 VSTATUS4 89 DISP0_SER_SCLK cspi SCLK i2c1 SCL USBOTG_OC 90 DISP0_DAT14 DEBUG_EVT_CHN_LINES1 EMI_DEBUG19 usb2 VSTATUS5 91 DISP0_SER_RS cspi SS0 DI0_PIN15 CSI1_VSYNCH DI0_PIN14 92 DISP0_DAT15 DEBUG_EVT_CHN_LINES2 EMI_DEBUG20 usb2 VSTATUS6 94 DISP0_DAT16 SDMA_EXT_EVENT0 DEBUG_EVT_CHN_LINES3 EMI_DEBUG21 usb2 VSTATUS7 96 DISP0_DAT17 SDMA_EXT_EVENT1 DEBUG_EVT_CHN_LINES4 98 DISP0_DAT18 AUD4_RXFS DEBUG_EVT_CHN_LINES5 EMI_DEBUG23 WEIM_CS2 100 DISP0_DAT19 AUD4_RXC DEBUG_EVT_CHN_LINES6 EMI_DEBUG24 WEIM_CS3 102 DISP0_DAT20 DEBUG_EVT_CHN_LINES7 EMI_DEBUG25 sata_phy TDI 104 DISP0_DAT21 DEBUG_BUS_DEVICE0 EMI_DEBUG26 sata_phy TDO 105 DISP0_nCS0 DI0_DO_CS DI1_PIN2 CSI1_DATA_EN DI1_PIN14 106 DISP0_DAT22 DEBUG_BUS_DEVICE1 EMI_DEBUG27 sata_phy TCK 107 DISP0_nCS1 cspi SS1 DIO_D1_CS 108 DISP0_DAT23 DEBUG_BUS_DEVICE2 EMI_DEBUG28 sata_phy TMS 109 DISP0_WR DI0_PIN11 DISP1_DAT21 USBH1_OC USBH2_OC 110 DISP0_VSYNCH DEBUG_CORE_STATE3 EMI_DEBUG3 usb1 IDDIG 112 DISP0_CONTRAST pwm2 PWMO wdog2 WDOG_B esdhc1 CD src TESTER_ACK 114 DISP0_HSYNCH DEBUG_CORE_STATE2 EMI_DEBUG2 usb1 ENDSSN 116 DISP0_DRDY DEBUG_CORE_STATE1 EMI_DEBUG1 usb1 BVALID 117 DISP0_RD DI0_PIN12 DISP1_DAT20 USBH1_PWR USBH2_PWR
Legend UART4 AUDMUX4 I2C1 ECSPI2 USBH2 UART5 AUDMUX5 I2C2 CSPI SPDIF
Table 27. Expansion Port Pin‐Mux Table (con)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 80
PUBI – Public Use Business Information
7. BoardAccessories
7.1. HDMIDaughterCardFor developers wishing to output video via HDMI, there is an optional HDMI daughter card which can be purchased for use with the Quick Start board. The part number for the optional card is MCIMXHDMICARD, and this card can be purchased directly from Freescale.com. This HDMI card is connected to J13, and occupies the Expansion Port. The brass standoff on the HDMI card is threaded to accept a standard metric M3 machine screw. This will allow for a more sturdy connection if the developer plans to work with HDMI for a long period of time. Figure 33 below shows the HDMI card that is available. The schematics for the HDMI daughter card can be found on the freescale.com/imxquickstart website. The daughter card uses the Silicon Image SiI9022 HDMI Transmitter to reformat the display signals into the correct HDMI format and drive the video signals out the attached HDMI cable. Common Mode Chokes have been placed on the output of the Transmitter to meet FCC and CE emissions requirements.
Figure 33. Optional HDMI Daughter Card
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 81
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
In order to use the optional HDMI card with the Quick Start board, the environmental variables must be correctly set to support the card. This change needs to be done only one time, when the HDMI card is first used. The change requires the developer to use a host computer running a terminal window. When the power button is first pressed, the developer has 3 seconds to defeat the AUTOBOOT feature by pressing any key on the host computer. Once the boot cycle has been stopped, the developer now has access to change the boot environmental variables on the software image. At the terminal window, the developer should type the following two lines, pressing the enter key after each line: setenv bootargs_base ‘set bootargs console=ttymxc0,115200 ${hdmi}’ saveenv Once the change is saved (saveenv), the Quick Start board can be turned off and then back on, or the developer can type boot on the terminal to restart the boot process. The Quick Start board is now correctly configured for HDMI operation. A note for developers: The HDMI parameters are contained in the U‐BOOT code, and the recommended line to change the video output parameters only tells U‐BOOT to substitute the stored parameters into the boot process. If the developer wishes to enter the exact string of variables into the U‐BOOT code, the following line can be used instead of the first line above:
setenv bootargs_base ‘set bootargs console=ttymxc0,115200 video=mxcdi0fb:RGB24,1024x768M-16@60’
The above entry is all one line. After the line entry is made, the saveenv entry is also needed.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 82
PUBI – Public Use Business Information
7.2. LCDDisplayDaughterCardFor developers wishing to output video to a touch screen LCD, there is an optional WVGA daughter card which can be purchased for use with the Quick Start board. The part number for the optional card is MCIMX28LCD, and this card can be purchased directly from Freescale.com. This LCD Display card is connected to J13, and occupies the Expansion Port. The brass standoff on the LCD Display card nearest the connector is threaded to accept a standard metric M3 machine screw. This will allow for a more sturdy connection if the developer plans to work with LCD display for a long period of time. In addition, the developer may also wish to screw into the remaining 3 brass stand‐offs metric M3 machines screws that are approximately 25mm long. The screws can be adjust to provide support to the LCD card as it hangs over the Quick Start board. Figure 34 below shows the LCD card that is available. The schematics for the LCD Display daughter card can be found on the freescale.com/imxquickstart website. The daughter card uses the Seiko 43WVF1G‐0 WVGA display, and provides all the power required for correct operations, regulated on the Display card. Power for the LCD Display, with the exception of the back light circuitry, comes from the MAIN_5V power source and does not go through the Dialog DA9053 PMIC.
Figure 34. MCIMX28LCD 4.3” WVGA Display Daughter Card
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 83
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
In order to use the optional LCD daughter card with the Quick Start board, the environmental variables must be correctly set to support the card. This change needs to be done only one time, when the LCD Display card is first used. The change requires the developer to use a host computer running a terminal window. When the power button is first pressed, the developer has 3 seconds to defeat the AUTOBOOT feature by pressing any key on the host computer. Once the boot cycle has been stopped, the developer now has access to change the boot environmental variables on the software image. At the terminal window, the developer should type the following two lines, pressing the enter key after each line: setenv bootargs_base ‘set bootargs console=ttymxc0,115200 ${lcd}’ saveenv Once the change is saved (saveenv), the Quick Start board can be turned off and then back on, or the developer can type boot on the terminal to restart the boot process. The Quick Start board is now correctly configured for LCD operation. A note for developers: The LCD parameters are contained in the U‐BOOT code, and the recommended line to change the video output parameters only tells U‐BOOT to substitute the stored parameters into the boot process. If the developer wishes to enter the exact string of variables into the U‐BOOT code, the following line can be used instead of the first line above:
setenv bootargs_base ‘set bootargs console=ttymxc0,115200 video=mxcdi0fb:RGB24,SEIKO-WVGA
The above entry is all one line. After the line entry is made, the saveenv entry is also needed.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 84
PUBI – Public Use Business Information
7.3. LVDSDisplaySet(ComingSoon) For developers wishing to output video to a LVDS panel, there is an optional LVDS panel which can be purchased for use with the Quick Start board. The part number for the optional card is MCIMX‐LVDS, and may be purchased directly from Freescale.com. The LVDS Display kit comes with the panel, mounted in a frame, and a 15 inch cable that will connect directly to the LVDS connector (J9) on the Quick Start board. The LVDS panel can be used in parallel with the other video outputs (VGA, HDMI, LCD) giving the developer a second screen if desired. Figure 35 below shows the LVDS Display available. The LVDS display is the same panel used on the i.MX53 SMD Tablet. The LVDS module is manufactured by HannStar Display Corp and is part number HSD100PXN1‐A00‐C11. The two support legs can be inserted in the corresponding slots on the frame to allow the developer to chose any desired display orientation.
Figure 35. LVDS Display Kit
Place Holder Picture. Need a better one.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 85
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
In order to use the optional LVDS Display Panel with the Quick Start board, the environmental variables must be correctly set to support the card. This change needs to be done only one time, when the LVDS Panel is first used. The change requires the developer to use a host computer running a terminal window. When the power button is first pressed, the developer has 3 seconds to defeat the AUTOBOOT feature by pressing any key on the host computer. Once the boot cycle has been stopped, the developer now has access to change the boot environmental variables on the software image. At the terminal window, the developer should type the following two lines, pressing the enter key after each line: setenv bootargs_base ‘set bootargs console=ttymxc0,115200 ${lvds}’ saveenv Once the change is saved (saveenv), the Quick Start board can be turned off and then back on, or the developer can type boot on the terminal to restart the boot process. The Quick Start board is now correctly configured for outputting video to the LVDS panel. A note for developers: The LVDS sd parameters are contained in the U‐BOOT code, and the recommended line to change the video output parameters only tells U‐BOOT to substitute the stored parameters into the boot process. If the developer wishes to enter the exact string of variables into the U‐BOOT code, the following line can be used instead of the first line above:
setenv bootargs_base ‘set bootargs console=ttymxc0,115200 video=mxcdi0fb:RGB666,XGA ldb’
The above entry is all one line. After the line entry is made, the saveenv entry is also needed.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 86
PUBI – Public Use Business Information
8. MechanicalPCBInformation The overall dimensions of the i.MX53 Quick Start PCB are shown in Figure 36. Quick Start Board Dimensions.
3 Inches 3 Inches
Figure 36. Quick Start Board Dimensions The Printed Circuit Board was made using standard 8‐layer technology. The material used was FR‐4 Hi Temp. The board stack up is as follows:
Top Layer Ground‐1 Layer Signal‐1 Layer Power‐1 Layer Power‐2 Layer Signal‐2 Layer Ground‐2 Layer Bottom Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 87
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
The stack up information provided by the PCB Fabrication Facility is as shown in Table 28. Board Stack up information. Widths and thickness are shown in mils. Impedances are shown in Ohms. The material used in calculating this stack up was 370HR. Single End Trace Differential Pair Traces
Layer
Thickness
Descrip
tion
Copp
er Oz.
Trace Width
Calculated
Im
pedance
Target
Impe
dance
Reference
Plane
Trace Width
Space
Width
Diff Pairs
(Pitch)
Calculated
Im
pedance
Target
Impe
dance
Reference
Plane
0.70 Mask 1.20 Plating
1 0.60 Signal 0.50 8.50 50.32 50 2 4.75 5.25 10 100.82 100 2 3.25 73.94 75 2 6.25 4.75 11 89.51 90 2
5.00 Prepreg 2 0.60 GND 0.50
4.00 Core 3 0.44 Signal 0.37 3.75 6.25 10 89.69 90 2,4
3.25 49.60 50 2,4 3.00 6.00 9 99.88 100 2,4 3.00 Prepreg
4 0.60 Power 0.50 30.00 Core
5 0.60 Power 0.50 3.00 Prepreg
6 0.44 Signal 0.37 3.75 6.25 10 89.69 90 5,7 3.25 49.60 50 5,7 3.00 6.00 9 99.88 100 5,7 4.00 Core
7 0.60 GND 0.50 5.00 Prepreg
8 0.60 Signal 0.50 8.50 50.32 50 7 4.75 5.25 10 100.82 100 7 3.25 73.94 75 7 6.25 4.75 11 89.51 90 7 1.20 Plating 0.70 Mask 62.28 = Total Thickness
Table 28. Board Stack up information
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 88
PUBI – Public Use Business Information
9. BoardVerification The On Board Diagnostic Scan (OBDS) tool used by the factory acceptance test tools is included on the MicroSD card image that is shipped with the i.MX53 Quick Start board. If the original image is corrupted or over‐written by the software developer, a fresh image can be downloaded from the freescale.com/imxquickstart web site. To access the OBDS tool, a serial cable and a host PC running a terminal program (Tera Term, HyperTerminal, etc) will be required. After connecting the host terminal to the Quick Start board, press the power button on the board. Before U‐BOOT completes the Autoboot countdown (3 seconds) press any key on the host computer. This will stop the Ubuntu Kernel from continuing the boot process and allow the developer to access the code on the MicroSD card. On the host computer terminal window, type the following line: Ext2load mmc 0:1 0x70800000 /unit_tests/obds.bin After the prompt returns: Loading file “/unit_tests/obds.bin” from mmc device 0:1 (xxa1) XXXXXX bytes read Type: go 70800000 This will begin the OBDS diagnostic tool. The tool has 16 tests that it can perform. They are as follows: MAC Address confirmation Debug UART Test DDR3 Test USBH1 Enumeration Test (Upper Host Port) Secure Real Time Clock Test Dialog PMIC ID Test SATA Test I2C Device Test GPIO Test Ethernet Test I2S Audio Test LCD Daughter Card Test LVDS Display Test VGA Video Test HDMI Daughter Card Test MMC/SD Card Test
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 89
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
The first question that the user will be asked by the OBDS test is if the user would like to AUTORUN the OBDS test. A yes answer (y or Y) will keep the OBDS test from prompting the user for any test that does not require direct user action. Any other key press will cause the OBDS test to prompt for all tests. A yes answer to this question is primarily for mass testing of Quick Start boards. Single users of this test can run this test with prompts without significant loss of time. The tests are straight forward, and if a supporting piece of equipment is required, the test will prompt the user for it. In order to complete all the tests, you would need to have the following equipment: USB HOST1 Test – Attached USB device required SATA Test – Attached SATA device required. Ethernet Test – The Ethernet loop back test plug as described below is required. Head Phone Test – A set of earphones or speakers are required. LCD Test – The optional LCD Display card is required LVDS Test – The optional LVDS display kit is required VGA Video Test – Connection to a VGA monitor is required HDMI Test – The optional HDMI card is required MMC/SD Card slot – A full size SD card is required in card slot J5. If the developer does not have one or more of the above items, the test can easily be skipped when asked if the user would like to perform the test. A complete cycle of tests covers 16 different aspects of the board. When the last test is run, the OBDS tool will print out a summary of the test results. A failure in any one particular area would indicate that there is a hardware fault with the Quick Start board that should be addressed. If all tests pass, but the developer code does not function correctly, the problem is most likely with the code. A more detailed description of the tests is as follows:
1) MAC Address confirmation. The i.MX53 Processor reads the MAC Address programmed into the Processor eFUSEs and prints them out on the terminal window. The resulting print out should match the MAC address label on the Quick Start board. If the two numbers match, the test has passed.
2) UART Test. When the test is running, the test expects different characters to be input from the
keyboard of the host computer. After a character is input, the i.MX53 Processor receives the input, transmits to the terminal window the received character, and then asks the user to confirm that the character is correct by pressing the ‘x’ key. The test is exited by typing an ‘x’ as an input character.
3) DDR Test. The test writes predetermined data onto the DDR3 memory, reads those memory blocks back out, and then compares the two values for errors. If the values match, the test passes.
4) USBH1 Enumeration Test. Any USB device is plugged into the upper HOST connector (the lower port is connected to the USBOTG module). After confirming that a USB device is plugged in, the I.MX53 will read the device enumeration data and print it out on the terminal window. If the Processor cannot read enumeration information, the test fails.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 90
PUBI – Public Use Business Information
5) Secure Real Time Clock Test. The i.MX53 Processor checks to make sure the RTC clock is
counting. If the clock is counting, the test passes.
6) PMIC Device ID Test. The i.MX53 Processor attempts to communicate with the PMIC using the attached I2C channel. If the two devices communicate, the test passes.
7) SATA Test. The processor attempts to communicate with an attached SATA device. If the processor detects the internal 50 MHz clock signal and communications coming from an attached SATA device, the test passes.
8) I2C Test. The processor attempts to communicate with one of the I2C devices on the Quick Start
board. If communications complete correctly, the test passes.
9) GPIO Test. The Processor drives the USER LED light controlled by PATA_DA_1 (pin L3) alternately high and low. If the user light appears to blink, the test passes.
10) FEC Ethernet Test. The Processor drives a data packet out of the Ethernet Jack, into the loop back cable, and then receives the test packet back. If the received packet matches the sent packet, the test passes.
11) I2S Audio Test. The Processor gives a tone to the Audio CODEC. If the tone can be heard through both speakers of the attached headphones, the test passes. After the user requests the test to be run, the user is prompted to insert a headphone set into jack (J18). When the headphones are connected, the user presses the ‘y’ key to confirm the headphones are attached. A sound will play. The test will then prompt you to replay the tone if needed. If the tone is no longer needed, the test will then prompt for an answer as to whether the tone was heard or not.
12) LCD Display test. If this test is selected, an image will be displayed on the attached LCD card. Once the image is displayed, the test will prompt the user to confirm whether or not the image is seen. If the image is seen, the test passes.
13) LVDS Display test. If this test is selected, an image will be displayed on the attached LVDS Panel. Once the image is displayed, the test will prompt the user to confirm whether or not the image is seen. If the image is seen, the test passes.
14) VGA Video test. If this test is selected, an image will be displayed on the attached video monitor. Once the image is displayed, the test will prompt the user to confirm whether or not the image is seen. If the image is seen, the test passes.
15) HDMI test. If this test is selected, an image will be displayed on the attached video monitor. Once the image is displayed, the test will prompt the user to confirm whether or not the image is seen. If the image is seen, the test passes.
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 91
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
16) MMC/SD Test. If the user selects this test to be run, the user will be prompted to insert an
MMC/SD card into the full size SD Card slot (J5). When the user confirms that the card is present, the processor will attempt to read the current SD card settings and manufacturing information on the SD card. If the Processor can read this information, the test passes.
The only special equipment required to complete the bank of OBDS tests is the Ethernet Loop back cable. This can be purchased on line (single plug Ethernet Lookback Cable) or it can be created by the developer by cutting one end of an unneeded Ethernet cable and connecting the wire from pin 1 to the wire from pin3, and connecting the wire from pin 2 to the wire from pin 6. All other wires remain unconnected. The four wires used will be solid Green, solid Orange, Green/White stripe, and Orange/White stripe. The solid colors are connected together and the striped colors are connected together. While the solid colors will always be connected to pins 2 and 6, the specific pin a color is attached to will depend on which plug is used. The same is true for the striped wires connected to pins 1 and 3. A diagram of this cable is shown in Figure 37 below.
Figure 37. Ethernet Loopback Cable
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 92
PUBI – Public Use Business Information
10. Troubleshooting The i.MX53 Quick Start board does not have specific troubleshooting features designed into the board. The board has proven robust during the initial test and development periods and should provide years of good service to the developer if treated with due caution. The test pads that are included on the schematic and on the board were not specifically designed for testing, but were placed on the board for developers who wanted to make wire connections to specific pins that might not be available without the test pads. One basic troubleshooting technique that is available to developers is to measure the voltage rails outputs on all the rails coming from the PMIC. The subsection on PMIC voltage rails presents a diagram with points the developer can use to make measurements. A second basic troubleshooting technique would be to measure clock frequencies to ensure the clock are running correctly. The position of the crystals and oscillators are in the design section under the i.MX53 Applications Processor. Aside from actual hardware difficulties, the Table 29 presents some other issues that may help the developer solve technical difficulties: Symptoms Possible Problem Action No 5V power to the Quick Start board, no Green LED light.
Attached power supply is not within the 4.5V – 5.5V window.
Use the power supply that came with the Quick Start board kit.
Fuse F1 has blown. Use multimeter to check for open.
Replace the fuse with a new 3A, 0603 surface mount fuse.
Intermittent signal on Debug UART, or color issues on VGA video output.
Cold solder connection on connector pins have broken loose after several cable insertions.
Examine the pins on the affected connector (J8 or J16). If a pin can wiggle back and forth, a solder iron should be used to reconnect the pin. Note: There is epoxy over the pins to increase pin strength. The epoxy may need to be removed first.
No Debug information on the Host Computer Terminal Window.
Incorrect Serial Cable used (eg Null modem cable)
Verify that serial cable is correct.
Lower USB Host Port is not working correctly.
Quick Start board is attached to a Host device through the Micro‐B Connector.
Remove cable from Micro‐B connector if Lower USB Host Port operations is desired.
Table 29. Problem Resolution Table
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 93
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
10.1. PMICVoltageRailTestPoints To assist the developer in determining whether the PMIC voltage rails are outputting the correct voltage levels, Figures 38 and 39 show the output capacitor on each regulator output with the ground pin colored yellow and the power pin colored red. Tables 30 and 31 show the expected voltage value for each capacitor.
Figure 38. Regulator Output Capacitor Positions Bottom
Capacitor Regulator ValueC224 VBUCKMEM 1.5VC221 VBUCKPERI 2.5V
Table 30. Output Capacitors and Values BOTTOM
C221 C224
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 94
PUBI – Public Use Business Information
Figure 39. Regulator Output Capacitor Positions Top
Capacitor Regulator ValueC199 VDD_DIG_PLL 1.3VC214 VLDO9 1.5VC216 VLDO10 1.3VC213 VLDO8 1.8VC211 VLDO7 2.75VC194 VLDO3 3.3VC203 VLDO4 2.775VC210 VLDO6 1.3VC207 VLDO5 1.3VC196 VLDO1 1.3VC218 VDDCORE 2.5VC223 VBUCKPERI 2.5VC225 VBUCKMEM 1.5VC230 VBUCKPRO 1.3VC228 VBUCKCORE 1.1V
Table 31. Output Capacitors and Values TOP
C213
C213
C211
C194
C203
C210
C207
C196
C218
C199
C214 C216
C223C225
C230 C228
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 95
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
11. KnownIssues At the initial launching of the Quick Start board, the following issues are known to exist:
1) SATA boot will not function with the sample grade i.MX53 ICs (rev 2.0 prototype silicon). The problem is an IC problem related to using the internal SATA clock. Since the external clock components have been removed from the Quick Start board, the SATA boot feature is not usable. The work around is to initialize SATA with minimum code on a microSD card, then pass the boot process to the SATA drive early. This problem is being fixed with the rev 2.1 production silicon i.MX53 Processor.
2) There is a defect in the Video Processing Unit (VPU) of the i.MX53 Processor (rev 2.0). The
defect causes the DDR3 SDRAM to miscalculate some blocks in video processing resulting in defects observable on the video output in high processing modes (1080p). This defect is being corrected on the rev 2.1 production silicon i.MX53 processor. For initial production Quick Start boards, the VCC voltage is being raised to 1.35V to allow the VPU to process without errors. On rev 2.1 silicon, VCC will be returned to 1.3V (by removing the software patch). This is not a recommended solution for customer use, but is sufficient for development work on the Quick Start board.
3) The Dialog DA9053 PMIC rev AA silicon has a 1.2A limitation of the VDDOUT supply rail. This is the voltage supply for all the PMIC regulators. The i.MX53 demonstration software is drawing close to the 1.2A limit, and at times, voltage dips occur on the VDDOUT supply rail as the Quick Start board tries to draw more power than the PMIC can supply. This has led to some abrupt shutdowns in the testing cycle, as VDDOUT dips down below the allowed threshold. When it becomes available, the DA9053 rev BB silicon will increase the current limit to 1.8A. For the initial Quick Start boards, a 220 uF capacitor has been placed across JP19 pin2 and JP2 to smooth out sudden momentary drops in voltage. In addition, a MicroElectronics STTH2L06 has been soldered from the 5V_Main (Anode) to JP19 pin2 (Cathode) to provide a direct current path outside the normal PMIC switcher. For this reason, the switcher L13 inductor has been removed from these boards, preventing their use with an attached battery. This fix is only being used for the preliminary rev AA silicon. All boards affected with this modification (in addition to having an obvious capacitor and diode) are labeled “700‐26565 Rev D”
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 96
PUBI – Public Use Business Information
12. PCBComponentLocations To aid the developer in locating major components on the Quick Start board, their locations have been highlighted and annotated in the same way that the connectors have been highlighted. These pictures are presented as the following Figures: Figure 40. Major Component Highlights Top Figure 41. Major Component Highlights Bottom The Assembly Drawings for all component locations are shown in a picture format for easy reference when using this document. The actual Gerber artwork for the assembly drawings is available from the i.MX53 Quick Start web site. The Assembly drawings are shown in the following figures: Figure 42. Assembly Drawing Top Figure 43. Assembly Drawing Bottom
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 97
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
U2 i.MX53 Application Processor U20 Dialog DA9053 PMIC
U3 DDR3 SDRAM U23 MMA8450QT Accelerometer
U5 DDR3 SDRAM U24 RS232 UART Transceiver
U9 SGTL5000 Audio CODEC F1 3A Fuse
Figure 40. Major Component Highlights Top
U2
U5 U3
U9
U20U24
U23
F1
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 98
PUBI – Public Use Business Information
U1 3.2V Voltage Regulator
U4 DDR3 SDRAM
U6 DDR3 SDRAM
U17 Ethernet PHY
Figure 41. Major Component Highlights Bottom
U17
U1
U4 U6
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 99
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 42. Assembly Drawing Top
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 100
PUBI – Public Use Business Information
Figure 43. Assembly Drawing Bottom
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 101
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
13. Schematics The main portion of the schematics consist of 13 pages. These pages are shown here for reference purposes. They can be found in the original Cadence Allegro‐OrCAD format (.DSN file) and in a PDF format on the i.MX53 Quick Start web site. The following figures show the schematic pages: Figure 44. DC 5V INPUT Figure 45. MX53 POWER Figure 46. MX53 DDR3 MEMORY Figure 47. MX53 CONTROL Figure 48. MX53 USB Figure 49. MX53 SD INTERFACE Figure 50. MX53 AUDIO Figure 51. MX53 SATA Figure 52. MX53 VGA Figure 53. MX53 ETHERNET Figure 54. EXPANSION HEADER Figure 55. DA9053 PMIC Figure 56. DEBUG, ACCELEROMETER
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 102
PUBI – Public Use Business Information
Figure 44. DC 5V INPUT
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 103
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 45. MX53 POWER
SH27
0
C49
0.01
UF
C46
0.1U
F
C70
0.1U
F
VDD
A_1
V3
C50
0.01
UF
C47
0.1U
F
NVC
C_S
RTC
i.MX
53 -
POW
ER
U2E G
ND
_1A
1
GN
D_2
A2
GN
D_3
A11
GN
D_4
A13
GN
D_5
A18
GN
D_6
A22
GN
D_7
A23
GN
D_8
B1
GN
D_9
B11
GN
D_1
0B1
3
GN
D_1
1B1
8
GN
D_1
2B2
3
GN
D_1
3C
12
GN
D_1
4C
20
GN
D_1
5C
21
GN
D_1
6D
19
GN
D_1
7E1
9
GN
D_1
8F1
9
GN
D_1
9F2
0
GN
D_2
0F2
1
GN
D_2
1F2
2
GN
D_2
2G
7
VD
DG
P_1
G8
VD
DG
P_2
G10
VD
DG
P_3
G11
VD
DG
P_4
H7
VD
DG
P_5
H9
VCC
_1H
13
VCC
_2J1
4
VCC
_3J1
6
VCC
_4K1
3
VCC
_5K1
5
VCC
_6L1
4
VCC
_7L1
6
NV
CC
_EM
I_D
RA
M_1
H18
NV
CC
_EM
I_D
RA
M_2
K17
NV
CC
_EM
I_D
RA
M_3
N17
NV
CC
_EM
I_D
RA
M_4
P17
NVC
C_E
IM_M
AIN
_1U
9
NVC
C_E
IM_M
AIN
_2U
10
NVC
C_E
IM_S
ECU
7
NVC
C_L
CD
_1J6
SVC
CB2
2
NVC
C_C
SI
R7
NV
CC
_FEC
F11
NV
CC
_GPI
OF8
NV
CC
_JTA
GG
9
NVC
C_K
EY
PAD
F7
VDD
_AN
A_PL
LG
16
VDD
_DIG
_PLL
H17
NV
CC
_XTA
LV1
2
NVC
C_S
RTC
_PO
WV1
1
FAST
R_A
NA
E18
FAST
R_D
IGE1
7
VDD
_FU
SEG
15
VD
DA_
1G
12
VD
DA_
2M
7
NVC
C_R
ESE
TH
16
GN
D_2
3G
19
GN
D_2
4H
8
GN
D_2
5H
10
GN
D_2
6H
12
GN
D_2
7J9
GN
D_2
8J1
1
GN
D_2
9J1
3
GN
D_3
0J1
5
GN
D_3
1J1
7
GN
D_3
2J2
0
GN
D_3
3K
8
VD
DG
P_6
H11
VD
DG
P_7
J8
VD
DG
P_8
J10
VD
DG
P_9
J12
VD
DG
P_1
0K7
VD
DG
P_1
1K9
VD
DG
P_1
2K1
1
VCC
_8M
9
VCC
_9M
11
VC
C_1
0M
13
VC
C_1
1M
15
VC
C_1
2N
8
VC
C_1
3N
10
VC
C_1
4N
12
VC
C_1
5N
14
VC
C_1
6N
16
NV
CC
_PAT
AN
7N
VC
C_S
D1
H15
NV
CC
_SD
2H
14
VD
DA_
3M
17
VD
DAL
1F9
NV
CC
_CKI
HG
17
NV
CC
_NAN
DF
T12
SVD
DG
PB2
GN
D_9
4A
B22
GN
D_9
5AB
2
VD
DG
P_1
3L8
VD
DG
P_1
4L1
0
VD
D_R
EGG
18
VD
DG
P_1
5L1
2
NV
CC
_EM
I_D
RA
M_5
T18
GN
D_3
4K1
0
GN
D_3
5K1
2
GN
D_3
6K1
4
GN
D_3
7K1
6
GN
D_3
8K2
1
GN
D_3
9L7
GN
D_4
0L9
GN
D_4
1L1
1
GN
D_4
2L1
3
GN
D_4
3L1
5
GN
D_4
4M
8
GN
D_4
5M
10
GN
D_4
6M
12
GN
D_4
7M
14
GN
D_4
8M
16
GN
D_4
9N
9
GN
D_5
0N
11
GN
D_5
1N
13
GN
D_5
2N
15
GN
D_5
3P
7
GN
D_5
4P
8
GN
D_5
5P1
0
GN
D_5
6P1
2
GN
D_5
7P1
4
GN
D_5
8P1
6
GN
D_5
9P2
1
GN
D_6
0R
9
GN
D_6
1R
11
GN
D_6
2R
13
GN
D_6
3R
15
GN
D_6
4R
17
GN
D_6
5R
20
GN
D_6
6T8
GN
D_6
7T1
0
GN
D_6
8A
A11
GN
D_6
9T1
4
GN
D_7
0T1
6
GN
D_7
1U
15
GN
D_7
2U
19
GN
D_7
3V1
5
GN
D_7
4V1
8
GN
D_7
5V1
9
GN
D_7
6V2
0
GN
D_7
7V2
1
GN
D_7
8V2
2
GN
D_7
9W
19
GN
D_8
0Y
14
GN
D_8
1Y
15
GN
D_8
2Y
19
GN
D_8
3A
A15
GN
D_8
4A
A20
GN
D_8
5A
A21
GN
D_8
6AB
1
GN
D_8
7A
B18
GN
D_8
8A
B23
GN
D_8
9AC
1
GN
D_9
0AC
2
GN
D_9
1A
C18
GN
D_9
2A
C22
GN
D_9
3A
C23
VC
C_1
7P9
VC
C_1
8P1
1
VC
C_1
9P1
3
VC
C_2
0P1
5
VC
C_2
1R
8
VC
C_2
2R
10
VC
C_2
3R
12
VC
C_2
4R
14
VC
C_2
5R
16
VC
C_2
6T7
VC
C_2
7T9
VC
C_2
8T1
1
VC
C_2
9T1
3
VC
C_3
0T1
5
VC
C_3
1T1
7
VC
C_3
2U
8
VC
C_3
3U
18
VD
DA_
4U
12
NVC
C_L
CD
_2J7
C45
22U
F
C72
0.1U
F
C52
0.1U
F
NVC
C_X
TAL_
2V5
C69
0.1U
F
To V
BU
CK
PER
I@
2.5V
1A
max
.
VD
DG
P
SH9
0
C53
0.1U
F
VIO
HI_
2V77
5
SATA
_PH
Y_2
V5
3.3V
VLD
O5_
1V3
C54
0.1U
F
1.8V
1.8V
VLD
O8_
1V8
SH
25
0
THIS
MUS
T BE
PO
WER
ED U
P FI
RST
SATA
_1V
3
TP2
VUSB
_2V
5
C55
0.1U
F
C41
22U
F
SH
1
0
SH
29
0
C68
0.1U
F
R20
0.02
DN
P
C56
0.1U
F
VLD
O8_
1V8
VBU
CK
CO
RE
C35
0.22
UF
C16
0.22
UF
C12
0.22
UF
GN
D
C27 0.22
UF
GN
D
SD1_
3V3
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
C13
0.22
UF
GN
D
SH
2
0
C29 0.22
UF
VDD
AL_
1V3
C21
0.22
UF
VBU
CKM
EM
C44
0.1U
F
C37 0.22
UF
C14 0.22
UF
C51
22U
F
C57
0.1U
F
VPER
I_SW
VM
EM_S
W
R19
0
To V
BU
CK
PRO
@1.
3V 1
A m
ax.
To V
BU
CK
CO
RE
@0.
85-1
.3V
2A m
ax
C30 0.22
UF
VD
D_F
US
E
SH
3
0
SH
24
0
C58
0.1U
F
GN
D
IMX_
NV
CC
_XTA
L
FAST
R_S
IG
IMX_
VD
DA_
1V2
GN
D
VDD
_RE
G_2
V5
C22 0.22
UF
LVD
S_2
V5
R12
0
SH5
0
L3
120O
HM
DN
P
12
SH6
0
VIO
HI_
2V77
5
SVC
C
C71
22U
F
1.8V
C59
0.1U
F
DD
RQ
_1.5
V
TP1
To V
LDO
10_1
V3@
1.3V
250
mA
max
2.77
5V
C38
0.22
UF
C28
10U
F
SH7
0
GN
DC
65
22U
F
GN
D
NVC
C_X
TAL_
2V5
C60
0.1U
F
1.8V
DIG
_PLL
_IN
T
VDD
AL_
1V3
LCD
_3V
2
Pla
ce o
n T
OP
VCC
_1V
3
GN
D
SH8
0
C31 0.22
UF
1.8V
DD
R_1
.5V
L2
120O
HM
12
2.5V
To V
LDO
4_2V
775
@2.
775V
150
mA
max
.
VD
DA
_1V
3
3.3V
NV
CC
_SR
TC
C23 0.22
UF
C40
10U
F
C17 0.22
UF
VBU
CK
PRO
C39
0.22
UF
GN
D
R25
0
GN
D
1.2V
C32
0.22
UF
VDD
GP
VLD
O3_
3V3
C9
0.22
UF
FAS
TR_S
IGF
ASTR
_SIG
C61
0.1U
F
C24
0.22
UF
GN
D
C18 0.22
UF
GN
D
GN
D
C33
0.22
UF
GN
D
C10 0.22
UF
C43
0.22
UF
C25
0.22
UF
C19
0.22
UF
C42
0.22
UF
SH
21
0
DIG
_PLL
_1V
3
GN
D
GN
D
GN
DR
210
0
DN
P
GN
D
C34
0.22
UF
C11 0.22
UF
C26 0.22
UF
C64
0.22
UF
GN
D
R17
0.02
DN
P
1.8V
These signals are reserved for Freescale
manufacturing use only. User must tie both
connections to GND.
C62
0.1U
F
Out
puts
from
DA9
053 AU
DIO
_3V2
VLD
O1_
1V3_
RTC
SH11
0
VDD
_FU
SE
C63
0.1U
F
Customer Note:
Internal generation of VDD_ANA and VDD_DIG have been
proven to work correctly. For customer designs, it is
possible to remove VLDO6, VLDO8 and VLDO10 from
VDDAL, VDD_DIG_PLL, and VDDA respectively, and use
those LDO regulators for other purposes. VDDA and
VDDAL need to be connected to VDD_DIG_PLL
externally in that case.
VBU
CKP
ERI
R80
0D
NP
2.77
5VSVD
DG
P
SH
4
0
Note:
If the internal chip regulators for PLL
circuits are not used, R12 should be
1K Ohm to limit current to VDD_FUSE.
If the internal chip regulators are
supplied by VDD_REG_2V5,
R12 should be 0 Ohm.
VLD
O3_
3V3
SH13
0
VLD
O7_
2V75
C66
0.1U
F
To V
BU
CK
MEM
@1.
5V 1
A m
ax.
C15
22U
FVC
C_1
V3
SH26
0
VLD
O10
_1V3
C36
47U
F
AN
A_P
LL_1
.8V
SH
22
0
VDD
_RE
G_2
V5
C67
0.1U
F
VBUCKPERI_SUP
TVD
AC_2
V75
Pla
ce
on
TO
P
C48
0.01
UF
C20
47U
F
DD
R_1
.5V
GN
D
FEC
_3V2
VLD
O6_
1V3
DC
DC
_3V
2
Dra
win
g Ti
tle:
Size
Doc
umen
t N
umbe
rR
ev
Dat
e:S
heet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:F
IUO
:P
UB
I:
SC
H-2
6565
PD
F: S
PF-
2656
5C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day,
Feb
ruar
y 0
1, 2
011
MX5
3 PO
WER
415
___
___
X
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 104
PUBI – Public Use Business Information
Figure 46. MX53 DDR3 MEMORY
C81
0.1U
F
DR
AM_S
DW
E
EIM
_SD
BA1
EIM
_SD
BA0
DR
AM_A
7D
RAM
_A6
EIM
_SD
BA2
DR
AM_A
9D
RAM
_A8
DR
AM_A
11D
RAM
_A10
DR
AM_A
13D
RAM
_A12
DD
R_V
REF D
RAM
_SD
CLK
_1
C76
0.1U
F
EIM
_SD
OD
T0
DR
AM_D
QM
1
DR
AM
_D26
DR
AM
_D25
DR
AM
_D24
DR
AM
_D31
DR
AM
_D23
DR
AM
_D16
DR
AM
_D30
DR
AM
_D29
DR
AM
_D28
DR
AM
_D27
DR
AM
_D21
DR
AM
_D20
DR
AM
_D19
DR
AM
_D18
DR
AM
_D17
DR
AM
_D22
DR
AM_D
[15.
.0]
C10
4
0.01
UF
DR
AM_D
QM
1
C12
7
0.1U
F
DR
AM_D
QM
0
C82
0.01
UF
DR
AM_A
0
DR
AM_A
2D
RAM
_A1
DR
AM_S
DW
E
DR
AM_A
4D
RAM
_A3
EIM
_SD
BA0
DR
AM_A
6D
RAM
_A5
EIM
_SD
BA2
EIM
_SD
BA1
DR
AM_A
8D
RAM
_A7
EIM
_SD
OD
T1
DR
AM_A
10D
RAM
_A9
DD
RQ
_1.5
V
DR
AM_A
12D
RAM
_A11
DR
AM_A
13
DR
AM_D
QM
2
R26
470
DD
R_1
.5V
DD
RQ
_1.5
V
C83
0.1U
F
DR
AM_D
QM
3D
RAM
_DQ
M2
DR
AM_D
[31.
.16]
DD
R_1
.5V
DR
AM_D
[15.
.0]
C12
8
0.1U
F
C84
0.01
UFDR
AM_R
ESET
DR
AM_S
DW
E
DR
AM_D
[15.
.0]
EIM
_SD
BA1
EIM
_SD
BA0
EIM
_SD
BA2
C10
1
0.1U
F
DR
AM_D
QM
3
USE: ELPIDA EDJ2116DASE-DJ-F or MICRON MT41J128M16HA-15E
DR
AM_S
DQ
S3_B
DR
AM_S
DQ
S3
DR
AM_S
DQ
S2
DR
AM_S
DQ
S3_B
DR
AM_S
DQ
S2_B
C85
10U
F
R27
470
DR
AM_C
S0
C86
0.1U
F
R28
200
DR
AM_D
QM
3D
RAM
_DQ
M2
DR
AM_C
AL_M
X53
DR
AM_S
DC
KE0
C93
0.01
UF
DD
RQ
_1.5
V
C12
9
0.1U
F
DD
R_1
.5V
C91
10U
F
DR
AM_S
DQ
S0_B
DR
AM_S
DQ
S0
DR
AM_A
0
R30
0
R29
200
C87
0.1U
F
DR
AM_S
DC
KE0
DR
AM_C
S0
DD
RQ
_1.5
V
DR
AM_C
ASD
RAM
_RAS
C10
3
0.1U
F
R19
024
0
C95
0.01
UF
DR
AM_D
31
DR
AM_D
18
DR
AM_D
30
DR
AM_D
27
DR
AM_D
19
DR
AM_D
22
DR
AM_D
20
DR
AM_D
17
DR
AM_D
29
DR
AM_D
21
DR
AM_D
24
DR
AM_D
26
DR
AM_D
23
DR
AM_D
16
DR
AM_D
28
DR
AM_D
25
R31
0
C92
0.1U
F
DR
AM_A
1
DR
AM_C
S1
DR
AM_S
DC
LK_0
DR
AM_S
DC
LK_0
_B
DD
R_1
.5V
DR
AM_S
DC
KE1
DR
AM_R
ASD
RAM
_CAS
DR
AM_C
S1
DR
AM_A
2
C11
2
10U
F
DD
RQ
_1.5
V
R32
0
C88
0.1U
F
C11
9
0.1U
F
C97
0.01
UF
DR
AM_A
3
R19
124
0
DR
AM_S
DC
LK_0
_B
DR
AM_S
DC
LK_0
DR
AM_A
[13.
.0]
C94
0.1U
F
DR
AM_A
4
R33
0
DR
AM_S
DC
KE1
DD
RQ
_1.5
V
DR
AM_R
ASD
RAM
_CAS
Dra
win
g Ti
tle:
Size
Doc
umen
t N
umbe
rR
ev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssif
icat
ion:
FCP:
FIU
O:
PUBI
:
SOU
RC
E:S
CH
-265
65 P
DF:
SPF-
2656
5C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day,
Feb
ruar
y 01
, 201
1
MX5
3 D
DR3
515
___
___
X
EIM
_SD
OD
T0
DR
AM_A
5
C13
0
10U
F
C89
0.1U
F
C12
0
0.1U
F
DD
RQ
_1.5
V
R19
224
0
DD
R_V
REF
DD
R_V
REF
DR
AM_D
0
C96
0.1U
F
DR
AM_A
6
2G_D
DR
3_S
DR
AM_1
28M
X16
U3
MT4
1J12
8M16
HA-
15E
A0N
3
A1P7
A2P3
A3N
2
A4P8
A5P2
A6R
8
A7R
2
A8T8
A9R
3
BA0
M2
BA1
N8
BA2
M3
VDD1B2
VDD2D9
VDD3G7
VDD4K2
VDD5K8
VDD6N1
VDD7N9
VDD8R1
VDD9R9
VDDQ1A1
VDDQ2A8
VDDQ3C1
VDDQ4C9
VSS1A9
VSS2B3
VSS3E1
VSS4G8
VSS5J2
VSS6J8
VSS7M1
VSS8M9
VSS9P1
VSS10P9
VSS11T1
VSS12T9
VSSQ1B1
VSSQ2B9
VSSQ3D1
VSSQ4D8
VSSQ5E2
NC
_L1
L1
NC
_L9
L9
NC
_M7
M7
NC
_T7
T7
DQ
0E
3
DQ
1F
7
DQ
2F
2
DQ
3F
8
DQ
4H
3
DQ
5H
8
DQ
6G
2
DQ
7H
7
A10/
APL7
A11
R7
A12/
BCN
7
LDQ
SF
3
LDQ
SG
3
UD
QS
C7
UD
QS
B7
DQ
8D
7
DQ
9C
3
DQ
10C
8
DQ
11C
2
DQ
12A
7
DQ
13A
2
DQ
14B
8
DQ
15A
3
VDDQ5D2
VDDQ6E9
VDDQ7F1
VDDQ8H2
VDDQ9H9 VSSQ6
E8
VSSQ7F9
VSSQ8G1
VSSQ9G9
A13
T3
NC
_J9
J9N
C_J
1J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RES
ETT2
OD
TK1
VREF
CA
M8
VREF
DQ
H1
ZQL8
LDM
E7
UD
MD
3
C10
7
0.01
UF
DR
AM_S
DQ
S0
DR
AM
_D8
DR
AM
_D15
DR
AM
_D7
DR
AM
_D14
DR
AM
_D13
DR
AM
_D12
DR
AM
_D11
DR
AM
_D10
DR
AM
_D9
DR
AM
_D4
DR
AM
_D3
DR
AM
_D2
DR
AM
_D1
DR
AM
_D0
DR
AM
_D6
DR
AM
_D5
C11
8
10U
F
DR
AM_A
7D
RAM
_SD
CLK
_1
DR
AM_S
DC
LK_1
_B
C90
0.1U
F
DR
AM_D
14
DR
AM_D
1
DR
AM_D
10
DR
AM_D
3
DR
AM_D
9D
RAM
_D8
DR
AM_D
15
DR
AM_D
7
DR
AM_D
6D
RAM
_D5
DR
AM_D
2
DR
AM_D
0
DR
AM_D
13D
RAM
_D12
DR
AM_D
11
DR
AM_D
4
C12
1
0.1U
F
DD
R_V
RE
F
DR
AM_A
8
R19
324
0
DR
AM
_D[3
1..1
6]
DR
AM_S
DQ
S0_B
C11
3
0.1U
F
DR
AM_A
0
C10
9
0.01
UF
DR
AM_A
9
DR
AM_S
DQ
S1_B
DR
AM_S
DQ
S1
DR
AM_D
[31.
.16]
EIM
_SD
OD
T1
EIM
_SD
BA0
DR
AM_D
1
C98
10U
F
DR
AM_A
10
2G_D
DR
3_S
DR
AM_1
28M
X16
U4
MT4
1J12
8M16
HA-
15E
A0N
3
A1P7
A2P3
A3N
2
A4P8
A5P2
A6R
8
A7R
2
A8T8
A9R
3
BA0
M2
BA1
N8
BA2
M3
VDD1B2
VDD2D9
VDD3G7
VDD4K2
VDD5K8
VDD6N1
VDD7N9
VDD8R1
VDD9R9
VDDQ1A1
VDDQ2A8
VDDQ3C1
VDDQ4C9
VSS1A9
VSS2B3
VSS3E1
VSS4G8
VSS5J2
VSS6J8
VSS7M1
VSS8M9
VSS9P1
VSS10P9
VSS11T1
VSS12T9
VSSQ1B1
VSSQ2B9
VSSQ3D1
VSSQ4D8
VSSQ5E2
NC
_L1
L1
NC
_L9
L9
NC
_M7
M7
NC
_T7
T7
DQ
0E3
DQ
1F7
DQ
2F2
DQ
3F8
DQ
4H
3
DQ
5H
8
DQ
6G
2
DQ
7H
7
A10/
APL7
A11
R7
A12/
BCN
7
LDQ
SF3
LDQ
SG
3
UD
QS
C7
UD
QS
B7
DQ
8D
7
DQ
9C
3
DQ
10C
8
DQ
11C
2
DQ
12A7
DQ
13A2
DQ
14B8
DQ
15A3
VDDQ5D2
VDDQ6E9
VDDQ7F1
VDDQ8H2
VDDQ9H9 VSSQ6
E8
VSSQ7F9
VSSQ8G1
VSSQ9G9
A13
T3
NC
_J9
J9N
C_J
1J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RES
ETT2
OD
TK1
VREF
CA
M8
VREF
DQ
H1
ZQL8
LDM
E7
UD
MD
3
C10
6
0.1U
F
C12
2
0.1U
F
DR
AM_S
DQ
S1
DR
AM_D
2
DR
AM_A
11
R19
424
0
EIM
_SD
BA1
DR
AM_S
DQ
S0D
RAM
_SD
QS0
_B
DR
AM_S
DQ
S1_B
DR
AM_S
DQ
S1
C11
4
0.1U
F
EIM
_SD
BA0
DR
AM_A
12
DR
AM_A
1
DR
AM_D
3
DR
AM_A
2
i.MX
53 -
DDR
U2J
DR
AM_A
0M
19
DR
AM_A
1L2
1
DR
AM_A
2M
20
DR
AM_A
3N
20
DR
AM_A
5N
21
DR
AM_A
6M
22
DR
AM_A
7N
22
DR
AM_A
8N
23
DR
AM_A
9M
21
DR
AM_A
10K
19
DR
AM_A
11L2
2
DR
AM_A
12L2
0
DR
AM_A
13L2
3
DR
AM_A
14N
18
DR
AM_S
DBA
0R
19
DR
AM_S
DBA
1P
20
DR
AM_R
ASJ1
9
DR
AM_C
ASL1
8
DR
AM_S
DW
EL1
9
DR
AM_S
DC
KE0
H19
DR
AM_S
DC
KE1
T19
DR
AM_S
DC
LK_0
K23
DR
AM_S
DC
LK_0
_BK
22
DR
AM_C
S0K
18
DR
AM_C
S1P
19
DR
AM_S
DQ
S0H
23
DR
AM_S
DQ
S3Y
22
DR
AM_D
0H
20
DR
AM_D
1G
21
DR
AM_D
2J2
1
DR
AM_D
3G
20
DR
AM_D
4J2
3
DR
AM_D
5G
23
DR
AM_D
6J2
2
DR
AM_D
7G
22
DR
AM_D
8E
21
DR
AM_D
9D
21
DR
AM_D
10E
22
DR
AM_D
11D
20
DR
AM_D
12E
23
DR
AM_D
13C
23
DR
AM_D
14F
23
DR
AM_D
15C
22
DR
AM_D
16U
20
DR
AM_D
17T2
1
DR
AM_D
18U
21
DR
AM_D
19R
21
DR
AM_D
20U
23
DR
AM_D
21R
22
DR
AM_D
22U
22
DR
AM_D
23R
23
DR
AM_D
24Y
20
DR
AM_D
25W
21
DR
AM_D
26Y
21
DR
AM_D
27W
22
DR
AM_D
28A
A23
DR
AM_D
29V
23
DR
AM_D
30A
A22
DR
AM_D
31W
23
DR
AM_D
QM
0H
21
DR
AM_D
QM
1E
20
DR
AM_D
QM
2T2
0
DR
AM_D
QM
3W
20
DR
AM_S
DBA
2N
19
DR
AM_S
DQ
S0_
BH
22
DR
AM_S
DQ
S1D
23
DR
AM_S
DQ
S2T2
2
DR
AM_S
DQ
S3_
BY
23D
RAM
_SD
QS
2_B
T23
DR
AM_S
DQ
S1_
BD
22
DR
AM_S
DO
DT0
J18
DR
AM_S
DO
DT1
R18
DR
AM_S
DC
LK_1
_BP
23D
RAM
_SD
CLK
_1P
22
DR
AM_R
ESET
P18
DR
AM_C
ALIB
RAT
ION
M23
DR
AM_A
15M
18
DR
AM_A
4K
20
DD
R_V
REF
L17
DR
AM_A
3
EIM
_SD
OD
T0
DR
AM_S
DQ
S1_B
C10
5
10U
F
DR
AM_A
13
C73
0.1U
F
C10
8
0.1U
F
C11
1
0.01
UF
EIM
_SD
BA2
DR
AM_D
4
C12
3
0.1U
F
DR
AM_S
DQ
S2
DR
AM_S
DQ
S3_B
DR
AM_S
DQ
S3
DR
AM_S
DQ
S2_B
EIM
_SD
BA1
DD
R_V
REF
C77
0.1U
F
DR
AM_C
AL_D
DR
A
C11
5
0.1U
F
DR
AM_D
5
DR
AM_S
DQ
S2
DR
AM_C
LK0
DR
AM_R
AS
C12
4
10U
F
DR
AM_D
6
1) Data pins can be swapped
within each byte
2) Data bytes can be
swapped
3) DQMx and DQSx must
follow each byte
When swapping bytes 0 or 1
into 2 or 3, must then use
32 bit access. Cannot use
16-bit access.
C11
0
0.1U
F
NOTE:
DDR data pins can be
swapped for improved
routing according to the
following rules:
EIM
_SD
BA2
DD
R_V
REF
DR
AM_C
LK0#
C75
0.1U
F
DR
AM_C
AL_D
DR
BD
RAM
_RES
ET
DR
AM_S
DQ
S2_B
DR
AM_C
AS
DR
AM_D
7
C11
6
0.1U
F
C10
0
0.01
UF
C74
0.1U
F
DD
R_1
.5V
DR
AM_S
DC
LK_0
_BD
RAM
_SD
CLK
_0
DR
AM_C
LK1
DR
AM_D
10D
RAM
_D9
DR
AM_D
8
DR
AM_D
13D
RAM
_D12
DR
AM_D
11
DR
AM_D
15D
RAM
_D14
2G_D
DR
3_S
DR
AM_1
28M
X16
U5
MT4
1J12
8M16
HA-
15E
A0N
3
A1P7
A2P3
A3N
2
A4P8
A5P2
A6R
8
A7R
2
A8T8
A9R
3
BA0
M2
BA1
N8
BA2
M3
VDD1B2
VDD2D9
VDD3G7
VDD4K2
VDD5K8
VDD6N1
VDD7N9
VDD8R1
VDD9R9
VDDQ1A1
VDDQ2A8
VDDQ3C1
VDDQ4C9
VSS1A9
VSS2B3
VSS3E1
VSS4G8
VSS5J2
VSS6J8
VSS7M1
VSS8M9
VSS9P1
VSS10P9
VSS11T1
VSS12T9
VSSQ1B1
VSSQ2B9
VSSQ3D1
VSSQ4D8
VSSQ5E2
NC
_L1
L1
NC
_L9
L9
NC
_M7
M7
NC
_T7
T7
DQ
0E
3
DQ
1F
7
DQ
2F
2
DQ
3F
8
DQ
4H
3
DQ
5H
8
DQ
6G
2
DQ
7H
7
A10/
APL7
A11
R7
A12/
BCN
7
LDQ
SF
3
LDQ
SG
3
UD
QS
C7
UD
QS
B7
DQ
8D
7
DQ
9C
3
DQ
10C
8
DQ
11C
2
DQ
12A
7
DQ
13A
2
DQ
14B
8
DQ
15A
3
VDDQ5D2
VDDQ6E9
VDDQ7F1
VDDQ8H2
VDDQ9H9 VSSQ6
E8
VSSQ7F9
VSSQ8G1
VSSQ9G9
A13
T3
NC
_J9
J9N
C_J
1J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RES
ETT2
OD
TK1
VREF
CA
M8
VREF
DQ
H1
ZQL8
LDM
E7
UD
MD
3
DR
AM_C
AL_D
DR
DD
RAM
_RES
ET
DR
AM_S
DQ
S3
DD
R_V
REF
C78
0.1U
F
DR
AM_S
DW
E
DR
AM_A
5D
RAM
_A4
DR
AM_A
9D
RAM
_A8
DR
AM_A
7D
RAM
_A6
DR
AM_C
S1
DD
R_1
.5V
DR
AM_C
LK1#
DR
AM_C
S0
DR
AM_A
11D
RAM
_A10
C11
7
0.1U
F
DR
AM_D
17D
RAM
_D16
DR
AM_A
13D
RAM
_A12
DR
AM_D
20D
RAM
_D19
DR
AM_D
18
DR
AM_D
23D
RAM
_D22
DR
AM_D
21
DR
AM_R
AS
C12
5
0.1U
F
DR
AM_C
AS
DR
AM_C
AL_D
DR
C
DR
AM_R
ESET
DR
AM_S
DC
KE0
DR
AM_S
DC
LK_0
DR
AM_S
DC
LK_0
_B
EIM
_SD
OD
T1
C10
2
0.01
UF
2G_D
DR
3_S
DR
AM_1
28M
X16
U6
MT4
1J12
8M16
HA-
15E
A0N
3
A1P7
A2P3
A3N
2
A4P8
A5P2
A6R
8
A7R
2
A8T8
A9R
3
BA0
M2
BA1
N8
BA2
M3
VDD1B2
VDD2D9
VDD3G7
VDD4K2
VDD5K8
VDD6N1
VDD7N9
VDD8R1
VDD9R9
VDDQ1A1
VDDQ2A8
VDDQ3C1
VDDQ4C9
VSS1A9
VSS2B3
VSS3E1
VSS4G8
VSS5J2
VSS6J8
VSS7M1
VSS8M9
VSS9P1
VSS10P9
VSS11T1
VSS12T9
VSSQ1B1
VSSQ2B9
VSSQ3D1
VSSQ4D8
VSSQ5E2
NC
_L1
L1
NC
_L9
L9
NC
_M7
M7
NC
_T7
T7
DQ
0E3
DQ
1F7
DQ
2F2
DQ
3F8
DQ
4H
3
DQ
5H
8
DQ
6G
2
DQ
7H
7
A10/
APL7
A11
R7
A12/
BCN
7
LDQ
SF3
LDQ
SG
3
UD
QS
C7
UD
QS
B7
DQ
8D
7
DQ
9C
3
DQ
10C
8
DQ
11C
2
DQ
12A7
DQ
13A2
DQ
14B8
DQ
15A3
VDDQ5D2
VDDQ6E9
VDDQ7F1
VDDQ8H2
VDDQ9H9 VSSQ6
E8
VSSQ7F9
VSSQ8G1
VSSQ9G9
A13
T3
NC
_J9
J9N
C_J
1J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RES
ETT2
OD
TK1
VREF
CA
M8
VREF
DQ
H1
ZQL8
LDM
E7
UD
MD
3
DR
AM_D
25D
RAM
_D24
C79
0.1U
F
DR
AM_D
28D
RAM
_D27
DR
AM_D
26
DR
AM_D
30D
RAM
_D29
DR
AM_D
31
DR
AM_S
DC
LK_1
_B
DD
R_1
.5V
DR
AM_A
0
DR
AM_A
2D
RAM
_A1
DR
AM_A
4D
RAM
_A3
DD
RQ
_1.5
V
DR
AM_S
DW
E
DR
AM_A
6D
RAM
_A5
DD
R_1
.5V
DR
AM_A
8D
RAM
_A7
DR
AM_A
10D
RAM
_A9
DR
AM_A
12D
RAM
_A11
DR
AM_A
13
DD
RQ
_1.5
VDR
AM_D
QM
0
DR
AM_S
DC
KE1
DR
AM_R
ESET
C12
6
0.1U
F
DR
AM_S
DC
LK_1
DR
AM_S
DC
LK_1
_BD
RAM
_DQ
M0
DR
AM_D
QM
1
C80
0.01
UF
DR
AM_S
DC
LK_1
_BD
RAM
_SD
CLK
_1
DR
AM_A
1D
RAM
_A0
DR
AM_A
3D
RAM
_A2
C99
0.1U
F
DR
AM_A
5D
RAM
_A4
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 105
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 47. MX53 CONTROL
SATA_LED
BOOT
_CFG
1_3
BOOT
_CFG
1_1
BOOT
_CFG
1_0
EIM
_A21
8 EIM
_A22
8BO
OT_C
FG1_4
R37
4.7K
GN
D
R57
4.7K
LCD_LED
G
D
S
G S
D
Q12
BSS1
38D
W-7
BOOT
_CFG
1_5
AU
DIO
_IN
SATA_LEDA
GN
D
BOOT
_CFG
2_3
GN
D
R40
4.7K
P N
FDC6
321C
DUAL
FET
Q13
FDC
6321
C_N
L
G2
3
D1
6
G1
1
S22
D2
4
S15
VLD
O3_
3V3
R58
4.7K
C13
3
18pF
C13
4
18pF
SATA
_CLK
_GPE
N10
JTAG
_TD
O15
R81
470
5V_LED
D14
RE
D
A C
5V_M
AIN
R17
31.
0K
GN
D
SAT
A_IN
SYS_UP_A
VCC
GN
D
U22 NC
7SP
125P
5X
1 2 345
GN
D
Dra
wing
Titl
e:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP:
FIU
O:
PU
BI:
SO
UR
CE:
SCH
-265
65 P
DF
:SPF
-265
65C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day,
Feb
ruar
y 01
, 201
1
MX5
3 CO
NTRO
L
615
___
___
X
R48
0 DN
P
R17
41.
0K
GN
D
R17
51.
0K
R59
4.7K
R46
4.7K
VLD
O3_
3V3
R17
61.
0K
R17
747
0
R41
10K
GN
D
R17
847
0
SPD
IF_T
X13
GN
D
R18
31.
0KSYS_LED
R60
4.7K
GN
DA
UD
IO_3
V2
R38
0 DN
P
R18
41.
0K
JTA
G_M
OD
VLD
O3_
3V3
MX5
3_XT
AL
5V_M
AIN
CK
IH2
CK
IH1
Y1 24
MH
z
14 3
2
MX5
3_EX
TAL
VLD
O3_
3V3
R18
747
0
USER_LED
D16
LED
_GR
EEN
A C
"USER" 5V
_MA
IN
nVDD_FLT
USER_LED_A
TP5
nVD
D_F
AU
LT6,
14
PM
IC_S
TBY
_REQ
EIM
_EB0
8
R61
4.7K
BO
OT_
MO
DE0
"3.3V"
BO
OT_
MO
DE1
EIM
_EB1
8
G
D
S
G S
D
Q9
BSS1
38D
W-7
BOOT
_CFG
2_4
EIM
_DA
08
FLT_LEDA
R16
810
K
TES
T_M
OD
E
EIM
_DA
28
BOOT
_CFG
2_5
VLD
O3_
3V3
GN
D
EIM
_LBA
8
SAT
A_1V
3
R62
4.7K
BOOT
_CFG
2_6
GN
D
EIM
_DA
88
GN
D
GN
D
GN
D
R36
0 DN
P
EIM
_A20
8
GN
D
R49
1.0K
QZ1
32.7
68KH
Z21
GN
D
BOOT
_CFG
2_7
GN
D
C21
712
PF
DIS
P0_
CO
NTR
AST
11,1
3
GN
D
C21
912
PF
EIM
_A19
8
GN
D
R50
1.0K
GN
D
SW1_
10BO
OT_
MO
DE0
BOO
T_M
OD
E1
CPU
_EC
KIL
EIM
_A18
8G
ND
BOOT
_CFG
3_3
D15
BAT
760
2 1
"SATA"
EIM
_A16
8
R63
4.7K
CPU
_CKI
L
EIM
_DA
18
i.MX
53 -
CONTR
OL PIN
S
NVCC
_SRT
C
NVCC_JTAG NVCC_GPIO
NVCC
_XTA
L
NVCC_RESET
TVDAC_1
NVCC
_KEY
PAD
NVCC
_GPI
O
NVCC
_SRT
C
NVCC
_CKI
H
U2C
JTAG
_TC
KD
9
JTAG
_TM
SA8
JTA
G_T
DI
B8
JTAG
_TD
OA7
JTAG
_TR
STB
E9
JTAG
_MO
DC
9
GPI
O_0
C8
GPI
O_1
B7
GPI
O_2
C7
GPI
O_3
A6
GPI
O_4
D8
GPI
O_5
A5
GPI
O_6
B6
GPI
O_7
A4
BO
OT_
MO
DE0
C18
BO
OT_
MO
DE1
B20
PO
R_B
C19
RES
ET_
IN_B
A21
CKI
H1
B21
EC
KIL
AC10
TEST
_MO
DE
D17
XTAL
AC11
EXTA
LAB
11
PM
IC_S
TBY
_RE
QW
15
PM
IC_O
N_R
EQ
W14
GPI
O_8
B5
GPI
O_9
E8C
KIH
2D
18
GP
IO_1
0W
16
GP
IO_1
1V1
7
GP
IO_1
2W
17
GP
IO_1
3AA
18
GP
IO_1
4W
18
GP
IO_1
6C
6
GP
IO_1
7A3
GP
IO_1
8D
7
GP
IO_1
9B4
CKI
LAB
10
SW3 TL
1015
AF16
0QG
12
RES
ET
EIM
_DA
78
JTAG
_TM
S15
BOOT
_CFG
3_4
VBU
CKP
RO
EIM
_DA6
8
"VGA"
GP
IO_0
(CLK
0)9,
13
BOOT
_CFG
3_5
JTAG
_TD
I15
GN
D
R64
4.7K
VD
DC
OR
E
GN
D
JTAG
_TC
K15
SW
2
TL10
15A
F160
QG
12
"LCD"
R82
10K
JTAG
_nTR
ST15
VLD
O8_
1V8
R65
4.7K
R17
9
1.0K
FLT_LED
SW1
SW_DIP-10/SM
DN
P
123456789
1817161514131211 10
1920
MX5
3_nO
NKE
YnO
NKE
Y/K
EEPA
CT
6,14
5V_M
AIN
D1
LED
_GR
EEN
A C
SW
1_D
SW
1_8
SW
1_7
D9
LED
_GR
EEN
A C
R18
1
1.0K
SW4 TL
1015
AF16
0QG
12
SW5 TL
1015
AF16
0QG
12
USE
R_U
I18
TVD
AC_2
V75
USE
R_U
I28
USER
DEF
INED
BUT
TONS
USER
DEF
2
USER
DEF
1
GN
D
VLD
O8_
1V8
VLD
O3_
3V3
VLD
O8_
1V8
VLD
O8_
1V8
R18
0
1.0K
GN
D
C25
3
2.2U
F
WD
T_O
UTP
UT
JTAG
_nSR
ST15
nRE
SET
R21
510
0K
GN
D
R13
47K
WATCHDOG TIMER
RESET TRIGGER
TP3
R10
10K
PM
IC_O
N_R
EQ
nRE
SET
14
BOOT
_CFG
1_6
BOOT
_CFG
1_7
GN
D
LCD
_3V2
BO
OT
FRO
M S
D/M
MC
R18
2
1.0K
I2C
3_SD
A11
I2C
3_S
CL
11R
198
1.0K
VLD
O3_
3V3
VLD
O8_
1V8
PC
LOC
K13
nVD
D_F
AU
LT6,
14
R22
14.
7KR
222
4.7K
R51
10.0
K
VDD_FLT
R52
10.0
K
R47
4.7K
1.8V
SY
S_U
P14
"PMIC PWR"
"5V PWR"
GN
D
nON
KEY
/KEE
PAC
T6,
14
WD
T_O
UT_
FLT
USE
R_I
N
R34
10K
5V_M
AIN
1.8V
C13
1
0.1U
F
R53
4.7K
R14
200K
DN
P
VGA_LED
R35
10K
D10
BLU
E
A C
TV_I
N
"FAULT"
D11
BLU
E
A C
AUDIO_LED
SW
1_2
D12
BLU
E
A C
R45
10M
DN
PD
13B
LUE
A C
WD
T_O
UTP
UT
VLD
O8_
1V8
PMIC
_ON
_REQ
A
C13
2
0.1U
F
R54
4.7K
VGA_LEDA
R44
10K
LCD
_IN
GN
D
R39
10K
TP4
AUDIO_LEDA
R21
610
K
R21
710
K
R21
810
K
R21
910
K
R22
010
K
US
ER_L
ED_E
N8
G
D
S
G S
D
Q10
BSS1
38D
W-7
R55
4.7K
nON
KEY
/KEE
PAC
T6,
14
1.8V
GN
D
R42
49.9
DN
P
R43
49.9
DN
P
nIR
Q14
BOO
T O
PTIO
N TA
BLE
5V_M
AIN
SYS_LED_A
PWR
G
D
S
G S
D
Q11
BSS1
38D
W-7
R56
4.7K
SW
1_6
LCD_LEDA
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 106
PUBI – Public Use Business Information
Figure 48. MX53 USB
R19
910
R66
100
R70
6.04
K
R71
6.04
K
US
B_H
OST
5V
Q15
2N70
02
3
1
2
5V_M
AIN
DC
DC
_3V
2
GN
D
C23
91.
0UF
C24
01.
0UF
FEC
_US
B_S
HIE
LD12
GN
D
DC
DC
_3V
2
US
B_H
2_5V
R18
510
0
GN
D
US
B_H
1_V
BUS
C13
8
0.1U
F
C13
6
0.1U
F
R18
610
0
US
BH
OS
T_D
P
USB
_HO
ST5
V
USB
_HO
ST5
V
R68
1.0
R69
1.0
C13
9
0.1U
F
R72
1.0
C14
2
0.1U
F
GN
D
R73
1.0
GN
D
GN
D
R19
53.
3K
R19
63.
3K
US
BCO
MB5
3_D
NG
ND
SH
28
0
EXT
_US
B5V
Q14
IRLM
L640
1
1
32
US
BCO
MB5
3_D
P
USB
_HO
ST5
V_E
N
EXT
_US
B5V
US
BC
OM
B_D
N
D17
SR
05
2 143
D18
SR
05
2 143
5V_M
AIN
US
BC
OM
B_D
P
US
B_P
WR
EN
8
US
B_O
TG_V
BU
S
Dra
win
g Ti
tle:
Siz
eD
ocum
ent
Num
ber
Rev
Dat
e:Sh
eet
of
Pag
e Ti
tle:
ICAP
Cla
ssif
icat
ion:
FCP
:F
IUO
:P
UBI
:
SO
UR
CE:
SCH
-265
65
:SPF
-265
65C
MC
IMX5
3-Q
UIC
KS
TAR
T
C
Tues
day
, Fe
brua
ry 0
1, 2
011
MX5
3 US
B
715
___
___
X
L5
90O
HM
21 4
3
US
B M
ICR
O-B
DEV
ICE
ON
LY
L6
90O
HM
21 4
3
US
B_H
1_R
RER
EXT
US
BCO
MB_
DN
GN
D
US
BCO
MB_
DP
Layout: Route 90ohm DIFF pairs on top layer only.
F2
1.1A
1 2
USB
OTG
_C_V
BUS
L7 120O
HM
12U
SBH
OS
T53_
DN
J3 4734
6-00
01
11
22
33
44
55
G16
G27
G38
G49 G510 G611
L9 120O
HM
12
TP6
US
BHO
ST5
3_D
P
TP8
US
BC
OM
B53
_DP
US
B_H
1_G
PAN
AIO
US
BC
OM
B53
_DN
GN
D
US
B_O
TG_G
PAN
AIO
GN
DG
ND
US
B_O
TG_V
DD
A25
_UN
FLT
US
B_O
TG_V
DD
A25
C13
7
2.2U
F
L4
120O
HM
12
VUS
B_2
V5
VD-
D+G
VD-
D+G
HY
BRID
DU
AL
USB
+ R
J45
J2A
B1
B2
B3
B4
S1 T1 T2 T3 T4
S4
S3
S2
US
B_O
TG_V
DD
A33
US
BHO
ST_D
N
US
BH
OS
T53_
DP
GN
D
US
BH
OS
T_D
N
US
BC
OM
B_D
PU
SB
CO
MB
_DN
GN
D
GN
D
i.MX53 USB
U2G
US
B_O
TG_V
BU
SE1
5
USB
_OTG
_ID
C16
US
B_O
TG_V
DD
A25
F14
US
B_O
TG_D
NA1
9
US
B_O
TG_V
DD
A33
G14
US
B_O
TG_D
PB1
9
US
B_O
TG_R
RE
FEXT
D16
US
B_O
TG_G
PA
NA
IOF1
5
USB
_H1_
GP
AN
AIO
A16
USB
_H1_
RR
EFE
XTB1
6
US
B_H
1_D
PA1
7
US
B_H
1_V
DD
A33
G13
US
B_H
1_D
NB1
7U
SB
_H1_
VD
DA
25F1
3
USB
_H1_
VB
US
D15
GN
D
C14
1
0.01
UF
B
OTT
OM
U
SB
HO
ST
SH
AR
ED W
ITH
US
B D
EVIC
E
GN
D
5V_M
AIN
GN
DG
ND
GN
D
US
B_H
1_V
DD
A25
_UN
FLT
ES
D P
rote
ctio
n
C14
0
2.2U
F
US
B_H
1_VD
DA
25
VUS
B_2V
5L8
120O
HM
12
C13
5
1000
pf
US
B_O
TG_I
D
US
B_H
1_V
DD
A33
US
B_O
TG_R
RE
FEX
T
USB
HO
ST_D
P
US
BH
OS
T53_
DN
C24
2
100U
F
US
B_H
1_5V
US
B_H
ST5
V
L19
120O
HM
12
US
BOTG
_C_G
ND
C24
3
100U
F
R20
04.
7K
Not
e:1)
The
Low
er U
SB
Hos
t Jac
k an
d th
eM
icro
US
B D
evic
e Ja
ck a
re c
ross
conn
ecte
d. T
he u
ser c
an p
lug
one
cabl
e in
to e
ither
jack
, but
can
not
plug
cab
les
into
bot
h ja
cks
at th
esa
me
time.
GN
D
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 107
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 49. MX53 SD INTERFACE
SD3_
DA
TA3
SD1_
3V3
SD1_
3V3
FEC
_MD
IO12
J4
SD
/MM
C S
KT
DA
T21
CD
/DAT
32
CM
D3
VDD
4
CLK
5
VSS
6
DA
T07
DA
T18
GND1SH1
GND2SH2
GND3SH3
GND4SH4
SD1_
CM
D
1.8V
1.8V
1.8V
1.8V
1.8V
US
B_PW
RE
N7
SD1_
CLK
SD IN
TER
FACE
S
FEC
_RXD
012
SD1_
DA
TA0
SD1
FEC
_RXD
112
SD3_
CLK
US
ER_L
ED
_EN
6
SD1_
DA
TA1
FEC
_CR
S_D
V12
SD3_
CM
D
SD3
FEC
_RX_
ER12
SD1_
DA
TA2
i.MX
53 -
MIS
C.
NVCC_FEC NVCC_KEYPAD
NVCC_SD1 NVCC_SD2
NVCC_PATA
U2B
KEY
_CO
L0C
5
KEY
_CO
L1E
7
KEY
_CO
L2C
4
KEY
_CO
L3F
6
KEY
_CO
L4E
5
KEY
_RO
W0
B3
KEY
_RO
W1
D6
KEY
_RO
W2
D5
KEY
_RO
W3
D4
KEY
_RO
W4
E6
SD
1_C
MD
F18
SD1_
CLK
E16
SD1_
DA
TA0
A20
SD1_
DA
TA1
C17
SD1_
DA
TA2
F17
SD1_
DA
TA3
F16
SD
2_C
MD
C15
SD2_
CLK
E14
SD2_
DA
TA0
D13
SD2_
DA
TA1
C14
SD2_
DA
TA2
D14
SD2_
DA
TA3
E13
FEC
_CR
S_D
VD
11F
EC_M
DC
E10
FEC
_MD
IOD
12
FEC
_RE
F_C
LKE1
2
FEC
_RXD
0C
11
FEC
_RX_
ER
F12
FEC
_RXD
1E1
1
FEC
_TX_
ENC
10
FEC
_TXD
0F1
0
FEC
_TXD
1D
10
PATA
_BU
FFE
R_E
NK
4
PATA
_CS_
0L5
PATA
_CS_
1L2
PATA
_DA_
0K
6
PATA
_DA_
1L3
PATA
_DA_
2L4
PATA
_DA
TA0
L1
PATA
_DA
TA1
M1
PATA
_DA
TA2
L6
PATA
_DA
TA3
M2
PATA
_DA
TA4
M3
PATA
_DA
TA5
M4
PATA
_DA
TA6
N1
PATA
_DA
TA7
M5
PATA
_DA
TA8
N2
PATA
_DA
TA9
N3
PATA
_DAT
A10
N4
PATA
_DAT
A11
M6
PATA
_DAT
A12
N5
PATA
_DAT
A13
N6
PATA
_DAT
A14
P6
PATA
_DAT
A15
P5
PATA
_DIO
RK
3
PAT
A_D
IOW
J3
PATA
_DM
ACK
J2
PATA
_DM
AR
QJ1
PATA
_IN
TRQ
K5
PATA
_IO
RD
YK
1
PATA
_RE
SET_
BK
2
SD1_
DA
TA3
C14
3
0.1U
F
FEC
_TXD
012
R85
4.7K
R86
4.7K
Dra
wing
Titl
e:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP:
FIU
O:
PUBI
:
SO
UR
CE:
SC
H-2
6565
PD
F:S
PF-2
6565
C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day,
Feb
ruar
y 0
1, 2
011
MX5
3 SD
INTE
RFAC
E
815
___
___
X
FEC
_TXD
112
C14
5
0.1U
F
VLD
O3_
3V3
FEC
_TX_
EN
12
I2C
2_SD
A9,
11,1
3
FEC
_MD
C12
I2S
_DIN
9
VLD
O3_
3V3
FEC
_nR
ST12
SD1_
CD
R10
810
KD
NP
SD1_
3V3
SD
1_C
D
CSI
0_R
STB
13C
SI0_
PW
DN
13
C14
4
10U
F
I2C
2_SC
L9,
11,1
3
R84
10K
DN
P
I2S
_DO
UT
9
SD
3_C
LK
GN
D
GN
D
SD1_
DAT
A3
US
ER_U
I26
US
ER_U
I16
GN
D
C14
6
10U
F
DC
DC
_3V2
SD
3_C
D
DC
DC
_3V
2
SD
3_D
ATA
7
SD
3_D
ATA
5
SD1_
CM
D
GN
D
SD
3_D
ATA
0
SD
3_C
MD
SD
3_W
P
I2S
_LR
CLK
9SD
1_D
ATA1
SD
3_D
ATA
1
SD
3_D
ATA
4
SD
3_D
ATA
6
SD
3_D
ATA
2
SD1_
DAT
A2
GN
D
SD1_
CLK
GN
D
SD
3_D
ATA
3
I2S
_SC
LK9
HE
ADP
HO
NE_
DE
T_B
9M
IC_D
ET_B
9
J5
CO
NN
CR
D 1
9
DA
T29
DA
T31
CM
D2
VSS1
3
VDD
4
CLK
5
VSS2
6
DA
T07
DA
T18
DA
T410
DA
T511
DA
T612
DA
T713
CD
14G
ND
116
WP
15G
ND
217
GN
D3
18
GN
D4
19
SD3_
DA
TA4
R97
10K
DN
P
SD3_
DA
TA5
SD3_
DA
TA6
SD3_
DA
TA7
FEC
_REF
_CLK
10,1
2
R76
10K
MX_
VG
A_H
SY
NC
11
EIM
_A20
6E
IM_A
196
EIM
_DA1
6E
IM_D
A06
MX_
VG
A_V
SYN
C11
EIM
_DA7
6E
IM_D
A66
EIM
_DA2
6
EIM
_EB0
6
EIM
_LB
A6
EIM
_DA8
6
EIM
_A16
6
EIM
_A18
6
EIM
_EB1
6
SD3_
DA
TA0
EIM
_A21
6E
IM_A
226
DIS
P0_P
OW
ER
_EN
13
DIS
P0_R
ESET
13
R14
4
0
SD3_
CD
R14
5
0
EIM
_OE
BOOT_CFG1_0
EIM
_RW
SD3_
WP
BOOT_CFG2_3
BOOT_C
FG1_5
BOOT_C
FG1_4
BOOT_C
FG1_3
BOOT_C
FG1_1
SH
32
0BOOT_CFG2_7
BOOT_CFG2_6
BOOT_CFG2_5
BOOT_CFG2_4
DIS
P0_n
CS
113
SD
CA
RD
_VD
D
BOOT_CFG3_5
BOOT_CFG3_4
BOOT_CFG3_3
R21
122
R21
222
i.MX
53 - E
IM
NVCC_EIM_MAINNVCC_EIM_SECNVCC_EIM_MAINNVCC_EIM_MAIN NVCC_NANDF
U2A
EIM
_OE
V8
EIM
_WA
ITAB
9
EIM
_BC
LKW
11
EIM
_LB
AAA
6
EIM
_RW
AB4
EIM
_EB
0AC
3
EIM
_EB
1AB
5
EIM
_EB
2Y
3
EIM
_EB
3Y
4
EIM
_CS
0W
8
EIM
_CS
1Y
7
EIM
_A16
AA5
EIM
_A17
V7
EIM
_A18
AB3
EIM
_A19
W7
EIM
_A20
Y6
EIM
_A21
AA4
EIM
_A22
AA3
EIM
_A23
V6
EIM
_A24
Y5
EIM
_A25
W6
EIM
_D16
U6
EIM
_D17
U5
EIM
_D18
V1
EIM
_D19
V2
EIM
_D20
W1
EIM
_D21
V3
EIM
_D22
W2
EIM
_D23
Y1
EIM
_D24
Y2
EIM
_D25
W3
EIM
_D26
V5
EIM
_D27
V4
EIM
_D28
AA1
EIM
_D29
AA2
EIM
_D30
W4
EIM
_D31
W5
EIM
_DA
0Y
8
EIM
_DA
1AC
4
EIM
_DA
2AA
7
EIM
_DA
3W
9
EIM
_DA
4AB
6
EIM
_DA
5V9
EIM
_DA
6Y
9
EIM
_DA
7AC
5
EIM
_DA
8AA
8
EIM
_DA
9W
10
EIM
_DA1
0AB
7
EIM
_DA1
1AC
6
EIM
_DA1
2V1
0
EIM
_DA1
3AC
7
EIM
_DA1
4Y
10
EIM
_DA1
5AA
9
NA
ND
F_W
E_B
AB8
NA
ND
F_R
E_B
AC8
NAN
DF_
ALE
Y11
NAN
DF_
CLE
AA10
NA
ND
F_W
P_B
AC9
NAN
DF_
RB
0U
11
NAN
DF_
CS
0W
12
NAN
DF_
CS
1V1
3
NAN
DF_
CS
2V1
4
NAN
DF_
CS
3W
13
BOOT_C
FG1_7
BOOT_C
FG1_6
DIS
P0_S
ER_S
CLK
13D
ISP0
_SER
_MIS
O13
DIS
P0_S
ER_R
S13
DIS
P0_S
ER_M
OSI
13
DIS
P0_S
ER_n
CS
13
SD
3_C
LK_A
DIS
P0_R
D11
,13
DIS
P0_W
R13
DIS
P0_n
CS
013
SD
1_C
LK_A
SD1_
DAT
A0
LCD
_BLT
_EN
11
SD3_
DA
TA1
R87
10K
AC
CL_
EN15
AC
CL_
INT2
_IN
15A
CC
L_IN
T1_I
N15
R88
10K
R89
10K
SD3_
DA
TA2
FEC
_nIN
T12
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 108
PUBI – Public Use Business Information
Figure 50. MX53 AUDIO
MIC
GN
D_A
NAL
OG
C15
0
0.1U
F
C15
2
0.1U
F
C15
3
0.1U
F
GN
D_A
NA
LOG
AUD
IO_H
P_V
GN
DTP
22
HP
_DE
T_ES
D
J6
AUD
_55
51
13
34
46
6
AUD
IO_3
V2
3.2V
DET
ECTI
ON
LEV
EL
J18 AU
D_5
55
11
33
44
66
HEA
D_R
IGH
T
R10
4
33
HP
_L_E
SD
I2C
2_S
DA
8,11
,13
I2S_
SC
LK8
HEA
D_L
EFT
HP
_R_E
SD
I2S_
LRC
LK8
I2S_
DO
UT
8I2C
2_S
CL
8,11
,13
I2S_
DIN
8
C15
1
1.0U
F
GPI
O_0
(CLK
0)6,
13
R10
1
2.2K
HEA
DP
HO
NE_
DET
_B8
C14
9
4.7u
F
MIC
_R_E
SD
C14
7
0.1U
F
Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICA
P C
lass
ifica
tion:
FC
P:FI
UO
:PU
BI:
SOU
RC
E:SC
H-2
6565
PD
F:SP
F-2
6565
C
MC
IMX5
3-Q
UIC
KST
ART
C
Wed
nesd
ay,
Janu
ary
12, 2
011
MX5
3 AU
DIO
915
___
___
X
L20
220O
HM
L21
220O
HM
L22
220O
HM
DN
P
L23
220O
HM
TP9
L24
220O
HM
L25
220O
HM
AUDIO_VDDD
MIC
BIAS
AUD
IO_3
V2
+
C15
4
220U
F
GN
DL10 12
0OH
M
12
+
C15
7
220U
F
GN
D
MIC
_DET
_B8
AUD
IO_V
AG
AUD
IO_C
PFI
LT
MIC
_DET
_ESD
SH
12
0 GN
D_A
NAL
OG
Note:
To support a MONO Headset with MIC, populate L22M
IC
GN
D
HP_
L
HP_
R
GN
D
GN
D_A
NA
LOG
MIC
_IN H
EAD
_RIG
HT
HP
_R
Hea
dp
hon
e
HP
_L
MIC
BIAS
MIC
_L_E
SD
U9
SG
TL50
00 3
2QFN
I2S_
SC
LK24
NC
522
LIN
EIN
_L14
CPF
ILT
18
VDDIO20
NC
419
SY
S_M
CLK
21
I2S_
DO
UT
25
I2S_
DIN
26
HP_
L6
CTR
L_D
ATA
27
NC
628
CTR
L_C
LK29
GND11
NC
18
HP_
R2
GND23
VDDA5 LI
NE
OU
T_L
12
LIN
EOU
T_R
11
MIC
15
NC
317
LIN
EIN
_R13
AGND7
I2S_
LRC
LK23
VDDD30
CTRL_ADR0_CS31
CTRL_MODE32
HP_
VGN
D4
NC
29
VAG
10
MIC
_BIA
S16
GND3-PAD33
AUD
IO_V
DD
A
AUD
IO_3
V2
R17
010
K
Audio CODEC
R17
110
K
C14
8
0.1U
F
MIC
GN
D
AUD
_SY
S_M
CLK
3.3V
DET
ECTI
ON
LEV
EL
TP10
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 109
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 51. MX53 SATA
C16
60.
01U
F
C16
70.
01U
F
SATA
C16
90.
01U
F
NOTE: Internal SATA clock reference was
confirmed on tapeout T02.0. Optional
parts have been removed from
further production runs.
C16
810
PF
DN
P
Dra
wing
Titl
e:
Size
Doc
umen
t N
umbe
rR
ev
Dat
e:Sh
eet
of
Page
Titl
e:
ICA
P C
lass
ifica
tion:
FCP:
FIU
O:
PUBI
:
SOU
RC
E:S
CH
-265
65 P
DF:
SPF
-265
65C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day,
Feb
ruar
y 0
1, 2
011
MX
53 S
ATA
1015
___
___
X
C17
010
PF
DN
P
R11
219
1
SATA
_REF
CLK
M
SATA
_RXP
SATA
_TXP
SATA
_TXN
SATA
_RXN
100
Ohm
Diff
eren
tial P
airs
SATA
_REF
i.MX53 SATA
U2F VP
H1
A9S
ATA
_TXM
B10
SATA
_TXP
A10
SAT
A_R
XPB1
2
SAT
A_R
XMA1
2
SATA
_REX
TC
13
SATA
_REF
CLK
MA
14SA
TA_R
EFC
LKP
B14
VP1
A15
VPH
2B9
VP2
B15
SAT
A_R
XP_C
ON
DIN
DO
UT
+
DO
UT
-
VC
C
GN
D
U11
FIN
1001
M5
DN
P
1 2
345
DC
DC
_3V
2
SAT
A_T
XP_C
ON
SAT
A_R
EFC
LKP
SAT
A_C
LK_O
E
SATA
_RE
F_C
LK
DC
DC
_3V2
To V
LDO
5_1V
3@
1.3V
150
mA
max
SATA
_PH
Y_2
V5
To V
BU
CK
PER
I@
2.5V
1A
max
.SA
TA_1
V3
X1 50M
Hz
OU
T3
GN
D2
VC
C4
OE
1
J7
CO
N 7
SA
TA
GN
D1
TXp
2TX
n3
GN
D4
RXn
5R
Xp6
GN
D7
SAT
A_R
XN_C
ON
SAT
A_T
XN_C
ON
R11
010
K
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
GN
D
GN
D
GN
D
GN
D
R11
110
0D
NP
SAT
A_C
LK_G
PEN
6
FEC
_RE
F_C
LK8,
12
R19
70 D
NP
C16
4
0.1U
F
Mou
nt th
ese
capa
cito
rs v
ery
clos
e to
the
conn
ecto
r J7.
SH
14
0
C16
30.
1UF
DN
P
C15
9
0.1U
F
C16
0
0.1U
FL2
712
0OH
M
1 2
C16
1
0.1U
F
C16
2
0.1U
F
C16
50.
01U
F
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 110
PUBI – Public Use Business Information
Figure 52. MX53 VGA
C17
70.
1UF
VGA_I2C_SCL
LVD
S0_
TX1_
P
R11
61.
05K
VGA_I2C_SDA
R11
50
C17
1
0.01
UF
IOB
L11
120O
HM
12
TVC
DC
_IO
R_B
AC
K
TVC
DC
_IO
G_B
AC
K
TVC
DC
_IO
B_B
AC
K
R11
40
IOG
R11
30
i.MX53 LVDS
U2H
LVD
S0_
CLK
_NA
B16
LVD
S0_
CLK
_PA
C16
LVD
S0_
TX0_
NY
17
LVD
S0_
TX0_
PA
A17
LVD
S0_
TX1_
NA
B17
LVD
S0_
TX1_
PA
C17
LVD
S0_
TX2_
NY
16
LVD
S0_
TX2_
PA
A16
LVD
S0_
TX3_
NA
B15
LVD
S0_
TX3_
PA
C15
LVD
S1_
CLK
_NA
A13
LVD
S1_
CLK
_PY
13
LVD
S1_
TX0_
NA
C14
LVD
S1_
TX0_
PA
B14
LVD
S1_
TX1_
NA
C13
LVD
S1_
TX1_
PA
B13
LVD
S1_
TX2_
NA
C12
LVD
S1_
TX2_
PA
B12
LVD
S1_
TX3_
NA
A12
LVD
S1_
TX3_
PY
12
LVD
S_B
G_R
ES
AA
14
NV
CC
_LV
DS
U13
NV
CC
_LV
DS
_BG
U14
IOR
TVD
AC
_CO
MP
C17
30.
1UF
TVD
AC
_VR
EF
LVD
S0_
TX2_
N
VGA_VSYNC
SH
180
MX_
VG
A_H
SY
NC
8
i.MX
53 - T
VEU
2I TVD
AC
_VR
EF
Y18
TVD
AC
_CO
MP
AA
19
TVD
AC
_IO
RA
C21
TVD
AC
_IO
GA
B20
TVD
AC
_IO
BA
C19
TVC
DC
_IO
R_B
AC
KA
B21
TVC
DC
_IO
G_B
AC
KA
C20
TVC
DC
_IO
B_B
AC
KA
B19
TVD
AC
_AH
VD
DR
GB
_1U
17
TVD
AC
_AH
VD
DR
GB
_2V
16
TVD
AC
_DH
VD
DU
16
LVD
S_2
V5
LVD
S0_
TX1_
NN
VC
C_L
VD
S_B
G
LVD
S0_
CLK
_N
LVD
S0_
TX2_
PLV
DS
0_TX
2_N
LVD
S0_
TX1_
P
LVD
S0_
TX0_
N
LVD
S0_
CLK
_P
LVD
S0_
TX0_
P
LVD
S_B
G_R
ES
VGA_HSYNC
VGA
GN
D
MX_
VG
A_V
SY
NC
8
U16
SR
V05
-4
4
25
3
16
GN
DG
ND
C18
0
0.01
UF
DC
DC
_3V
2
GN
D
GN
DG
ND
GN
D
GN
D
GN
D
LVD
S0_
CLK
_N
GN
D
GN
DG
ND
GN
D
GN
D
GN
D
R12
30
GN
D
C17
8
4.7u
F
GN
D
R12
1
49.9
R12
70
C17
2
0.1U
F
GN
D
Dra
wing
Titl
e:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ific
atio
n:F
CP
:F
IUO
:P
UB
I:
SO
UR
CE
:SC
H-2
6565
PD
F:S
PF
-265
65C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day
, Fe
brua
ry 0
1, 2
011
MX5
3 VG
A
1115
___
___
X
C18
10.
1UF
GN
D
R12
628
K
R11
775
GN
D
C17
9
0.1U
F
I2C
2_S
DA
8,9,
11,1
3
GN
D
R11
875
GN
D
VD
AC
_GN
D
C18
20.
1UF
R11
975
VDA
C_G
ND
VD
AC
_GN
D
5V_M
AIN
DC
DC
_3V
2
I2C
2_S
CL
8,9,
11,1
3
LVD
S0_
TX2_
P
R12
20
Rout
e tra
ces
as 1
00 O
hmDi
ffer
entia
l Pai
rs (x
5)
LVL_
SH
FT_
OE
SH15
0
LVD
S_A
UX_
PW
R
SH
16
0
DIS
P0_
RD
8,13
I2C
3_S
CL
6I2
C3_
SD
A6
R22
30
R22
40
DN
P
DC
DC
_3V
2
SH
17
0
J9 CO
N 3
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
C17
40.
1UF
LVD
S0_
CLK
_P
OP
TIO
NAL
LVD
S0
DIS
PLA
Y O
UTP
UT
LVD
S0_
TX0_
PLV
DS
0_TX
0_N
C17
50.
1UF
LCD
_BLT
_EN
8
DIS
P0_
CO
NTR
AS
T6,
13
TVD
AC_2
V75
5V_M
AIN
TV_2V75
VG
A_I
2C_S
CL
VG
A_5
V_M
AIN
J8 DB
15 S
MT
1234
6
5
78910 1112131415
S2 S1
VG
A_I
2C_S
DA
COMPONENT VIDEO Y OUTPUT (GREEN)
COMPONENT VIDEO Pb OUTPUT (BLUE)
IOB
VG
A V
IDE
O C
ON
NE
CTO
R
IOR
VG
A_V
SY
NC
VG
A_S
HIE
LD_G
ND
COMPONENT VIDEO Pr OUTPUT (RED)
VG
A_H
SY
NC
DC
DC
_3V2
IOG
L28
120O
HM
1 2
5V_M
AIN FLT_5V_MAIN
VG
A_V
SY
NC
U15
SR
V05
-4
4
25
3
16
U12
74LV
C1T
45
VC
CA
1
GN
D2
A3
B4
DIR
5
VC
CB
6
U13
74LV
C1T
45
VC
CA
1
GN
D2
A3
B4
DIR
5
VC
CB
6
VG
A_H
SY
NC
VG
A_V
SY
NC
_AU
X
VG
A_H
SYN
C_A
UX
C18
32.
2UF
R12
00
C17
60.
1UF
C25
22.
2UF
I2C
2_S
CL
8,9,
11,1
3I2
C2_
SD
A8,
9,11
,13
GN
D
5V_M
AIN
U14
TXS
0102
OE
6B
21
B1
8
VCCB7
VCCA3
A1
5
A2
4
GND2
I2C
2_S
CL_
AU
XV
GA_
I2C
_SD
A
R21
30
VG
A_I
2C_S
CL
I2C
2_S
DA
_AU
X
R21
40
5V_M
AIN
LVD
S_I2
C2_
SD
ALV
DS_
I2C
2_S
CL
IOGIOB
IOR
TV_2
V75
LVD
S0_
TX1_
N
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 111
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 53. MX53 ETHERNET
R14
01.
5K
R13
749
.9R
138
49.9
FEC
_nR
ST
8
GN
D
GN
DG
ND
GN
D
GN
D
FEC
_TX_
EN8
GN
D
GN
D
FEC
_TXD
18
R14
149
.9R
139
49.9
FEC
_TXD
08
FEC
_MD
C8
R20
810
0
R20
910
0
C19
2
0.1U
F
FEC
_nIN
T8
ENET
0_LE
D1R
ENET
0_LE
D2R
FEC
_RX_
ER8
FEC
_CR
S_D
V8
FEC
_RXD
18 FE
C_R
EF_C
LK8,
10
C19
1
0.02
2UF
FEC
_RXD
08
C18
9
15pF
C19
0
15pF
FEC
_A3V
2
FEC
_3V
2
R14
312
.1K
R20
410
K C19
3
1.0U
F
R14
210
K
C18
4
0.1U
F
U17 LA
N87
20A
MD
IO12
MD
C13
LED
2/IN
TSEL
2
RXD
1/M
OD
E1
7R
XD0/
MO
DE
08
LED
1/R
EGO
FF
3
TXEN
16TX
D0
17
TXD
118
CR
S_D
V/M
OD
E2
11
RST
15
XTAL
1/C
LKIN
5
XTAL
24
VDD2A1
VDD1A19
RXP
23
RXN
22
TXN
20
TXP
21
VD
DC
R6
INT/
REF
CLK
O14
RB
IAS
24
RXE
R/P
HY
AD0
10VDDIO
9
VSS25
1CT:1
TRANSM
IT
TX+
TX-
RX-
1 2 3 6 4 5 7 8
RX+
1CT:1CT
RECEIVE
R1R2
R3 R4
0.1uF 5%
0.001uF 2k
V 20%
C1C2
R[1-4] - 7
5 OHMS 5
%
YELL
OW
GREEN
SHIELD
ORANGE
"Thi
s pa
rt wi
ll be
pop
ulat
ed w
ith p
arts
that
may
or
may
not
hav
e in
tern
al L
ED
cur
rent
resi
stor
s. E
xter
nal L
ED r
esis
tors
mus
t be
used
, co
lor
and
brig
htne
ss o
f LE
Ds
may
var
y."
J2B
HY
BRID
DU
AL U
SB
+ R
J45
TD+
2
CT_
T1
TD-
3
RD
+4
RD
-5
CT_
R10
Y-
13
Y+
14
G-
11
G+
12
NC
66
NC
77
NC
88
NC
99
SGN
D5
S5
SGN
D6
S6
SGN
D7
S7
SGN
D8
S8
C18
5
0.1U
F
L12
120O
HM
12
FEC
_3V2
FEC
_3V
2
FEC
_VD
DC
R
TXP0
TXN
0
FEC
_A3V
2
FEC
_A3V
2
RXP
0
FAS
T ET
HER
NET
PH
Y
FEC
_RB
IAS
C18
6
0.1U
F
RXN
0
EN
ET0
_100
MLE
D2
EN
ET0
_LIN
KLE
D1
FEC
_3V2
EN
ET0
_LIN
KLE
D1
ENET
0_10
0MLE
D2
FEC
_USB
_SH
IELD
7
FEC
_MD
IO8
Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICA
P C
lass
ifica
tion:
FCP:
FIU
O:
PUBI
:
SOU
RC
E:SC
H-2
6565
PD
F:SP
F-2
6565
C
MC
IMX5
3-Q
UIC
KST
ART
C
Frid
ay,
Janu
ary
14,
2011
MX5
3 FE
C
1215
___
___
X
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 112
PUBI – Public Use Business Information
Figure 54. EXPANSION HEADER
DIS
P0_
DA
T23
DIS
P0_
DA
T4
VLC
D_B
LT
DIS
P0_
HS
YN
C
DIS
P0_
DA
T5
I2C
2_SC
L8,
9,11
I2C
2_SD
A8,
9,11
DIS
P0_V
SY
NC
GN
D
TS_X
N14
GN
D
DIS
P0_
VS
YN
C
TS_X
P14
DIS
P0_
DA
T6
TS_Y
N14
TS_Y
P14
Dra
win
g Ti
tle:
Size
Doc
umen
t N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ific
atio
n:FC
P:
FIU
O:
PU
BI:
SOU
RC
E:S
CH
-265
65
PD
F:S
PF
-265
65C
MC
IMX5
3-Q
UIC
KST
ART
C
Tues
day
, F
ebru
ary
01,
201
1
EXPA
NSIO
N H
EAD
ER
1315
___
___
X
DIS
P0_
DA
T7
DIS
P0_H
SY
NC
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
DIS
P0_
DR
DY
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
J13
QS
H-0
60-0
1-L-
D-A
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
SH
1S
H2
SH
3S
H4
SH
5S
H6
SH
7S
H8
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
8182
8384
8586
8788
8990
9192
9394
9596
9798
9910
010
110
210
310
410
510
610
710
810
911
011
111
211
311
411
511
611
711
811
912
0
POR
T_ID
014
DIS
P0_
DA
T8
DIS
P0_D
RD
Y
SS
5.6
35" L
ON
G DN
P
EX
P H
DR
STA
ND
OFF
GN
D
R16
9
2.74
K
DIS
P0_
DA
T9
POR
T_ID
114
VLD
O8_
1V8
DIS
P0_D
AT0
PC
LOC
K6
DIS
P0_D
CLK
DIS
P0_
DA
T10
EXPA
NSI
ON
HEA
DER
FO
R D
EBU
G A
ND
LC
D I/
F
DIS
P0_
DA
T11
LCD
_3V2
DIS
P0_S
ER
_RS
8
EXP
_HD
R_P
IN_7
9
DIS
P0_
DA
T12
DIS
P0_S
ER
_SC
LK8
DIS
P0_
RD
8,11
VLD
O9_
1V5
DIS
P0_S
ER
_nC
S8
CS
I0_D
AT1
6
CS
I0_D
AT1
5
CS
I0_D
AT1
4
CS
I0_D
AT1
3
CS
I0_D
AT1
2
CS
I0_P
IXC
LKC
SI0
_VS
YN
CH
CS
I0_D
AT1
9
CS
I0_D
AT1
8
CS
I0_D
AT1
7
CS
I0_H
SY
NC
H
DIS
P0_R
ES
ET
8
CS
I0_P
WD
N8
CS
I0_R
STB
8
DIS
P0_S
ER
_MO
SI
8D
ISP
0_D
AT1
3
I2C
1_SD
A14
,15
CS
I0_D
AT1
3C
SI0
_DA
T12
CS
I0_D
AT1
8
CS
I0_D
AT1
7C
SI0
_DA
T16
CS
I0_D
AT1
5C
SI0
_DA
T14
CS
I0_D
AT1
9
DIS
P0_D
AT1
SP
DIF
MC
LOC
K
CS
I0_V
SYN
CH
CS
I0_H
SYN
CH
5V_M
AIN
DIS
P0_
DA
T14
5V_M
AIN
DIS
P0_
WR
8
LCD
_3V
2
5V_M
AIN
DIS
P0_D
CLK
DIS
P0_
SER
_MIS
O8
DIS
P0_D
AT2
DIS
P0_P
OW
ER
_EN
8
DIS
P0_
nCS1
8
UAR
T1_R
X15
GPI
O_0
(CLK
0)6,
9
CS
I0_P
IXC
LK
DIS
P0_
DA
T15
DIS
P0_
nCS0
8
VLD
O8_
1V8
i.MX
53 -
IPU
NVCC_CSI
NVCC_LCD
U2D C
SI0
_DA
T8T1
CS
I0_D
AT9
R4
CS
I0_D
AT1
0R
5
CS
I0_D
AT1
1T2
CS
I0_D
AT1
2T3
CS
I0_D
AT1
3T6
CS
I0_D
AT1
4U
1
CS
I0_D
AT1
5U
2
CS
I0_D
AT1
6T4
CS
I0_D
AT1
7T5
CS
I0_D
AT1
8U
3
CS
I0_D
AT1
9U
4
CS
I0_V
SY
NC
P4
CS
I0_P
IXC
LKP1
CS
I0_M
CLK
P2
DI0
_PIN
4D
2
DIS
P0_D
AT0
J5
DIS
P0_D
AT1
J4
DIS
P0_D
AT2
H2
DIS
P0_D
AT3
F1
DIS
P0_D
AT4
G2
DIS
P0_D
AT5
H3
DIS
P0_D
AT6
G1
DIS
P0_D
AT7
H6
DIS
P0_D
AT8
G6
DIS
P0_D
AT9
E2
DIS
P0_
DA
T10
G3
DIS
P0_
DA
T11
H5
DIS
P0_
DA
T12
H1
DIS
P0_
DA
T13
E1
DIS
P0_
DA
T14
F2
DIS
P0_
DA
T15
F3
DIS
P0_
DA
T16
D1
DIS
P0_
DA
T17
F5
DIS
P0_
DA
T18
G4
DIS
P0_
DA
T19
G5
DIS
P0_
DA
T20
F4
DIS
P0_
DA
T21
C1
DIS
P0_
DA
T22
E3
DIS
P0_
DA
T23
C3
DI0
_PIN
3C
2
DI0
_DIS
P_C
LKH
4
DI0
_PIN
2D
3
DI0
_PIN
15E
4
CS
I0_D
AT4
R1
CS
I0_D
AT5
R2
CS
I0_D
AT6
R6
CS
I0_D
AT7
R3
CS
I0_D
ATA
_EN
P3
VLD
O8_
1V8
DIS
P0_D
AT3
LCD
_BLT
1_N
14
DIS
P0_
DA
T16
I2C
1_SC
L14
,15
DIS
P0_D
AT4
DIS
P0_
DA
T17
UAR
T1_T
X15
DIS
P0_D
AT5
DIS
P0_
DA
T18
SP
DIF
_TX
6
DIS
P0_D
AT6
DIS
P0_
DA
T19
DIS
P0_
DA
T0
DIS
P0_D
AT7
DIS
P0_
DA
T20
DIS
P0_
DA
T1
VIO
HI_
2V77
5
DIS
P0_D
AT8
DIS
P0_D
AT12
DIS
P0_D
AT11
DIS
P0_D
AT10
DIS
P0_D
AT9
DIS
P0_D
AT15
DIS
P0_D
AT14
DIS
P0_D
AT13
DIS
P0_C
ON
TRA
ST
6,11
R18
810
KD
NP
DIS
P0_
DA
T21
R18
910
KD
NP
DIS
P0_
DA
T2
DIS
P0_D
AT16
DIS
P0_D
AT20
DIS
P0_D
AT19
DIS
P0_D
AT18
DIS
P0_D
AT17
DIS
P0_D
AT23
DIS
P0_D
AT22
DIS
P0_D
AT21
DIS
P0_
DA
T22
DIS
P0_
DA
T3
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 113
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 55. DA9053 PMIC
R14
820
0K
TP16
R15
10
GN
D
TBA
T
VLD
O3_
3V3
TS_X
N13
C22
3
0.1U
F
C21
41.
0UF
TP18
GN
D
C20
9
0.47
UF
VB
UC
KC
OR
E
5V_M
AIN
PO
RT_
ID0
13
SW
BU
CK
ME
M
U20
C
DA
9053
VC
EN
TER
A7
VS
W_A
8A
8
VS
W_A
9A
9
VB
US
_PR
OT_
A5
A5
VB
US
_PR
OT_
A6
A6
VB
US
_SE
LB
5
VD
DO
UT_
A11
A11
VD
DO
UT_
A10
A10
VB
US
B6
AD
_CO
NT
B11
DC
IN_P
RO
T_A
3A
3
DC
IN_P
RO
T_A
4A
4
VB
AT_
A13
A13
VB
AT_
A12
A12
DC
IN_S
EL
B3
DC
INB
4
D-
B13
D+
C13
VB
BA
TB
2
VR
EF
A2
IRE
FD
5
VD
D_R
EF
C2
TBA
TL6
AD
CIN
4_G
PIO
_0C
6
AD
CIN
5_G
PIO
_1C
5
AD
CIN
6_G
PIO
_2C
4
TSIY
N_G
PIO
_3K
6
TSIY
P_G
PIO
_4K
8
TSIX
N_G
PIO
_5K
5
TSIX
P_G
PIO
_6K
7
TSIR
EF
_GP
IO_7
K9
OU
T_32
KK
12
XOU
TB
1
XIN
C1
VLD
O5_
1V3
TP19
TBA
T
VD
DO
UT
GN
D
VLD
O6_
1V3
PM
IC_V
DD
_RE
F
TS_X
P13
TP20
VLD
O7_
2V75
C20
8
0.1U
F
PO
RT_
ID1
13
VLD
O8_
1V8
L16
4.7U
H
12
Sup
ply
for D
DR3
mem
orie
s @
1.5V
C20
5
47U
F
L14
2.2U
H
CD
RH
2D18
/HP
-2R
2NC
12
TP11
GN
D
BO
OS
T_P
RO
T
BO
OS
T_S
EN
SE
_P
DIG
_PLL
_1V
3
JP1
HD
R 1
X1D
NP
1
LCD
_BLT
1_N
13
TES
TP
VLD
O8_
1V8
VD
DC
OR
E
I2C
1_S
DA
13,1
5
JP2
HD
R 1
X1D
NP
1
GN
D
GN
D
AD
CIN
6/G
PIO
_2
C20
1
10U
F
L15
2.2U
H
CD
RH
2D18
/HP
-2R
2NC
12
TSIR
EF
_GP
IO_7
NC
Q8
NTL
JF41
56N
5
43
2
16
8
7
VLD
O9_
1V5
C22
7
4.7u
F
C20
0
10U
F
L17
2.2U
H
CD
RH
2D18
/HP
-2R
2NC
12
AD
CIN
6/G
PIO
_2
C21
62.
2UF
GN
D
GN
D
C21
32.
2UF
GN
D
C23
022
UF
L18
2.2U
H
CD
RH
2D18
/HP
-2R
2NC
12
C21
12.
2UF
PM
IC_V
RE
F
I2C
1_S
CL
13,1
5
C21
02.
2UF
SY
S_E
N
VLD
O8_
1V8
C20
32.
2UF
R15
24.
7K
VD
DC
OR
E
C20
4
4.7u
F
U20
D
DA
9053
VD
D_I
O1
L4
VD
D_I
O2
K4
NR
ES
ET
F10
NIR
QE
10
NV
DD
_FA
ULT
_GP
IO_1
3C
11
GP
_FB
1_G
PIO
_12
B10
PW
R_U
P_G
P_F
B2
J10
TPL5
NO
NK
EY
_KE
EP
_AC
TM
11
SY
S_E
N_G
PIO
_8D
10
PW
R_E
N_G
PIO
_9C
10
PW
R1_
EN
_GP
IO_1
0L2
AC
C_I
D_D
ET_
GP
IO_1
1L3
NS
HU
TDO
WN
D11
SO
L10
SI
K10
SK
L11
NC
SK
11
DA
TA_G
PIO
_14
N1
CLK
_GP
IO_1
5M
2
GN
D
C19
42.
2UF
C19
5
10U
F
SH
DN
_5V
3
GN
D
VLD
O3_
3V3
VD
DO
UT
VB
UC
KP
RO
C21
80.
1UF
VM
EM
_SW
VD
DO
UT
U20
A
DA
9053
VD
D_L
DO
1E
2V
LDO
1D
1
VLD
O2
F2
VD
D_L
DO
2E
1
VD
D_L
DO
3_4
J2V
LDO
3J1
VLD
O4
H1
VD
D_L
DO
5G
2
VD
D_L
DO
6H
2
VLD
O5
F1
VLD
O6
G1
VD
D_L
DO
7_8
K2
VD
D_L
DO
9_10
M3
VLD
O7
K1
VLD
O8
L1
VLD
O9
M1
VLD
O10
N2
VD
DC
OR
ED
2
TSIR
EF_
GP
IO_7
GN
D
LCD
_BLT
3_N
U20
B
DA
9053
VB
UC
KP
ER
IE
12
SW
BU
CK
PE
RI
L13
VP
ER
I_S
WD
12
VB
UC
KM
EM
C12
SW
BU
CK
ME
MM
13
VM
EM
_SW
B12
SY
S_U
PL1
2
SW
BU
CK
CO
RE
_G13
G13
SW
BU
CK
CO
RE
_F13
F13
VB
UC
KP
RO
M12
SW
BU
CK
PR
OH
13
SW
_BO
OS
TM
10
BO
OS
T_S
EN
SE
_PN
10
BO
OS
T_S
EN
SE
_NN
9
BO
OS
T_P
RO
TN
11
LED
1_IN
M9
LED
2_IN
L8
LED
3_IN
L7V
SS
_NO
ISY
_D6
D6
VD
DB
UC
K_M
EM
N13
VD
DB
UC
K_P
ER
_PR
O_K
13K
13
VD
DB
UC
K_P
ER
_PR
O_J
13J1
3
VD
DB
UC
K_C
OR
E_D
13D
13
VD
DB
UC
K_C
OR
E_E
13E
13
VB
UC
KC
OR
EF
12
PW
R_E
N
SW
BU
CK
PR
O
TP24
GN
D
GN
D
PM
IC_I
RE
F
VD
DO
UT
VS
W
GN
D
VB
BA
T
U20
E
DA
9053
VS
S_N
OIS
Y_E
8E
8
VS
S_N
OIS
Y_E
7E
7
VS
S_N
OIS
Y_G
9G
9
VS
S_N
OIS
Y_H
8H
8
VS
S_N
OIS
Y_E
9E
9
VS
S_N
OIS
Y_F
8F
8
VS
S_N
OIS
Y_E
6E
6
VS
S_N
OIS
Y_J
7J7
VS
S_N
OIS
Y_H
7H
7
VS
S_N
OIS
Y_E
5E
5
VS
S_N
OIS
Y_G
7G
7
VS
S_N
OIS
Y_F
7F
7
VS
S_N
OIS
Y_F
6F
6
VS
S_Q
UIE
T_H
6H
6
VS
S_N
OIS
Y_J
9J9
VS
S_Q
UIE
T_G
5G
5
VS
S_Q
UIE
T_J5
J5
VS
S_Q
UIE
T_J6
J6
VS
S_N
OIS
Y_F
5F
5
VS
S_N
OIS
Y_F
9F
9
VS
S_N
OIS
Y_G
8G
8
VS
S_N
OIS
Y_J
8J8
VS
S_N
OIS
Y_H
9H
9
VS
S_Q
UIE
T_H
5H
5
VS
S_N
OIS
Y_D
7D
7
VS
S_Q
UIE
T_G
6G
6
PM
IC_I
RE
F
GN
D
GN
D
nIR
Q6
VD
DC
OR
E
C22
010
UF
GN
D
U20
F
DA
9053
NC
_A1
A1
NC
_B7
B7
NC
_B8
B8
NC
_B9
B9
NC
_C3
C3
NC
_C7
C7
NC
_C8
C8
NC
_C9
C9
NC
_D3
D3
NC
_D4
D4
NC
_D8
D8
NC
_D9
D9
NC
_E3
E3
NC
_E4
E4
NC
_E11
E11
NC
_F3
F3
NC
_F4
F4
NC
_F11
F11
NC
_G3
G3
NC
_G4
G4
NC
_G10
G10
NC
_G11
G11
NC
_G12
G12
NC
_H3
H3
NC
_H4
H4
NC
_H10
H10
NC
_H11
H11
NC
_H12
H12
NC
_J3
J3
NC
_J4
J4
NC
_J11
J11
NC
_J12
J12
NC
_K3
K3
NC
_L9
L9
NC
_M4
M4
NC
_M5
M5
NC
_M6
M6
NC
_M7
M7
NC
_M8
M8
NC
_N5
N5
NC
_N6
N6
NC
_N7
N7
NC
_N3
N3
NC
_N4
N4
NC
_N8
N8
NC
_N12
N12
PW
R1_
EN
GN
D
GN
D
GN
D
VLD
O10
_1V
3
LCD
_BLT
2_N
TP12
GN
D
1000
mA
max
GN
D
GN
D
GN
D
GN
D
PM
IC_V
DD
_RE
F
GN
D
TP13
GN
D
VB
AT
VB
UC
KC
OR
E
SH
30
0
GN
D
TP23
GN
D
GN
D
C23
12.
2UF
DN
P
JP2
JP1
R15
30.
1
LCD
_BLT
3_N
GP
_FB
1
SW
_BO
OS
T
Q7
Si2
333D
S1
32
GN
D
5V_M
AIN
Sup
ply
for V
DD_R
EG to
be c
onfig
ured
@2.
5V
R14
910
K
3V3_
EN
3
GN
D
nON
KE
Y/K
EE
PA
CT
6
VP
ER
I_S
W
1000
mA
max
R20
310
K
R15
010
K
C22
92.
2UF
3V3_
EN
TES
TP
VB
BA
T
LCD
_BLT
2_N
1000
mA
max
GN
D
GN
D
R15
568
K
3.6
to V
BA
T+20
0mV
GP
IO_1
4
2000
mA
max
nVD
D_F
AU
LT6
GN
D
C20
6
1.0U
F
VD
DO
UT_
SU
P
TBA
T
GN
D
C22
422
UF
TP21
C21
5
1.0U
F
C22
122
UF
-+
4mm
13m
m
nIR
Q
5V_J
K3
VB
UC
KP
ER
I
C21
2 0.22
UF
TP17
J14
CO
N_1
X3
DN
P
123
VIO
HI_
2V77
5
SW
BU
CK
PE
RI
VD
DO
UT
TES
TP
SW
BU
CK
CO
RE
C19
61.
0UF
CL
2.7m
m-+
GN
D
GN
D
J19
HD
R 1
X2D
NP
1 2
AD
_CO
NT
GN
D
I2C
1_S
DA
nRE
SE
T
VC
EN
TER
C22
222
UF
Sup
ply
for C
ORE
tobe
con
figur
ed @
1.1V
TP15
R15
41M
C22
622
UF
VB
UC
KM
EM
GN
D
C22
822
UF
GN
D
TS_Y
N13
GN
D
TBA
T
GN
D
C19
91.
0UF
Dra
win
g Ti
tle:
Siz
eD
ocum
ent
Num
ber
Rev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ific
atio
n:F
CP
:F
IUO
:P
UB
I:
SO
UR
CE
:SC
H-2
6565
P
DF
:SP
F-2
6565
C
MC
IMX5
3-Q
UIC
KST
ART
D
Wed
nesd
ay,
Janu
ary
12,
201
1
PMIC
DA
9053
1415
___
___
X
nRE
SE
TI2
C1_
SC
L
nRE
SE
T6
nSH
UTD
OW
N
GP
IO_1
5
ML1
220-
VM
1LA
YO
UT
&K
EE
PO
UT
C22
5
0.1U
F
C20
71.
0UF
VLC
D_B
LT
TS_Y
P13
L13
2.2U
H1
2
TP14
CL
3mm
VLD
O3_
3V3
Pins
D7
and
F5 c
anbe
left
open
as
they
are
"NC
" pi
ns.
SY
S_U
P6
JP1 and JP2 for
OPTIONAL
COIN CELL
Note:
Traces are routed to NC pins for layout purposes only.
This allows signals to route out of chip via NC pins
on the top layer. NC pins are not connected to any
pad internal to the PMIC.
VLD
O1_
1V3_
RTC
D8
BA
T760 2
1
nSH
UTD
OW
N
Supp
ly fo
r VCC
tobe
con
figur
ed @
1.3V
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 114
PUBI – Public Use Business Information
Figure 56. DEBUG, ACCELEROMETER
GN
DG
ND
VLD
O8_
1V8
AC
CL_
EN
8
ACC
L_IN
T1_I
N8
I2C
1_SC
L13
,14
I2C
1_SD
A13
,14
ACC
L_IN
T2_I
N8
VLD
O8_
1V8
L26
600
OH
M
1 2
ACC
ELER
OM
ETER
VLD
O8_
1V8
JTAG
TH
RO
UG
H H
OLE
CO
NN
ECTO
R
Dra
wing
Titl
e:
Size
Doc
umen
t N
umbe
rR
ev
Dat
e:Sh
eet
of
Page
Titl
e:
ICA
P C
lass
ifica
tion:
FC
P:
FIU
O:
PU
BI:
SOU
RC
E:SC
H-2
6565
PD
F:S
PF-
2656
5C
MC
IMX5
3-Q
UIC
KST
ART
C
Wed
nesd
ay, J
anua
ry 1
2, 2
011
DEB
UG
, ACC
ELER
OM
ETER
1515
___
___
X
UAR
T D
B9 S
MT
CO
NN
ECTO
R
R15
810
KR
159
10K
DN
P
R16
010
K
R15
710
0R
161
10K
R16
710
0
R16
210
K
JTAG
_nS
RS
T6
R16
410
K
J15
TST-
110-
05-T
-D-R
A
12
34
56
78
910
1112
1314
1516
1718
1920
R16
510
K
R16
30 D
NP
JTA
G_D
AC
K
R16
610
K
DC
DC
_3V
2
GN
DG
ND
JTA
G_R
TCK
JTAG
_PW
RVT
REF
_JTA
G
JTA
G_D
E
C23
8
1000
pF
C23
4
1.0U
F
UAR
T1_R
X13
C23
5
0.1U
F
C23
2
0.1U
F
C23
6
0.1U
F
C23
3
0.1U
F
C23
7
0.1U
F
UA
RT_
RXL
UAR
T_V
P
UAR
T_C
1M
UA
RT_
TXL
UAR
T_C
1P
GN
D
DC
DC
_3V
2
DC
E_TX
UAR
T_C
2M
DC
E_R
X
UAR
T_C
2P
GN
D
GN
DU
ART_
VM
UA
RT1
_TX
13
U24
SP32
32VCC16 C
2+4
R1I
N13
R2I
N8
R1O
UT
12
R2O
UT
9
C1-
3
C1+
1
GND15
V+2
V-
6
C2-
5
T1IN
11
T2IN
10
T1O
UT
14
T2O
UT
7
J16
DB
9
594837261
M2
M1
Female DB-9 Connector
UA
RT_
SHIE
LD_G
ND
CD1
DCE
2
O
543 876 9
IO IOI OO
RXTX DSR
GND
DTR
CTS
RTS
RI
GN
D
GN
DG
ND
DC
E_TX
DC
E_R
X
U25 74LV
C1T
45VCC
A1
GN
D2
A3
B4
DIR
5
VCC
B6
U26 74LV
C1T
45VCC
A1
GN
D2
A3
B4
DIR
5
VCC
B6
GN
D
GN
D
C24
7
0.1U
F
C24
9
0.1U
F
C24
8
0.1U
F
C25
0
0.1U
F
GN
D
GN
D
GN
D
GN
D
DC
DC
_3V2
DC
DC
_3V2
VLD
O8_
1V8
VLD
O8_
1V8
JTAG
_nTR
ST
6
JTAG
_TM
S6
JTAG
_TD
I6
U23
MM
A845
0QT
VDD11
NC
22
NC
33
SCL
4
GND15
SDA
6
SA0
7
EN
8
INT2
9
TES
T/G
ND
10IN
T111
GN
D12
GND213
VDD214
NC
1515
NC
1616
JTAG
_TC
K6
UA
RT_
RXL
R20
210
KD
NP
R20
610
K
SH20
0
AC
CL_
SA0
ACC
L_VD
D
GN
D
GN
D
GN
D
JTAG
_TD
O6
GN
DC24
6
0.1U
F
UAR
T_TX
L
VLD
O8_
1V8
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 115
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
14. BillofMaterials The Bill of Materials used to manufacture the Quick Start board is presented in this section. The capacitors and resistors used are considered generic type components and do not include manufacturer names or part numbers. The remainder of the parts have manufactures and part numbers provided for the primary part specified. Second source vendors are not included. The final section of the Bill of materials includes the list of parts not populated on the Quick Start board at the time of manufacture. Parts are listed in the following tables: Table 32. Generic Resistors Table 33. Generic Capacitors Table 34. Specified Components Table 35. Non‐Populated Components
Generic Resistors Description QTY Reference Designator RES MF ZERO OHM 1/20W 5% 0201 4 R123, R127, R213, R214 RES MF ZERO OHM 1/16W 5% 0402 12 R25, R30, R31, R32, R33, R113, R114, R115, R144, R145, R151,
R223 RES MF ZERO OHM 1/10W ‐‐ 0603 3 R12, R19, R120 RES MF ZERO OHM 1/8W ‐‐ 0805 1 R122 RES MF 0.1 OHM 1/8W 1% 0402 2 R153, R201 RES MF 1.0 OHM 1/16W 1% 0402 4 R68, R69, R72, R73 RES MF 22 OHM 1/16W 5% 0402 2 R211, R212 RES 10 OHM 1/20W 5% 0201 1 R199 RES MF 33.0 OHM 1/20W 5% 0201 1 R104 RES MF 49.9 OHM 1/20W 1% 0201 5 R121, R137, R138, R139, R141 RES MF 75 OHM 1/20W 5% 0201 3 R117, R118, R119 RES TF 100 OHM 1/20W 5% RC0201 7 R66, R157, R167, R185, R186, R208, R209 RES MF 191 OHM 1/16W 1% 0402 1 R112 RES MF 200 OHM 1/16W 1% 0402 2 R28, R29
Table 32. Generic Resistors
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 116
PUBI – Public Use Business Information
Generic Resistors Description QTY Reference Designator RES MF 240 OHM 1/16W 1% 0402 5 R190, R191, R192, R193, R194 RES MF 470 OHM 1/20W 1% 0201 6 R26, R27, R81, R177, R178, R187 RES MF 1.0K 1/20W 1% 0201 13 R49, R50, R173, R174, R175, R176, R179, R180, R181, R182,
R183, R184, R198 RES MF 1.05K 1/16W 1% 0402 1 R116 RES MF 1.5K 1/20W 5% 0201 1 R140 RES MF 2.2K 1/20W 5% 0201 1 R101 RES MF 2.74K 1/16W 1% 0402 1 R169RES 3.3K 1/20W 5% RC0201 ROHS 2 R195, R196RES MF 4.7K 1/20W 5% 0201 3 R85, R86, R200RES MF 4.7K OHM 1/20W 1% 0201 20 R37, R40, R46, R47, R53, R54, R55, R56, R57, R58, R59, R60,
R61, R62, R63, R64, R65, R152, R221, R222 RES MF 6.04K 1/16W 1% 0402 2 R70, R71RES MF 10K 1/20W 5% 0201 33 R10, R34, R35, R39, R41, R44, R76, R82, R87, R88, R89, R110,
R142, R149, R150, R158, R160, R161, R162, R164, R165, R166, R168, R170, R171, R203, R204, R206, R216, R217, R218, R219, R220
RES MF 10.0K 1/20W 1% 0201 2 R51, R52RES MF 12.1K 1/16W 1% 0402 1 R143RES MF 28K 1/16W 1% 0402 1 R126RES MF 47K 1/20W 5% 0201 1 R13RES MF 68K 1/20W 1% 0201 1 R155RES MF 100K 1/20W 1% 0201 3 R7, R9, R215RES MF 200K 1/16W 1% 0402 1 R148RES MF 432K 1/16W 1% 0402 1 R8RES MF 1.0M 1/20W 5% 0201 1 R154
Table 32. Generic Resistors (con.)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 117
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Generic Capacitors Description QTY Reference Designator CAP CER 10PF 25V 5% C0G 0201 1 C5 CAP CER 12PF 25V 5% C0G 0201 2 C217, C219 CAP CER 15PF 25V 5% C0G 0201 2 C189, C190 CAP CER 18PF 25V 5% C0G 0201 2 C133, C134CAP CER 1000PF 16V 10% X7R 0201 1 C238CAP CER 1000PF 2KV 10% X7R 1210 1 C135CAP CER 0.01UF 10V 10% X5R 0201 22 C48, C49, C50, C80, C82, C84, C93, C95, C97, C100, C102, C104,
C107, C109, C111, C141, C165, C166, C167, C169, C171, C180CAP CER 0.022UF 10V 10% X5R 0201 1 C191CAP CER 0.1UF 6.3V 10% X5R 0201 104 C8, C44, C46, C47, C52, C53, C54, C55, C56, C57, C58, C59, C60,
C61, C62, C63, C66, C67, C68, C69, C70, C72, C73, C74, C75, C76, C77, C78, C79, C81, C83, C86, C87, C88, C89, C90, C92, C94, C96, C99, C101, C103, C106, C108, C110, C113, C114, C115, C116, C117, C119, C120, C121, C122, C123, C125, C126, C127, C128, C129, C131, C132, C136, C138, C139, C142, C143, C145, C147, C148, C150, C152, C153, C159, C160, C161, C162, C164, C172, C174, C175, C176, C177, C179, C181, C182, C184, C185, C186, C192, C208, C218, C223, C225, C232, C233, C235, C236, C237, C246, C247, C248, C249, C250
CAP CER 0.1UF 16V 10% X7R 0402 1 C173CAP CER 0.1UF 35V 10% X5R 0402 1 C245CAP CER 0.22UF 6.3V 20% X5R 0201 31 C9, C10, C11, C12, C13, C14, C16, C17, C18, C19, C21, C22, C23,
C24, C25, C26, C27, C29, C30, C31, C32, C33, C34, C35, C37, C38, C39, C42, C43, C64, C212
CAP CER 0.47UF 6.3V 10% X5R 0402 1 C209CAP CER 1.0UF 35V 10% X5R 0603 1 C244CAP CER 1.0UF 10V 10% X5R 0402 12 C3, C151, C193, C196, C199, C206, C207, C214, C215, C234,
C239, C240CAP CER 2.2UF 6.3V 20% X5R 0402 11 C137, C140, C183, C194, C203, C210, C211, C213, C216, C252,
C253CAP CER 2.2UF 25V 10% X5R 0805 1 C229CAP CER 4.7UF 6.3V 20% X5R 0402 4 C149, C178, C204, C227CAP CER 10UF 6.3V 20% X5R 0603 17 C7, C28, C40, C85, C91, C98, C105, C112, C118, C124, C130,
C144, C146, C195, C200, C201, C220 CAP CER 10UF 10V 10% X5R 0805 2 C2, C4CAP CER 22UF 6.3V 20% X5R 0805 12 C15, C41, C45, C51, C65, C71, C221, C222, C224, C226, C228,
C230CAP CER 47uF 6.3V 20% X5R 0805 3 C20, C36, C205CAP CER 100UF 6.3V 20% X5R 1206 4 C1, C241, C242, C243
Table 33. Generic Capacitors
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 118
PUBI – Public Use Business Information
SPECIFIED COMPONENTS Description QTY Reference Designator Manufacturer Part Number CAP TANT 220UF ESR=0.800 OHM 4V 20% ‐‐ 3216‐10 2 C154,C157 NICHICON F950G227MSAAQ2IND FER BEAD 120OHM@100MHZ 2A 25% 0603 3 L7,L9,L19 MURATA BLM18PG121SH1IND FER BEAD 120 OHM@100MHZ 500MA 25% 0603 2 L10,L12 MURATA BLM18AG121SN1JIND PWR 4.7UH@100KHZ 1.1A 20% SMT 1 L1 TDK VLF4012AT‐4R7M1R1IND PWR 2.2UH@100KHZ 1.6A 30% SMD 4 L14,L15,L17,L18
SUMIDA ELECTRIC
CDRH2D18/HP‐2R2NC
IND CHK 90 OHM@100MHZ 330MA 25% 0805 2 L5,L6 MURATA DLW21HN900SQ2LIND FER 120OHM@100MHZ 300MA 25% 0402 6 L2,L4,L8,L11,L27,L28 MURATA BLM15HB121SN1D IND FER BEAD 600 OHM@100MHZ 300MA 25% 0402 1 L26 MURATA BLM15HD601SN1D IND FER BEAD 220OHM@100MHZ 700MA 25% 0402 5 L20,L21,L23,L24,L25 MURATA BLM15EG221SN1_ IND PWR 2.2UH@1MHZ 1.5A 20% SMD 1 L13 TDK VLS3012T‐2R2M1R5 IND PWR 4.7UH@1MHZ 1A 20% SMD 1 L16 TDK VLS3012T‐4R7M1R0 CON 1 PWR PLUG DIAM 2.0MM RA TH ‐‐ 430H NI 1 J1 CUI STACK PJ‐202A CON 5 AUD JACK 3.2MM SKT RA TH ‐‐ 197H SN 079L 2 J6,J18 CUI STACK SJ‐43515TS HDR 2X10 RA SHRD TH 100MIL CTR 365H SN 230L 1 J15 SAMTEC TST‐110‐05‐T‐D‐RA CON 1X7 PLUG SATA TH 50MIL SP 331H ‐‐ 96L 1 J7 3M 5607‐5102‐SH CON 2X60 SKT SMT 0.5MM SP AU 1 J13 SAMTEC QSH‐060‐01‐L‐D‐A
CON 19 CRD SKT SMT ‐‐ 150H AU 1 J5 PROCONN TECHNOLOGY SDC013‐A0‐501F
CON 30 SHRD SKT RA SMT 1MM SP AU 1 J9 HIROSE DF19G‐30P‐1H(56)
Table 34. Specified Components
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 119
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
SPECIFIED COMPONENTS Description QTY Reference Designator Manufacturer Part Number CON 5 MICRO USB B RA SHLD SKT 0.65MM SP SMT AU 1 J3 MOLEX 47346‐0001 CON 9 DB 0.118 SKT RA SMT 55MIL SP 494H AU 1 J16 NORCOMP 190‐009‐263R001 CON 12 SKT SD/MMC RA SMT 43MIL SP 78H AU 1 J4 3M 29‐08‐05WB‐MG CON 15 DB RA SKT SMT 0.76MM SP 425H SN 1 J8 NORCOMP 200‐015‐263R001
OSC 50MHZ PROG 3.3V 1 X1 FOX ELECTRONICS FXO‐HC736R‐50
XTAL 32.768KHZ RSN ‐‐ SMT 1 QZ1 MICRO CRYSTAL CC7V‐T1A 32.768KHZ 9PF+/‐30PPM
XTAL 24MHZ ‐‐ 3.2X2.5MM SMT 1 Y1 SIWARD INTERNATIONAL
XTL571300LLI24.000‐10TR
IC BUF TS 0.9‐3.6V 1 U22 FAIRCHILD NC7SP125P5X IC TRANS 1.65V‐5.5V SINGLE SOT23‐6 4 U12,U13,U25,U26
TEXAS INSTRUMENTS SN74LVC1T45DBVR
IC XCVR RS232 120KBPS 3.0‐5.5V SSOP16 1 U24 SIPEX SP3232ECA‐L IC VREG LDO ADJ 0.6‐5.3V 1A 2.5‐5.5V WDFN‐6L 1 U1 RICHTEK RT8010PQW IC XCVR ETHERNET 1.6‐3.6V QFN24 1 U17 SMSC LAN8720A‐CP‐TR IC AUDIO CODEC STEREO 8‐27MHZ 1.8‐3.3V QFN32 1 U9
FREESCALE SEMI SGTL5000XNAA3R2
IC VXLTR 2BIT 1.65‐3.6V/2.3‐5.5V SOT70‐8 1 U14
TEXAS INSTRUMENTS TXS0102DCUR
IC FIFO 12BIT 1.71‐1.89V QFN16 1 U23 FREESCALE SEMI MMA8450QT
IC LIN PMIC WITH USB PWR MANAGER 5.5V VFBGA169 1 U20
Dialog Semiconductor DA9053
IC MPU ARM COREA8 1GHZ ‐‐ TEPBGA529 1 U2
FREESCALE SEMI IMX53
IC MEM DDR3 SDRAM 2Gb 128MX16 1.5V FBGA96 4 U3,U4,U5,U6 MICRON
MT41J128M16HA‐15E:D
Table 34. Specified Components (con.)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 120
PUBI – Public Use Business Information
SPECIFIED COMPONENTS Description QTY Reference Designator Manufacturer Part Number LED ULTRA‐BRIGHT GREEN SMT 0603 3 D1,D9,D16 LITE ON LTST‐C190KGKT LED BLUE ‐‐ 20MA SMT 4 D10,D11,D12,D13 LITE ON LTST‐C190TBKT LED ULTRA BRIGHT RED SGL 30MA 0603 1 D14 LITE ON LTST‐C190KRKT TRAN NMOS 60V 115MA SOT23 1 Q15 ON SEMI 2N7002LT1G DIODE TVS ARRAY 12A 5V 300W SOT23_S6 2 U15,U16 SEMTECH CORP SRV05‐4.TCT DIODE SCH 1A 20V SOD323 2 D8,D15 PHILIPS SEMI BAT760 TRAN NMOS DUAL 200MA 50V SOT363 4 Q9,Q10,Q11,Q12 DIODES INC BSS138DW‐7‐F
TRAN PMOS PWR 12V 4.3A SOT23 2 Q1,Q14 INTERNATIONAL RECTIFIER IRLML6401TRPBF
DIODE TVS ESD PROT ULT LOW CAP 5‐5.4V SOD‐923 1 D4 ON SEMI ESD9L5.0ST5G TRAN NMOS PWR 4.6A 30V DIODE SCHOTTKY 2.0A WDFN6 1 Q8 ON SEMI NTLJF4156NT1G TRAN PMOS PWR 4.1A 12V SOT‐23 1 Q7 VISHAY INT SI2333DS‐T1‐E3 DIODE TVS 2‐CH ARRAY 25A 5V 500W SOT‐143 2 D17,D18 SEMTECH CORP SR05.TCT FUSE PLYSW 1.1A HOLD 6V SMT ROHS 1 F2
TYCO ELECTRONICS MICROSMD110F‐2
FUSE CBKR 3A 24V 0603 1 F1 BOURNS SF‐0603F300‐2 SW SPST PB 50MA 12V SMT 4 SW2,SW3,SW4,SW5 E SWITCH TL1015AF160QG CON 22 RJ‐45/DUAL USB RA TH 50MIL SP 1231H AU 90L 1 J2
PREMIER MAGNETICS RJ45‐103YDD2
Table 34. Specified Components (con.)
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 121
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
NON‐POPULATED COMPONENTS Description QTY Reference Designator Manufacturer Part Number CAP CER 10PF 25V 5% C0G 0201 0 C168, C170 CAP CER 0.1UF 6.3V 10% X5R 0201 0 C163 CAP CER 2.2UF 50V 10% X7R 1206 0 C231 IND FER 120OHM@100MHZ 300MA 25% 0402 0 L3 MURATA BLM15HB121SN1D IND FER BEAD 220OHM@100MHZ 700MA 25% 0402 0 L22 MURATA BLM15EG221SN1_ CON 1X3 PLUG SHRD TH 1.25MM 165H SN 0 J14 MOLEX 0530470310 HDR 1X2 TH 100MIL SP 165H AU 0 J19 SAMTEC TLW‐102‐06‐G‐S HDR 1X1 TH ‐‐ 330H SN 115L 0 JP1, JP2 SAMTEC TSW‐101‐23‐T‐S IC DRV LVDS 1‐BIT HIGH SPEED DIFF 3.3V SOT23‐5 0 U11 FAIRCHILD FIN1001M5 MOSFET,DUAL N & P CHANNEL, SOT6 ROHS 0 Q13 FAIRCHILD FDC6321C_NL RES MF ZERO OHM 1/20W 5% 0201 0 R36, R38, R48, R197 RES MF ZERO OHM 1/16W 5% 0402 0 R210, R224 RES MF ZERO OHM 1/10W ‐‐ 0603 0 R80, R163 RES MF 0.02OHM 1/4W 0.5% 0805 0 R17, R20 RES MF 49.9 OHM 1/20W 1% 0201 0 R42, R43 RES TF 100 OHM 1/20W 5% RC0201 0 R111 RES MF 10K 1/20W 5% 0201 0 R84, R97, R108, R159,
R188, R189, R202
RES MF 200K 1/20W 5% 0201 0 R14 RES MF 10M 1/20W 5% 0201 0 R45 SW SPST DIP SMT 50V 100MA DIP10 0 SW1 Multicomp MCNHDS‐10‐T
Table 35. Non‐Populated Components
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 122
PUBI – Public Use Business Information
15. PCBinformation This section provides the Gerber artwork in a picture format for easy reference when using this document. The actual Gerber files are available from the i.MX53 Quick Start web site. The Gerber file package consists of all artwork files and additional supplemental files. The 14 artwork files are shown in the following figures: Figure 57. Top Etch Layer Figure 58. Second Etch Layer Figure 59. Third Etch Layer Figure 60. Fourth Etch Layer Figure 61. Fifth Etch Layer Figure 62. Sixth Etch Layer Figure 63. Seventh Etch Layer Figure 64. Bottom Etch Layer Figure 65. Soldermask Top Figure 66. Soldermask Bottom Figure 67. Pastemask Top Figure 68. Pastemask Bottom Figure 69. Silkscreen Top Figure 70. Silkscreen Bottom
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 123
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 57. Top Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 124
PUBI – Public Use Business Information
Figure 58. Second Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 125
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 59. Third Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 126
PUBI – Public Use Business Information
Figure 60. Fourth Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 127
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 61. Fifth Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 128
PUBI – Public Use Business Information
Figure 62. Sixth Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 129
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 63. Seventh Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 130
PUBI – Public Use Business Information
Figure 64. Bottom Etch Layer
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 131
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 65. Soldermask Top
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 132
PUBI – Public Use Business Information
Figure 66. Soldermask Bottom
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 133
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 67. Pastemask Top
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 134
PUBI – Public Use Business Information
Figure 68. Pastemask Bottom
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 135
PUBI – Public Use Business Information
Hardware Reference Manual for i.MX53 Quick Start
Figure 69. Silkscreen Top
Freescale Semiconductor Hardware User Guide for i.MX53 Quick Start Board, Preliminary Rev 0.91 136
PUBI – Public Use Business Information
Figure 70. Silkscreen Bottom
top related